Gabe Black
f61bb9adb9
ARM: Hook up the push/pop versions of stm/ldm in thumb.
2010-06-02 12:58:05 -05:00
Gabe Black
a76ab8e040
ARM: Hook SVC into the thumb decoder.
2010-06-02 12:58:05 -05:00
Gabe Black
cbdebf852e
ARM: Implement SVC (was SWI) outside of the decoder.
2010-06-02 12:58:05 -05:00
Gabe Black
34032f97d6
ARM: Trigger system calls from the SupervisorCall invoke method.
...
This simplifies the decoder slightly, and makes the system call mechanism
very slightly more realistic.
2010-06-02 12:58:05 -05:00
Gabe Black
52460938cb
ARM: Fix multiply operations.
...
These fixes were provided by Ali and fix the saturation condition code and
various multiply instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
4fb6fcd82d
ARM: Decode the scalar saturating add/subtract instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
30dd622622
ARM: Decode the parallel add and subtract instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
62e8487d57
ARM: Implement signed saturating add and/or subtract instructions.
2010-06-02 12:58:05 -05:00
Gabe Black
a1253ec644
ARM: Implemented prefetch instructions/decoding (pli, pld, pldw).
2010-06-02 12:58:05 -05:00
Gabe Black
61b00d3224
ARM: Decode unconditional ARM instructions.
2010-06-02 12:58:04 -05:00
Gabe Black
b6e2f5d33f
ARM: Make sure ldm exception return writes back its base in the right mode.
...
This change moves the writeback of load multiple instructions to the beginning
of the macroop. That way, the MicroLdrRetUop that changes the mode will
necessarily happen later, ensuring the writeback happens in the original mode.
The actual value in the base register if it also shows up in the register list
is undefined, so it's fine if it gets clobbered by one of the loads. For
stores where the base register is the lowest numbered in the register list,
the original value should be written back. That means stores can't write back
at the beginning, but the mode changing problem doesn't affect them so they
can continue to write back at the end.
2010-06-02 12:58:04 -05:00
Gabe Black
89060f1fd8
ARM: Rework how unrecognized/unimplemented instructions are handled.
...
Instead of panic immediately when these instructions are executed, an
UndefinedInstruction fault is returned. In FS mode (not currently
implemented), this is the fault that should, to my knowledge, be triggered in
these situations and should be handled using the normal architected
mechanisms. In SE mode, the fault causes a panic when it's invoked that gives
the same information as the instruction did. When/if support for speculative
execution of ARM is supported, this will allow a mispeculated and unrecognized
and/or unimplemented instruction from causing a panic. Only once the
instruction is going to be committed will the fault be invoked, triggering the
panic.
2010-06-02 12:58:04 -05:00
Gabe Black
aa45fafb2e
ARM: Add support for "SUBS PC, LR and related instructions".
2010-06-02 12:58:04 -05:00
Gabe Black
2419903dc0
ARM: Make ldrs into the PC and ldm exception return do interworking branches.
2010-06-02 12:58:04 -05:00
Gabe Black
28227440a7
ARM: Align the PC when using it as the base for a load.
2010-06-02 12:58:04 -05:00
Gabe Black
d63f748b53
ARM: Implement ADR as separate from ADD.
2010-06-02 12:58:04 -05:00
Gabe Black
e92dc21fde
ARM: Add support for interworking branch ALU instructions.
2010-06-02 12:58:04 -05:00
Gabe Black
11c3361be4
ARM: Fix when the flag bits are updated for thumb.
2010-06-02 12:58:04 -05:00
Gabe Black
14d25fbad0
ARM: Don't rely on undefined behavior to get arithmetic right shift.
...
Shifting to the right of a signed value when the MSB is one is technically
undefined behavior, even though in my experience it's done the "right thing"
and sign extended the value. This replaces the arithmetic right shift code in
ARM that uses that coincidence with some code that relies on bit math.
2010-06-02 12:58:04 -05:00
Gabe Black
05d880f7a1
ARM: Restrict the shift amount from a register to 8 bits.
...
The shift amount when taken from a register is supposed to be truncated to an
8 bit value.
2010-06-02 12:58:04 -05:00
Gabe Black
9ebaf8ecd5
ARM: Define the VFP load/store multiple instructions.
2010-06-02 12:58:04 -05:00
Gabe Black
3f83094af2
ARM: Decode the VFP load/store multiple instructions.
2010-06-02 12:58:04 -05:00
Gabe Black
647edea970
ARM: Fix the constant describing the number of floating point registers.
2010-06-02 12:58:04 -05:00
Gabe Black
2f3102f1ef
ARM: Add templates for VFP load/store multiple instructions.
2010-06-02 12:58:04 -05:00
Gabe Black
739f23c64c
ARM: Add base classes for VFP load/store multiple.
2010-06-02 12:58:04 -05:00
Gabe Black
cb631d87c3
ARM: Add floating point load/store microops.
2010-06-02 12:58:04 -05:00
Gabe Black
3a11412c99
ARM: Add an fp version of one of the microop indexed registers.
2010-06-02 12:58:04 -05:00
Gabe Black
d5aee75efe
ARM: Move the mmap region to where Linux actually has it.
2010-06-02 12:58:04 -05:00
Gabe Black
a8eb9d521c
ARM: Eliminate the unused rhi and rlo operands.
2010-06-02 12:58:03 -05:00
Gabe Black
b02c7f1bcd
ARM: Move the macro mem constructor out of the isa desc.
...
This code doesn't use the parser at all, and moving it out reduces the
conceptual complexity of that code.
2010-06-02 12:58:03 -05:00
Gabe Black
7b62e9ad71
ARM: Make macroops panic if executed directly.
...
The macroop should never be executed, only it's microops will.
2010-06-02 12:58:03 -05:00
Ali Saidi
8fadf2691d
ARM: GCC < 4.3 has some issues with attribute no return on some functions. Fix so it works for older gccs.
2010-06-02 12:58:03 -05:00
Gabe Black
f18040a205
ARM: Split out the "basic" templates and format.
...
--HG--
rename : src/arch/arm/isa/formats/basic.isa => src/arch/arm/isa/templates/basic.isa
2010-06-02 12:58:03 -05:00
Gabe Black
c175f1b993
ARM: Remove unnecessary cruft from includes.isa.
2010-06-02 12:58:03 -05:00
Gabe Black
e29ec7d2ed
ARM: Move the inst2string function out of the isa_desc.
...
Delete the now empty formats/util.isa.
2010-06-02 12:58:03 -05:00
Gabe Black
ae135228fc
ARM: Get rid of the unused ArmGenericCodeSubs.
2010-06-02 12:58:03 -05:00
Gabe Black
8c012e9571
ARM: Make the predecoder print out the ExtMachInst it gathered when traced.
2010-06-02 12:58:03 -05:00
Gabe Black
458bd025d4
ARM: Remove special naming for the new version of multiply.
2010-06-02 12:58:03 -05:00
Gabe Black
2196f75a25
ARM: Hook the new multiply instructions into all the decoders.
2010-06-02 12:58:03 -05:00
Gabe Black
33da368e99
ARM: Implement all integer multiply instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
50229be27f
ARM: Add templates for multiply instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
3430b34cff
ARM: Add base classes for multiply instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
c7d2f43641
ARM: Decode plain binary immediate thumb data processing instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
dcf218155d
ARM: Define a new "movt" data processing instruction.
2010-06-02 12:58:03 -05:00
Gabe Black
b615ed1470
ARM: Hook the new branch instructions into the 32 bit thumb decoder.
2010-06-02 12:58:03 -05:00
Gabe Black
274badd201
ARM: Hook the new branch instructions into the 16 bit thumb decoder.
2010-06-02 12:58:03 -05:00
Gabe Black
b6b2f8891a
ARM: Eliminate the old style branch instructions.
2010-06-02 12:58:03 -05:00
Gabe Black
d082705b01
ARM: Hook the new branch instructions into the ARM decoder.
2010-06-02 12:58:02 -05:00
Gabe Black
9869343636
ARM: Implement branch instructions external to the decoder.
2010-06-02 12:58:02 -05:00
Gabe Black
a6c1c8debb
ARM: Add new templates for branch instructions.
2010-06-02 12:58:02 -05:00
Gabe Black
ef3972eaae
ARM: Implement new base classes for branches.
2010-06-02 12:58:02 -05:00
Gabe Black
769f3406fe
ARM: Replace the interworking branch base class with a special operand.
2010-06-02 12:58:02 -05:00
Gabe Black
b6e7029dd5
ARM: Fix PC operand handling.
2010-06-02 12:58:02 -05:00
Gabe Black
7eb3ea2798
ARM: Remove the special naming from the new version of data processing instructions.
2010-06-02 12:58:02 -05:00
Gabe Black
4f08b52af2
ARM: Get rid of unnecessary flag calculating functions.
2010-06-02 12:58:02 -05:00
Gabe Black
bf903ec9a1
ARM: Get rid of the unused Jump format.
2010-06-02 12:58:02 -05:00
Gabe Black
36ca0658a4
ARM: Get rid of obsoleted predicated inst formats, etc.
2010-06-02 12:58:02 -05:00
Gabe Black
7939b48265
ARM: Implement disassembly for the new data processing classes.
2010-06-02 12:58:02 -05:00
Gabe Black
b66e3aec43
ARM: Hook the external data processing instructions into the Thumb decoder.
2010-06-02 12:58:02 -05:00
Gabe Black
beb759912b
ARM: Move the modified_imm function from all ARM instructions to just data processing ones.
2010-06-02 12:58:02 -05:00
Gabe Black
8136cb3605
ARM: Hook the new external data processing instructions to the ARM decoder.
2010-06-02 12:58:02 -05:00
Gabe Black
bf45d44cbe
ARM: Implement data processing instructions external to the decoder.
2010-06-02 12:58:02 -05:00
Gabe Black
c02f9cdddf
ARM: Add new base classes for data processing instructions.
2010-06-02 12:58:02 -05:00
Gabe Black
1e7b317a98
ARM: Hook up 32 bit thumb load/store multiple.
2010-06-02 12:58:02 -05:00
Gabe Black
64d6b6ebfd
ARM: Hook up 16 bit thumb load/store multiple.
2010-06-02 12:58:02 -05:00
Gabe Black
51bde086d5
ARM: Reimplement load/store multiple external to the decoder.
...
--HG--
rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/insts/macromem.isa
rename : src/arch/arm/isa/formats/macromem.isa => src/arch/arm/isa/templates/macromem.isa
2010-06-02 12:58:02 -05:00
Gabe Black
93a3714816
ARM: Move the templates for predicated instructions into a separate file.
...
This allows the templates to all be available at the same time before any of
the formats, etc. This breaks an artificial circular dependence.
--HG--
rename : src/arch/arm/isa/formats/pred.isa => src/arch/arm/isa/templates/pred.isa
2010-06-02 12:58:01 -05:00
Gabe Black
04300e33d4
ARM: Remove the special naming for the new memory instructions.
...
These are the only memory instructions now.
2010-06-02 12:58:01 -05:00
Gabe Black
deb6e8f805
ARM: Eliminate the old memory formats which are no longer used.
2010-06-02 12:58:01 -05:00
Gabe Black
1905024766
ARM: Eliminate decoding for the very deprecated FPA instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
55465844dc
ARM: Make the addressing mode 3 loads/stores use the externally defined instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
36b6ca2ce3
ARM: Pull double memory instructions out of the decoder.
2010-06-02 12:58:01 -05:00
Gabe Black
79b288f7b5
ARM: Force the condition code for 16 bit thumb instructions to be unconditional.
...
Before, because 16 bit thumb instructions didn't set the upper 16 bits of the
ExtMachInst, that field would be interpretted as "equals".
2010-06-02 12:58:01 -05:00
Gabe Black
a86491fbf2
ARM: Decode 16 bit thumb PC relative memory instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
dc8af1b211
ARM: Decode 16 bit thumb immediate addressed memory instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
4bbd73649d
ARM: Decode 16 bit thumb register addressed memory instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
462cf6f49b
ARM: Make single stores decode to the new external store instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
3b0f3b1ee2
ARM: Add a .w to the disassembly of 32 bit thumb instructions.
...
This isn't technically correct since the .w should only be added if there are
32 and 16 bit encodings, but always having it always is better than never
having it.
2010-06-02 12:58:01 -05:00
Gabe Black
fde3c8f41d
ARM: Make 32 bit thumb use the new, external load instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
3b93015304
ARM: Define the store instructions from outside the decoder.
...
--HG--
rename : src/arch/arm/isa/insts/ldr.isa => src/arch/arm/isa/insts/str.isa
2010-06-02 12:58:01 -05:00
Gabe Black
81fdced83f
ARM: Define the load instructions from outside the decoder.
2010-06-02 12:58:01 -05:00
Gabe Black
321d3a6e8c
ARM: Implement a new set of base classes for non macro memory instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
8933857af7
ARM: Create a "decoder" directory for the files implementing the decoder.
...
--HG--
rename : src/arch/arm/isa/armdecode.isa => src/arch/arm/isa/decoder/arm.isa
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/decoder/decoder.isa
rename : src/arch/arm/isa/thumbdecode.isa => src/arch/arm/isa/decoder/thumb.isa
rename : src/arch/arm/isa/vfpdecode.isa => src/arch/arm/isa/decoder/vfp.isa
2010-06-02 12:58:01 -05:00
Gabe Black
4ebd44dc4f
ARM: Flesh out the 32 bit thumb store single instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
386424ccb5
ARM: Implement the 32 bit thumb load word instructions.
2010-06-02 12:58:01 -05:00
Gabe Black
292b8a3c91
ARM: Add an operand for accessing the current PC.
2010-06-02 12:58:00 -05:00
Gabe Black
003346077f
ARM: Flesh out 32 bit thumb load word decoding.
2010-06-02 12:58:00 -05:00
Gabe Black
0d4c4cacab
ARM: Implement some 32 bit thumb data processing immediate instructions.
2010-06-02 12:58:00 -05:00
Gabe Black
bd8812cf99
ARM: Replace the "never" condition with the "unconditional" condition.
2010-06-02 12:58:00 -05:00
Gabe Black
af91d27271
ARM: Add a base class for 32 bit thumb data processing immediate instructions.
2010-06-02 12:58:00 -05:00
Gabe Black
bfe1a194dd
ARM: Add a function to decode 32 bit thumb immediate values.
2010-06-02 12:58:00 -05:00
Gabe Black
0116655674
ARM: Expand the decoding for 32 bit thumb data processing immediate instructions.
2010-06-02 12:58:00 -05:00
Gabe Black
cef2e8ecee
ARM: Stub out the 32 bit Thumb portion of the decoder.
2010-06-02 12:58:00 -05:00
Gabe Black
659f8d021f
ARM: Add bitfields for 32 bit thumb.
2010-06-02 12:58:00 -05:00
Gabe Black
bc6ae010c9
ARM: Decode VFP instructions.
2010-06-02 12:58:00 -05:00
Gabe Black
7b8525287d
ARM: Stub out the 16 bit thumb decoder.
2010-06-02 12:58:00 -05:00
Gabe Black
aaa619ea23
ARM: Add thumb bitfields to the ExtMachInst and the isa definition.
2010-06-02 12:58:00 -05:00
Gabe Black
a1838f2c79
ARM: Make the decoder handle thumb instructions separately.
...
--HG--
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/armdecode.isa
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/thumbdecode.isa
2010-06-02 12:58:00 -05:00
Gabe Black
0dffd8ce79
ARM: Add a thumb bit bitfield.
2010-06-02 12:58:00 -05:00
Gabe Black
96be7e16c1
ARM: Make the predecoder handle Thumb instructions.
2010-06-02 12:58:00 -05:00
Gabe Black
f49cdb4f5d
ARM: Make sure ExtMachInst is used consistently instead of regular MachInst.
2010-06-02 12:58:00 -05:00
Gabe Black
330d9d4dbc
ARM: Add a bitfield for setting the regular, inst bits of an ExtMachInst.
2010-06-02 12:58:00 -05:00
Gabe Black
a59d219989
ARM: Add a bit to the ExtMachInst to select thumb mode.
2010-06-02 12:58:00 -05:00
Gabe Black
4ddeceba96
ARM: Allow ARM processes to start in Thumb mode.
2010-06-02 12:58:00 -05:00
Gabe Black
3951afd2fa
ARM: Detect thumb mode elf images.
2010-06-02 12:58:00 -05:00
Gabe Black
ebb273bb7b
ARM: Add a new base class for instructions that can do an interworking branch.
2010-06-02 12:57:59 -05:00
Gabe Black
9ef82c0bc4
ARM: Track the current ISA mode using the PC.
2010-06-02 12:57:59 -05:00
Gabe Black
1c0d9806e5
ARM: Fix custom writer/reader code for non indexed operands.
2010-06-02 12:57:59 -05:00
Gabe Black
4b87bc887a
ARM: Remove IsControl from operands that don't imply control transfers.
...
Also remove IsInteger from CondCodes.
2010-06-02 12:57:59 -05:00
Ali Saidi
322f345b51
ARM: Adjust some copyrights
2010-06-02 12:57:59 -05:00
Nathan Binkert
c1aabe8172
style: clean up ruby's Set class
...
Further cleanup should probably be done to make this class be non-Ruby
specific and put it in src/base.
There are probably several cases where this class is used, std::bitset
could be used instead.
2010-06-01 11:38:56 -07:00
Nathan Binkert
bb589d463b
x86: put back code that I accidentally deleted
2010-05-25 20:15:44 -07:00
Nathan Binkert
13d64906c2
copyright: Change HP copyright on x86 code to be more friendly
2010-05-23 22:44:15 -07:00
Gabe Black
c5c559b6ab
SPARC: Implement the version of movcc that uses the fp condition codes.
2010-05-14 14:22:51 -07:00
Ali Saidi
72071690e7
Automated merge with ssh://m5sim.org//repo/m5
2010-05-13 23:48:06 -04:00
Maximilien Breughe
fc746c2268
BPRED: Fixed the treshold-bug in the tournament predictor.
...
Suppose the saturating counters of a branch predictor contain n bits. When the
counter is between 0 and (2^(n-1) - 1), boundaries included, the branch is
predicted as not taken. When the counter is between 2^(n-1) and (2^n - 1),
boundaries included, the branch is predicted as taken.
2010-05-13 23:45:57 -04:00
Gabe Black
c4497dbf03
X86: Make the cvti2f microop sign extend its integer source correctly.
...
The code was using the wrong bit as the sign bit. Other similar bits of code
seem to be correct.
2010-05-12 00:51:35 -07:00
Gabe Black
cc76842f83
X86: Actual change that fixes div. How did that happen?
2010-05-12 00:49:12 -07:00
Nathan Binkert
c4057a13f1
macos: MacOS has deprecated getdirentries, so just disable the code.
...
Hopefully it isn't used much
2010-05-06 08:42:21 -07:00
Nathan Binkert
f07ee128cc
compile: don't #include unnecessary stuff
...
Time from base/time.hh has a name clash with Time from Ruby's
TypeDefines.hh. Eventually Ruby's Time should go away, so instead of
fixing this properly just try to avoid the clash.
2010-05-06 08:42:18 -07:00
Gabe Black
2ee7a89209
X86: Update the base aux vector X86 processes install.
2010-05-03 00:44:08 -07:00
Gabe Black
7524fdda6a
X86: Sometimes CPUID depends on ecx, so pass that in.
2010-05-02 00:40:17 -07:00
Gabe Black
51a3d65e25
X86: Finally fix a division corner case.
...
When doing an unsigned 64 bit division with a divisor that has its most
significant bit set, the division code would spill a bit off of the end of a
uint64_t trying to shift the dividend into position. This change adds code
that handles that case specially by purposefully letting it spill and then
going ahead assuming there was a 65th one bit.
2010-05-02 00:39:29 -07:00
Nathan Binkert
82fb350f9a
stats: make simTicks and simFreq accessible from stats.hh
2010-04-18 13:23:25 -07:00
Nathan Binkert
50bf3895b0
callback: Make helper functions that create callback objects for you
...
clean up callback stuff a little bit while we're at it.
2010-04-18 13:23:25 -07:00
Nathan Binkert
12fc22571c
event: Allow EventWrapper to take an object reference
2010-04-18 13:23:24 -07:00
Nathan Binkert
4225a68a95
scons: don't maintain files in sorted order
...
This causes builds to happen in sorted order rather than in
declaration order. This gets annoying when you make a global change
and then you notice that the files that are being compiled are jumping
around the directory hierarchy.
2010-04-15 16:25:14 -07:00
Nathan Binkert
e99828b06a
tick: rename Clock namespace to SimClock
2010-04-15 16:24:12 -07:00
Nathan Binkert
f7e6f19ada
eventq: move EventQueue constructor to cc file
...
Also make copy constructor and assignment operator private.
2010-04-15 16:24:10 -07:00
Korey Sewell
b49511ae48
inorder: timing for inst forwarding
...
when insts execute, they mark the time they finish to be used for subsequent isnts
they may need forwarding of data. However, the regdepmap was using the wrong
value to index into the destination operands of the instruction to be forwarded.
Thus, in some cases, we are checking to see if the 3rd destination register
for an instruction is executed at a certain time, when there is only 1 dest. register
valid. Thus, we get a bad, uninitialized time value that will stall forwarding
causing performance loss but still the correct execution.
2010-04-10 23:31:36 -04:00
Nathan Binkert
d71f9712b3
eventq: allow an implicit cast from an EventManager to an EventQueue *
2010-04-02 15:28:22 -07:00
Nathan Binkert
f32674d9bc
eventq: Clean up some flags
...
- Make the initialized flag always available, not just in debug mode.
- Make the Initialized flag actually use several bits so it is very
unlikely that something that's uninitialized accidentally looks
initialized.
- Add an initialized() function that tells you if the current event is
indeed initialized.
- Clear the flags on delete so it can't be accidentally thought of as
initialized.
- Fix getFlags assert statement. "How did this ever work?"
2010-04-02 15:28:22 -07:00
Nathan Binkert
2ee3edba8e
eventq: Make priorities just an integer instead of an enum.
...
Symbolic names should still be used, but this makes it easier to do
things like:
Event::Priority MyObject_Pri = Event::Default_Pri + 1
Remember that higher numbers are lower priority (should we fix this?)
2010-04-02 15:28:21 -07:00
Nathan Binkert
01dffaa32f
refcnt: no default copy contructor or copy operator
...
We shouldn't allow these because the default versions will copy
the reference count which is definitely not what we want.
2010-04-02 11:20:32 -07:00
Nathan Binkert
141f61d83a
ruby: get rid of gems_common/util.hh and .cc and use stuff in src/base
2010-04-02 11:20:32 -07:00
Nathan Binkert
f1c3f3044b
ruby: get "using namespace" out of headers
...
In addition to obvious changes, this required a slight change to the slicc
grammar to allow types with :: in them. Otherwise slicc barfs on std::string
which we need for the headers that slicc generates.
2010-04-02 11:20:32 -07:00
Nathan Binkert
be10204729
style: another ruby style pass
2010-03-31 16:56:45 -07:00
Nathan Binkert
60ae1d2b10
style: cleanup the Ruby Tester
2010-03-29 20:39:02 -04:00
Korey Sewell
1c98bc5a56
m5: merge inorder updates
2010-03-27 02:23:00 -04:00
Korey Sewell
ac316d45e8
inorder: write-hints bug fix
...
make sure to only read 1 src reg. for write-hint and any other similar
'store' instruction. Reading the source reg when its not necessary
can cause the simulator to read from uninitialized values
2010-03-27 01:40:05 -04:00
Timothy M. Jones
6b293c73fd
CPU: Added comments to address translation classes.
2010-03-25 12:43:52 +00:00
Nathan Binkert
a2652a048a
ruby: continue style pass
2010-03-23 22:49:43 -07:00
Steve Reinhardt
f066bfc2f5
cpu: get rid of uncached access "events"
...
These recordEvent() calls could cause crashes since they
access the req pointer after it's potentially been
deleted during a failed translation call. (Similar
problem to the traceData bug fixed in the previous cset.)
Moving them above the translation call (as was done
recentlyi in cset 8b2b8e5e7d35) avoids the crash
but doesn't work, since at that point we don't know if
the access is uncached or not.
It's not clear why these calls are there, and no one
seems to use them, so we'll just delete them. If they
are needed, they should be moved to somewhere that's
guaranteed to be after the translation completes but
before the request is possibly deleted, e.g., in
finishTranslation().
2010-03-23 08:50:59 -07:00
Steve Reinhardt
4d77ea7a57
cpu: fix exec tracing memory corruption bug
...
Accessing traceData (to call setAddress() and/or setData())
after initiating a timing translation was causing crashes,
since a failed translation could delete the traceData
object before returning.
It turns out that there was never a need to access traceData
after initiating the translation, as the traced data was
always available earlier; this ordering was merely
historical. Furthermore, traceData->setAddress() and
traceData->setData() were being called both from the CPU
model and the ISA definition, often redundantly.
This patch standardizes all setAddress and setData calls
for memory instructions to be in the CPU models and not
in the ISA definition. It also moves those calls above
the translation calls to eliminate the crashes.
2010-03-23 08:50:57 -07:00
Nathan Binkert
5ab13e2deb
ruby: style pass
2010-03-22 18:43:53 -07:00
Korey Sewell
2620e08722
inorder: import name for addtl. bpred stats
2010-03-22 17:19:48 -04:00
Maximilien Breughe
0170e851de
inorder: fix squash bug in branch predictor
2010-03-22 16:59:12 -04:00
Korey Sewell
4ac245737d
inorder: fix address list bug
2010-03-22 15:38:28 -04:00
Brad Beckmann
66632539b6
ruby: improved isReadWrite fix me comment
2010-03-22 11:19:17 -07:00
Brad Beckmann
b55e69ccac
ruby: Removed the unnecessary MachineType message fields
2010-03-21 21:22:22 -07:00
Brad Beckmann
898f1fc4a4
ruby: Reorganized Ruby topology and protocol files
...
--HG--
rename : configs/ruby/MESI_CMP_directory.py => configs/ruby/protocols/MESI_CMP_directory.py
rename : configs/ruby/MI_example.py => configs/ruby/protocols/MI_example.py
rename : configs/ruby/MOESI_CMP_directory.py => configs/ruby/protocols/MOESI_CMP_directory.py
rename : configs/ruby/MOESI_CMP_token.py => configs/ruby/protocols/MOESI_CMP_token.py
rename : configs/ruby/MOESI_hammer.py => configs/ruby/protocols/MOESI_hammer.py
rename : configs/ruby/networks/MeshDirCorners.py => src/mem/ruby/network/topologies/MeshDirCorners.py
2010-03-21 21:22:22 -07:00
Brad Beckmann
f3cdc0d5a3
ruby: Disable adaptive routing by for faster simulation perf.
2010-03-21 21:22:21 -07:00
Brad Beckmann
f9408f984f
ruby: Changed the default set size to 1
...
Previously, the set size was set to 4. This was mostly do to the fact that a
crazy graduate student use to create networks with 256 l2 cache banks. Now it
is far more likely that users will create systems with less than 64 of any
particular controller type. Therefore Ruby should be optimized for a set size
of 1.
2010-03-21 21:22:21 -07:00
Brad Beckmann
61f1d9a3d7
ruby: Reordered protocol buffers
...
Reordered vnet priorities to agree with PerfectSwitch for protocols MI_example,
MOESI_CMP_token, and MOESI_hammer
2010-03-21 21:22:21 -07:00
Brad Beckmann
4f044605e8
ruby: Adds configurable bit selection for numa mapping
2010-03-21 21:22:21 -07:00
Brad Beckmann
8b15ed7ebf
ruby: Added flag to disable mem_vec allocation
...
The RubySystem flag no_mem_vec will disable Ruby from allocating it's memory
data array.
2010-03-21 21:22:21 -07:00
Brad Beckmann
92cfd1cac7
ruby: Ruby support for sparse memory
...
The patch includes direct support for the MI example protocol.
2010-03-21 21:22:21 -07:00
Brad Beckmann
b5e4c3cbf2
ruby: Finally removed bash code cira. 2001ish!
2010-03-21 21:22:21 -07:00
Brad Beckmann
6d22db4eaa
ruby: Ruby support for LLSC
2010-03-21 21:22:21 -07:00
Brad Beckmann
f53287f9ad
ruby: Minor dma latency initialization fix
2010-03-21 21:22:21 -07:00
Tushar Krishna
7c20d5511a
ruby: Fix multiple wakeups in Ruby Eventqueue
...
Fix bug in Ruby Event queue to avoid multiple wakeups of same consumer in
same cycle
2010-03-21 21:22:21 -07:00
Brad Beckmann
103f5a2c94
ruby: Removed the obsolete file specified network files
2010-03-21 21:22:21 -07:00
Brad Beckmann
d464087101
ruby: Added copyright to many Ruby *.py files
2010-03-21 21:22:20 -07:00
Brad Beckmann
378fbce911
ruby: Fixed small data msg bug in MOESI_hammer-dir
2010-03-21 21:22:20 -07:00
Brad Beckmann
4ee3b0da45
TimingSimpleCPU: Fixed uncacacheable request read bug
...
Previously the recording of an uncached read occurred after the request was
possibly deleted within the translateTiming function.
2010-03-21 21:22:20 -07:00
Brad Beckmann
0368ef915a
ruby: Removed the no longer used rubymem files
2010-03-21 21:22:20 -07:00
Brad Beckmann
c48a735336
ruby: Fix MOESI_hammer cache profiler calls for L2 misses
2010-03-21 21:22:20 -07:00
Brad Beckmann
391b4e64e6
ruby: Removed deprecated stats from the main profiler
2010-03-21 21:22:20 -07:00
Nathan Binkert
86207a69e4
orion: Make declarations match definition
2010-03-16 08:15:16 -07:00
Nathan Binkert
edb59ed263
ruby: Fix copyrights on files
...
Mostly files missed during import or screwed up during import
2010-03-14 20:58:45 -07:00
Nathan Binkert
0bbf63f17a
slicc: Change the code generation so that the generated code is easier to read
2010-03-12 18:42:56 -08:00
Nathan Binkert
c8f296bca0
packet: add a method to set the size
2010-03-12 17:31:08 -08:00
Nathan Binkert
671faf3316
eventq: rearrange a little bit so I can add some stuff
2010-03-12 17:31:04 -08:00
Nathan Binkert
402f42ebfa
eventq: remove some unused includes
2010-03-12 17:31:02 -08:00
Nathan Binkert
fce7c820f4
bugfix: since pow() causes a bug don't use it
...
It's a power of two anyway, so why use it in the first place.
2010-03-12 15:11:09 -08:00
Nathan Binkert
140785d24c
ruby: get rid of std-includes.hh
...
Do not use "using namespace std;" in headers
Include header files as needed
2010-03-10 18:33:11 -08:00
Nathan Binkert
1badec39a9
ruby: remove calc_host.diff since we don't use it
2010-03-10 16:22:27 -08:00
Nathan Binkert
226eaf9ddf
ruby: get rid of the ioutil stuff since it isn't used anymore
2010-03-10 16:22:26 -08:00
Nathan Binkert
cf86532857
slicc: have a central mechanism for creating a code_formatter.
...
This makes it easier to add global variables like protocol
2010-03-10 16:22:26 -08:00
Nathan Binkert
1068ca85d0
scons: import ply to work around scons sys.path weirdness
2010-03-10 15:39:34 -08:00
Nathan Binkert
25aac791de
SmartDict: Make SmartDict an attrdict
2010-02-28 19:28:09 -08:00
Nathan Binkert
ebdd004eb2
uart: use integer versions of time instead of messing around with floats
2010-02-28 19:28:09 -08:00
Nathan Binkert
f0b4259e98
cpu_models: get rid of cpu_models.py and move the stuff into SCons
2010-02-26 18:14:48 -08:00
Nathan Binkert
ac106767c8
isa_parser: Make SCons import the isa_parser
...
this is instead of forking a new interpreter
2010-02-26 18:14:48 -08:00
Nathan Binkert
629e8df196
isa_parser: move the operand map stuff into the ISAParser class.
2010-02-26 18:14:48 -08:00
Nathan Binkert
4db57edade
isa_parser: move more support functions into the ISAParser class
2010-02-26 18:14:48 -08:00
Nathan Binkert
5ad139375e
isa_parser: move more stuff into the ISAParser class
2010-02-26 18:14:48 -08:00
Nathan Binkert
4ef6e129d6
isa_parser: move the formatMap and exportContext into the ISAParser class
2010-02-26 18:14:48 -08:00
Nathan Binkert
4e105f6fe1
isa_parser: Make stack objects class members instead of globals
2010-02-26 18:14:48 -08:00
Nathan Binkert
b4178b1ae7
isa_parser: add a debug variable that changes how errors are reported.
...
This allows us to get tracebacks in certain cases where they're more
useful than our error message.
2010-02-26 18:14:48 -08:00
Nathan Binkert
40a05f04fb
isa_parser: Use an exception to flag error
...
This allows the error to propagate more easily
2010-02-26 18:14:48 -08:00
Nathan Binkert
f82a92925c
isa_parser: Move more stuff into the ISAParser class
2010-02-26 18:14:48 -08:00
Nathan Binkert
f7a627338c
isa_parser: move code around to prepare for putting more stuff in the class
2010-02-26 18:14:48 -08:00
Nathan Binkert
eb4ce01056
isa_parser: simple fixes, formatting and style
2010-02-26 18:14:48 -08:00
Nathan Binkert
a9f6c8edc3
events: Give EventWrapped a default name and description
2010-02-26 18:09:41 -08:00
Lisa Hsu
7f3cd9a9fd
cache stats: account for writebacks and/or device occupancy in the cache.
...
Plus, a minor bugfix that neglects to update blk->contextSrc in certain cases on a cache insert.
2010-02-24 13:46:55 -08:00
Lisa Hsu
1d3228481f
cache: Make caches sharing aware and add occupancy stats.
...
On the config end, if a shared L2 is created for the system, it is
parameterized to have n sharers as defined by option.num_cpus. In addition to
making the cache sharing aware so that discriminating tag policies can make use
of context_ids to make decisions, I added an occupancy AverageStat and an occ %
stat to each cache so that you could know which contexts are occupying how much
cache on average, both in terms of blocks and percentage. Note that since
devices have context_id -1, having an array of occ stats that correspond to
each context_id will break here, so in FS mode I add an extra bucket for device
blocks. This bucket is explicitly not added in SE mode in order to not only
avoid ugliness in the stats.txt file, but to avoid broken stats (some formulas
break when a bucket is 0).
2010-02-23 09:34:22 -08:00
Lisa Hsu
be4cf50c5a
stats: this makes some fixes to AverageStat and AverageVector.
...
Also, make Formulas work on AverageVector. First, Stat::Average (and thus
Stats::AverageVector) was broken when coming out of a checkpoint and on resets,
this fixes that. Formulas also didn't work with AverageVector, but added
support for that.
2010-02-23 09:33:18 -08:00
Lisa Hsu
2ad386f104
cache: pull CacheSet out of LRU so that other tags can use associative sets.
2010-02-23 09:33:09 -08:00
Timothy M. Jones
a5feaa6a69
BaseDynInst: Preserve the faults returned from read and write.
...
When implementing timing address translations instead of atomic, I
forgot to preserve the faults that are returned from the read and
write calls. This patch reinstates them.
2010-02-20 20:11:58 +00:00
Timothy M. Jones
29e8bcead5
O3PCU: Split loads and stores that cross cache line boundaries.
...
When each load or store is sent to the LSQ, we check whether it will cross a
cache line boundary and, if so, split it in two. This creates two TLB
translations and two memory requests. Care has to be taken if the first
packet of a split load is sent but the second blocks the cache. Similarly,
for a store, if the first packet cannot be sent, we must store the second
one somewhere to retry later.
This modifies the LSQSenderState class to record both packets in a split
load or store.
Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA
to indicate whether unaligned memory accesses are allowed. This is used
throughout the changed code so that compiler can optimise away code dealing
with split requests for ISAs that don't need them.
2010-02-12 19:53:20 +00:00
Timothy M. Jones
7fe9f92cfc
BaseDynInst: Make the TLB translation timing instead of atomic.
...
This initiates a timing translation and passes the read or write on to the
processor before waiting for it to finish. Once the translation is finished,
the instruction's state is updated via the 'finish' function. A new
DataTranslation class is created to handle this.
The idea is taken from the implementation of timing translations in
TimingSimpleCPU by Gabe Black. This patch also separates out the timing
translations from this CPU and uses the new DataTranslation class.
2010-02-12 19:53:19 +00:00
Timothy M. Jones
dd60902152
Power ISA: Add an alignment fault to Power ISA and check alignment in TLB.
2010-02-12 19:53:19 +00:00
Brad Beckmann
64999b4343
ruby: fixed data block assignment fix
...
Fixed data block assignment to not delete if not internally allocated.
2010-02-10 16:40:54 -08:00
Brad Beckmann
714865e4a4
ruby: Initialize sender in MI_example-dir
2010-02-10 16:40:54 -08:00
Brad Beckmann
a407675106
ruby: Fixed slicc to initialize the m_is_blocking flag
2010-02-10 16:40:54 -08:00
Brad Beckmann
1d4c3ecdc3
ruby: Added FS support to the simple mesh topology
...
Added full-system support to the simple mesh toplogy by allowing dma contrllers
to be attached to router zero in the network.
2010-02-01 14:27:16 -08:00
Brad Beckmann
db2ecbb6b6
ruby: Set default protocol back to MI_example
2010-02-01 11:07:38 -08:00
Korey Sewell
c7f6e2661c
inorder: double delete inst bug
...
Make sure that instructions are dereferenced/deleted twice by marking they are
on the remove list
2010-01-31 18:30:59 -05:00
Korey Sewell
9357e353fc
inorder: inst count mgmt
2010-01-31 18:30:48 -05:00
Korey Sewell
be6724f7e7
inorder: implement split stores
2010-01-31 18:30:43 -05:00
Korey Sewell
6939482c49
inorder: implement split loads
2010-01-31 18:30:35 -05:00
Korey Sewell
ea8909925f
inorder: add activity stats
2010-01-31 18:30:24 -05:00
Korey Sewell
f3bc2df663
inorder: object cleanup in destructors
2010-01-31 18:30:08 -05:00
Korey Sewell
1a89e8f4cb
inorder: user per-thread dummy insts/reqs
2010-01-31 18:29:59 -05:00
Korey Sewell
002f1b8b7e
inorder: add execution unit stats
2010-01-31 18:29:49 -05:00
Korey Sewell
82c5a754e6
inorder: recvRetry bug fix
...
- on certain retry requests you can get an assertion failure
- fix by allowing the request to literally "Retry" itself
if it wasnt successful before, and then block any requests
through cache port while waiting for the cache to be
made available for access
2010-01-31 18:29:18 -05:00
Korey Sewell
349d86c0e4
inorder-stats: add prereq to basic stat
...
only show requests processed when the resource is actually in use
2010-01-31 18:29:06 -05:00
Korey Sewell
0b29c2d057
inorder: ctxt switch stats
...
- m5 line enforcement on use_def.cc,hh
2010-01-31 18:28:59 -05:00
Korey Sewell
ffa9ecb1fa
inorder: pipeline stage stats
...
add idle/run/utilization stats for each pipeline stage
2010-01-31 18:28:51 -05:00
Korey Sewell
4d749472e3
inorder: enforce stage bandwidth
...
each stage keeps track of insts_processed on a per_thread basis but we should
be keeping that on a total basis inorder to enforce stage width limits
2010-01-31 18:28:31 -05:00
Korey Sewell
b4e0ef7837
inorder: set thread status'
...
set Active/Suspended/Halted status for threads. useful for system when determining
if/when to exit simulation
2010-01-31 18:28:12 -05:00
Korey Sewell
5e0b8337ed
inorder: add/remove halt/deallocate context respectively
...
Halt is called from the exit() system call while
deallocate is unused. So to clear up things, just
use halt and remove deallocate.
2010-01-31 18:28:05 -05:00
Korey Sewell
069b38c0d5
inorder: track last branch committed
...
when threads are switching in/out the CPU, we need to keep
track of special cases like branches. Add appropriate
variables in ThreadState t track this and then use
these variables when updating pc after context switch
2010-01-31 18:27:58 -05:00
Korey Sewell
aacc5cb205
inorder: add updatePC event to resPool
...
this will be used for when a thread comes back from a cache miss, it needs to update the PCs
because the inst might of been a branch or delayslot in which the next PC isnt always
a straight addition
2010-01-31 18:27:49 -05:00
Korey Sewell
90d3b45a56
inorder: ready thread wakeup
...
allow a thread to wakeup and be activated after
it has been in suspended state and another
thread is switched out. Need to give
pipeline stages a "activateThread" function
so that can get to their suspended instruction
when the time is right.
2010-01-31 18:27:38 -05:00
Korey Sewell
3eb04b4ad7
inorder: add threadmodel flag
...
this prints out messages relative to what
threading model is being used (smt, switch-on-miss, single, etc.)
2010-01-31 18:27:25 -05:00
Korey Sewell
611a8642c2
inorder: mem. mgmt. update
...
update address List and address Map to take
into account multiple threads
2010-01-31 18:27:12 -05:00
Korey Sewell
4dbc2f1718
inorder: suspend in respool
...
give resources their own specific
activity to do for a "suspend" event
instead of defaulting to deactivating the thread for a
suspend thread event. This really matters
for the fetch sequence unit which wants to remove the
thread from fetching while other units want to
ignore a thread suspension. If you deactivate a thread
in a resource then you may lose some of the allotted
bandwidth that the thread is taking up...
2010-01-31 18:27:02 -05:00
Korey Sewell
4ea296e296
inorder: fetch thread bug
...
dont check total # of threads but instead all
active threads
2010-01-31 18:26:54 -05:00
Korey Sewell
96b493d315
inorder: ready/suspend status fns
...
update/add in the use of isThreadReady & isThreadSuspended
functions.Check in activateThread what list a thread is
on so it can be managed accordingly.
2010-01-31 18:26:47 -05:00
Korey Sewell
d9eaa2fe21
inorder-cleanup: remove unused thread functions
2010-01-31 18:26:40 -05:00
Korey Sewell
e1fcc64980
inorder: activate thread on cache miss
...
-Support ability to activate next ready thread after a cache miss
through the activateNextReadyContext/Thread() functions
-To support this a "readyList" of thread ids is added
-After a cache miss, thread will suspend and then call
activitynextreadythread
2010-01-31 18:26:32 -05:00
Korey Sewell
4a945aab19
inorder: add event priority offset
...
allow for events to schedule themselves later if desired. this is important
because of cases like where you need to activate a thread only after the previous
thread has been deactivated. The ordering there has to be enforced
2010-01-31 18:26:26 -05:00
Korey Sewell
eac5eac67a
inorder: squash on memory stall
...
add code to recognize memory stalls in resources and the pipeline as well
as squash a thread if there is a stall and we are in the switch on cache miss
model
2010-01-31 18:26:13 -05:00
Korey Sewell
d8e0935af2
inorder: add insts to cpu event
...
some events are going to need instruction data when they process, so just
include the instruction in the event construction
2010-01-31 18:26:03 -05:00
Korey Sewell
e8312ab6f7
inorder: switch out buffer
...
add buffer for instructions to switch out to in a pipeline stage
can't squash the instruction and remove the pipeline so we kind of need
to 'suspend' an instruction at the stage while the memory stall resolves
for the switch on cache miss model
2010-01-31 18:25:48 -05:00
Korey Sewell
a892af7b26
inorder: dont allow early loads
...
- loads were happening on same cycle as the address was generated which is slightly
unrealistic. Instead, force address generation to be on separate cycle from load
initiation
- also, mark the stages in a more traditional way (F-D-X-M-W)
2010-01-31 18:25:27 -05:00
Korey Sewell
0e96798fe0
configs/inorder: add options for switch-on-miss to inorder cpu
2010-01-31 18:25:13 -05:00
Korey Sewell
7b3b362ba5
inorder: init internal debug cpu counters
...
- cpuEventNum
- resReqCount
2010-01-31 17:18:15 -05:00
Brad Beckmann
ab2f864af2
m5: Regression Tester Update
...
This patch includes the necessary regression updates to test the new ruby
configuration system. The patch includes support for multiple ruby protocols
and adds the ruby random tester. The patch removes atomic mode test for
ruby since ruby does not support atomic mode acceses. These tests can be
added back in when ruby supports atomic mode for real.
--HG--
rename : tests/quick/50.memtest/test.py => tests/quick/60.rubytest/test.py
2010-01-29 20:29:40 -08:00
Brad Beckmann
ceae8383ff
ruby: Replaced gems_common debug statements
...
Replaced Ruby debug statements with M5 statements.
2010-01-29 20:29:34 -08:00
Brad Beckmann
143d8ea698
ruby: removed last level cache support
...
Removed the last level cache support and MOESI_hammer's dependency on it.
Replaces the LLC support with the more generic MachineType count.
2010-01-29 20:29:34 -08:00
Brad Beckmann
90aab239a1
ruby: Added a Scons option to prevent HTML file creation
2010-01-29 20:29:33 -08:00
Brad Beckmann
1feae85017
ruby: Removed static members in RubyPort including hitcallback
...
Removed static members in RubyPort and removed the ruby request unique id.
2010-01-29 20:29:33 -08:00
Brad Beckmann
a579d3e43c
ruby: Removed the old config interface
...
Removed the old config interface from RubySystem and libruby.
2010-01-29 20:29:33 -08:00
Brad Beckmann
e4218dd08f
ruby: Re-enabled orion power models
...
Removed the dummy power function implementations so that Orion can implement
them correctly. Since Orion lacks modular design, this patch simply enables
scons to compile it. There are no python configuration changes in this patch.
2010-01-29 20:29:33 -08:00
Brad Beckmann
8dd45674ae
ruby: Converted Garnet to M5 configuration
2010-01-29 20:29:32 -08:00
Steve Reinhardt
b544462505
Garnet: reorganize directory tree.
...
Rename the ruby/network/garnet-foo directories to garnet/foo.
Move the common NetworkHeader.hh file from garnet-fixed-pipeline
up to the common garnet directory.
Fix up include paths.
--HG--
rename : src/mem/ruby/network/garnet-fixed-pipeline/NetworkHeader.hh => src/mem/ruby/network/garnet/NetworkHeader.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/CreditLink_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/CreditLink_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/GarnetNetwork_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/InputUnit_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/NetworkLink_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/OutVcState_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/OutVcState_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/OutputUnit_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/Router_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/Router_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/RoutingUnit_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/RoutingUnit_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/SConscript => src/mem/ruby/network/garnet/fixed-pipeline/SConscript
rename : src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/SWallocator_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/Switch_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/VCallocator_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/VCallocator_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/VirtualChannel_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/flitBuffer_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
rename : src/mem/ruby/network/garnet-fixed-pipeline/flit_d.cc => src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc
rename : src/mem/ruby/network/garnet-fixed-pipeline/flit_d.hh => src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/FlexibleConsumer.hh => src/mem/ruby/network/garnet/flexible-pipeline/FlexibleConsumer.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.cc => src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/GarnetNetwork.hh => src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/InVcState.cc => src/mem/ruby/network/garnet/flexible-pipeline/InVcState.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/InVcState.hh => src/mem/ruby/network/garnet/flexible-pipeline/InVcState.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/NetworkConfig.hh => src/mem/ruby/network/garnet/flexible-pipeline/NetworkConfig.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc => src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.hh => src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.cc => src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/NetworkLink.hh => src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.cc => src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/OutVcState.hh => src/mem/ruby/network/garnet/flexible-pipeline/OutVcState.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/Router.cc => src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/Router.hh => src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/SConscript => src/mem/ruby/network/garnet/flexible-pipeline/SConscript
rename : src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.cc => src/mem/ruby/network/garnet/flexible-pipeline/VCarbiter.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/VCarbiter.hh => src/mem/ruby/network/garnet/flexible-pipeline/VCarbiter.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/flit.cc => src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/flit.hh => src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.cc => src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
rename : src/mem/ruby/network/garnet-flexible-pipeline/flitBuffer.hh => src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
rename : src/mem/ruby/network/garnet-flexible-pipeline/netconfig.defaults => src/mem/ruby/network/garnet/flexible-pipeline/netconfig.defaults
2010-01-29 20:29:30 -08:00
Brad Beckmann
6c867f8263
ruby: Added a mesh topology
2010-01-29 20:29:27 -08:00
Brad Beckmann
faa76fc248
ruby: MESI_CMP_directory updated to the new config system
2010-01-29 20:29:27 -08:00
Brad Beckmann
3e286d825d
ruby: Sorted the file includes to maintain consistency
2010-01-29 20:29:26 -08:00
Brad Beckmann
5fb1f5c72b
ruby: Renamed the MESI directory sm file
...
Renamed the MESI directory file to be consistent with all other protocols.
--HG--
rename : src/mem/protocol/MESI_CMP_directory-mem.sm => src/mem/protocol/MESI_CMP_directory-dir.sm
2010-01-29 20:29:26 -08:00
Brad Beckmann
79f354466e
ruby: Removed the GPL header in MESI_CMP_directory-msg
...
I'm not sure how this got past our initial ruby code import, but this obviously
needed to be removed.
2010-01-29 20:29:26 -08:00
Brad Beckmann
31fcf09a68
ruby: MOESI_CMP_directory updated to the new config system
2010-01-29 20:29:26 -08:00
Brad Beckmann
1c4405ad5e
ruby: Added atomic support to MOESI_CMP_token
2010-01-29 20:29:25 -08:00
Brad Beckmann
042d5b87a4
ruby: fixed memory fetch bug for persistent requests
2010-01-29 20:29:25 -08:00
Brad Beckmann
d77a9df3c1
ruby: MOESI_CMP_token updates to use the new config system
2010-01-29 20:29:25 -08:00
Brad Beckmann
d42152742b
ruby: Allows boolean and string defaults for StateMachine parameters
2010-01-29 20:29:24 -08:00
Brad Beckmann
b3d195153e
ruby: MI_example updates to use the new config system
2010-01-29 20:29:24 -08:00
Brad Beckmann
134cc3d48d
ruby: convert to M5 MemorySize
...
Converted both ruby caches and directory memory to use the M5 MemorySize python
type.
2010-01-29 20:29:23 -08:00
Brad Beckmann
3a835c7cbb
ruby: Added Cache and MemCntrl profiler calls
2010-01-29 20:29:23 -08:00
Brad Beckmann
47502163b7
ruby: added data print to ruby request
2010-01-29 20:29:23 -08:00
Brad Beckmann
66279fac3f
ruby: Added atomic support to MOESI_hammer
2010-01-29 20:29:23 -08:00
Brad Beckmann
45230a4f6b
ruby: added the GEMS ruby tester
2010-01-29 20:29:23 -08:00
Brad Beckmann
4eb3bfc31b
ruby: fixed MOESI_hammer data writebacks to the directory
2010-01-29 20:29:22 -08:00
Brad Beckmann
f88faa6c11
ruby: cleaned up ruby profilers
...
Cleaned up the ruby profilers by moving the memory controller profiling code
out of the main profiler object and into a separate object similar to the
current CacheProfiler. Both the CacheProfiler and MemCntrlProfiler are
specific to a particular Ruby object, CacheMemory and MemoryControl
respectively. Therefore, these profilers should not be SimObjects and
created by the python configuration system, but instead private objects. This
simplifies the creation of these profilers.
2010-01-29 20:29:22 -08:00
Brad Beckmann
cfe41d0a1b
ruby: Removed RubySystem::getNumberOfSequencers
...
removed the static function RubySystem::getNumberOfSequencers and replaced
it with a python config variable
2010-01-29 20:29:21 -08:00
Brad Beckmann
1907e39fd2
ruby: added ruby stats print
...
Moved the previous rubymem stats print feature to ruby System so that ruby
stats are printed on simulation exit.
2010-01-29 20:29:21 -08:00
Brad Beckmann
020716cab3
ruby: fixed Set.cc bug to allow zero sized sets
...
This is necessary for example when no dma sequencers are necessary in the
simulated system.
2010-01-29 20:29:21 -08:00
Brad Beckmann
ce2d13195b
ruby: FS support using the new configuration system
2010-01-29 20:29:21 -08:00
Brad Beckmann
dc758641c9
ruby: reorganized ruby python configuration
...
Reorganized ruby python configuration so that protocol and ruby memory system
configuration code can be shared by multiple front-end configuration files
(i.e. memory tester, full system, and hopefully the regression tester). This
code works for memory tester, but have not tested fs mode.
2010-01-29 20:29:20 -08:00
Brad Beckmann
e735ca7c77
ruby: Removed out_link_vec from Consumer
...
Removed the out_line_vec data structure from the Consumer. I'm not sure
what this did before, but currently it has no usefulness.
2010-01-29 20:29:20 -08:00
Brad Beckmann
0f6535dba1
ruby: Convered ruby tracing support usage of sequencer
...
Modified ruby's tracing support to no longer rely on the RubySystem map
to convert a sequencer string name to a sequencer pointer. As a
temporary solution, the code uses the sim_object find function.
Eventually, we should develop a better fix.
2010-01-29 20:29:20 -08:00
Brad Beckmann
2c9ca672df
ruby: Memory Controller Profiler with new config system
...
This patch includes a rather substantial change to the memory controller
profiler in order to work with the new configuration system. Most
noteably, the mem_cntrl_profiler no longer uses a string map, but instead
a vector. Eventually this support should be removed from the main
profiler and go into a separate object. Each memory controller should have
a pointer to that new mem_cntrl profile object.
2010-01-29 20:29:20 -08:00
Brad Beckmann
2a0555470c
ruby: Converted MOESI_hammer dma cntrl to new config system
2010-01-29 20:29:19 -08:00
Brad Beckmann
3b290a35ac
ruby: Added the cache profiler to the new config system
2010-01-29 20:29:19 -08:00
Brad Beckmann
4e5f4b5074
ruby: Converted the sequencer deadlock event to m5 eventq
2010-01-29 20:29:19 -08:00
Brad Beckmann
e15abd17f9
ruby: Wrapped ruby events into m5 events
...
Wrapped ruby events using the m5 event object. Removed the prio_heap
from ruby's event queue and instead schedule ruby events on the m5 event
queue.
2010-01-29 20:29:19 -08:00
Brad Beckmann
63a60cc81e
ruby: Removed the tech_nm variable from RubySystem
2010-01-29 20:29:19 -08:00
Brad Beckmann
12daaed84a
ruby: Added clock to ruby system
...
As a first step to migrate ruby to the M5 eventqueue, added a clock
variable to the ruby system.
2010-01-29 20:29:19 -08:00
Brad Beckmann
ed81489954
ruby: Ruby changes required to use the python config system
...
This patch includes the necessary changes to connect ruby objects using
the python configuration system. Mainly it consists of removing
unnecessary ruby object pointers and connecting the necessary object
pointers using the generated param objects. This patch includes the
slicc changes necessary to connect generated ruby objects together using
the python configuraiton system.
2010-01-29 20:29:19 -08:00
Brad Beckmann
42bebab779
ruby: connects sm queues to the network
2010-01-29 20:29:18 -08:00
Steve Reinhardt
a8ea70dac6
ruby: Calculate system total memory capacity in Python
...
rather than in RubySystem object.
2010-01-29 20:29:18 -08:00
Steve Reinhardt
0b54f1db8e
ruby: Add support for generating topologies in Python.
2010-01-29 20:29:17 -08:00
Steve Reinhardt
184cf4db5b
scons: ignore blank lines in .slicc files
2010-01-29 20:29:17 -08:00
Steve Reinhardt
c6f1d959be
ruby: Make SLICC-generated objects SimObjects.
...
Also add SLICC support for state-machine parameter defaults
(passed through to Python as SimObject Param defaults).
2010-01-29 20:29:17 -08:00
Steve Reinhardt
98c94cfe3c
ruby: Convert most Ruby objects to M5 SimObjects.
...
The necessary companion conversion of Ruby objects generated by SLICC
are converted to M5 SimObjects in the following patch, so this patch
alone does not compile.
Conversion of Garnet network models is also handled in a separate
patch; that code is temporarily disabled from compiling to allow
testing of interim code.
2010-01-29 20:29:17 -08:00
Steve Reinhardt
b43994ba45
ruby: get rid of obsolete, unused CustomTopology class.
2010-01-29 20:29:14 -08:00
Brad Beckmann
7f03dce012
ruby: fix out_port declaration
2010-01-29 20:29:14 -08:00
Brad Beckmann
43e4f59e4f
ruby: Added message type check to OutPortDeclAST.py
...
Though OutPort's message type is not used to generate code, this fix checks
that the programmer's intent is correct. Eventually, we may want to
remove the message type from the OutPort declaration statement.
2010-01-29 20:29:13 -08:00
Nathan Binkert
5b90934dd2
build: need to include cstdio
2010-01-23 14:02:03 -08:00
Nathan Binkert
8a3fbbd8d9
compile: compile on 32 bit hardware
2009-11-05 17:21:26 -08:00
Nathan Binkert
52ccfde2cd
isa_parser: allow negative integer literals
2009-11-05 17:21:25 -08:00
Derek Hower
589218168c
Automated merge with ssh://hg@m5sim.org/m5
2010-01-22 17:23:21 -06:00
Lisa Hsu
d6da172517
util: do checkpoint aggregation more cleanly, fix last changeset.
...
1) Move alpha-specific code out of page_table.cc:serialize().
2) Begin serializing M5_pid and unserializing it, but adding an function to do optional paramIn so that old checkpoints don't need to be fixed up.
3) Fix up alpha startup code so that the unserialized M5_pid value is properly written to DTB_IPR_ASN.
4) Fix the memory unserialize that I forgot somehow in the last changeset.
5) Add in an agg_se.py to handle aggregated checkpoints. --bench foo-bar plus positional arguments foo bar are the only changes in usage from se.py.
Note this aggregation stuff has only been tested for Alpha and nothing else, though it should take a very minimal amount of work to get it to work with another ISA.
2010-01-19 22:03:44 -08:00
Derek Hower
07ea0891f1
ruby: new atomics implementation
...
This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order.
2010-01-19 17:11:36 -06:00
Derek Hower
279f179bab
merge
2010-01-19 15:48:12 -06:00
Lisa Hsu
4a40ac71f8
util: make a generic checkpoint aggregator that can aggregate different cpts into one multi-programmed cpt. Make minor changes to serialization/unserialization to get it to work properly. Note that checkpoints were made with a comment at the beginning with // - this must be changed to ## to work properly with the python config parser in the aggregator.
2010-01-18 14:30:31 -08:00
Lisa Hsu
8b4e8690b7
cache: make tags->insertBlock() and tags->accessBlock() context aware so that the cache can make context-specific decisions within their various tag policy implementations.
2010-01-12 10:53:02 -08:00
Lisa Hsu
9f63548478
since totalInstructions() is impl'ed by all the cpus, make it an abstract base class.
2010-01-12 10:22:46 -08:00
Lisa Hsu
daebe18e89
faults: i think these fault invocations should be panic and not fatal. it definitely made implementing a trace cpu easier this way.
2010-01-12 10:17:19 -08:00
Matt DeVuyst
18dc80e07b
MIPS: Beef up process initialization.
2009-12-31 15:30:51 -05:00
Gabe Black
ecaa7070e6
MIPS: Implement the SE mode version of rdhwr.
2009-12-31 15:30:51 -05:00
Gabe Black
c70f3c93af
MIPS: Fix decoding of the rdhwr instruction.
2009-12-31 15:30:51 -05:00
Gabe Black
134937b594
MIPS: Implement the set_thread_area system call.
2009-12-31 15:30:50 -05:00
Gabe Black
d3ed32b989
MIPS: Create an artificial control register to hold the thread pointer.
...
In Linux, the set_thread_area system call stores the address of the thread
local storage area into a field of the current thread_info structure. Later,
to access that value, the program uses the rdhwr instruction to read a
"hardware register" with index 29. The 64 bit MIPS manual, volume II, says
that index 29 is reserved for a future ABI extension and should cause a
"Reserved Instruction Exception". In Linux (and potentially other ISAs) that
exception is trapped and emulated to return the value stored by
set_thread_area as if that were actually stored by a physical register.
The tp_value address (as named in the Linux kernel) is ironically stored as a
control register so that it goes with a particular ThreadContext. Syscall
emulation will use that to emulate storing to the OS's thread info structure,
and rdhwr will emulate faulting and returning that value from software by
returning the value itself, as if it was in hardware. In other words, we fake
faking the register in SE mode. In an FS mode implementation it should
work as specified in the manual.
2009-12-31 15:30:50 -05:00
Gabe Black
cc07dcf026
MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg.
...
The MIPS ISA object expects to be constructed with a CPU pointer it uses to
look at other thread contexts and allow them to be manipulated with control
registers. Unfortunately, that differs from all the other ISA classes and
would complicate their implementation.
This change makes the event constructor use a CPU pointer pulled out of the
thread context passed to setMiscReg instead.
2009-12-31 15:30:50 -05:00
Gabe Black
1261f1d8db
MIPS: Add missing syscall slots.
...
These are all after the existing ones, suggesting they were added after the
original list was created.
2009-12-21 14:59:40 -08:00
Soumyaroop Roy
1bd0f772f1
Alpha: Implement MVI and remaining BWX instructions.
2009-12-20 15:03:23 -06:00
Gabe Black
3e1cda5080
X86: Add a latency that describes how long an interrupt takes to propagate through the IO APIC.
2009-12-19 01:50:06 -08:00
Gabe Black
c7ca1d3c8a
X86: Add a common named flag for signed media operations.
2009-12-19 01:48:31 -08:00
Gabe Black
2554511533
X86: Create a common flag with a name to indicate high multiplies.
2009-12-19 01:48:07 -08:00
Gabe Black
e474079ddc
X86: Create a common flag with a name to indicate scalar media instructions.
2009-12-19 01:47:30 -08:00
Derek Hower
5aa104e072
ruby: cleaned up ruby-lang configuration
2009-12-04 13:12:40 -06:00
Brad Beckmann
5d8a669539
Resurrection of the CMP token protocol to GEM5
2009-11-18 16:34:33 -08:00
Brad Beckmann
dcac2ec24c
ruby: removed the chip pointer from MessageBuffer
...
The Chip object no longer exists and thus is removed from the MessageBuffer
constructor.
2009-11-18 16:34:32 -08:00
Brad Beckmann
c9764b1ff1
ruby: added error message to isinstance check
...
Added error message when a symbol is not an instance of a particular expected
type.
2009-11-18 16:34:32 -08:00
Brad Beckmann
20f872ed2a
ruby: Added boolean to State Machine parameters
...
* * *
ruby: Removed primitive .hh includes
2009-11-18 16:34:32 -08:00
Brad Beckmann
8011e80725
ruby: The persistent table files from GEMS
...
These files are need by the MOESI_CMP_token protocol.
2009-11-18 16:34:32 -08:00
Brad Beckmann
cef3c56163
ruby: MOESI hammer support for DMA reads and writes
2009-11-18 16:34:32 -08:00
Brad Beckmann
dbb2c111cc
ruby: Added a memory controller feature to MOESI hammer
2009-11-18 16:34:32 -08:00
Brad Beckmann
bc12b8432d
ruby: Hammer ruby configuration support
2009-11-18 16:34:32 -08:00
Brad Beckmann
877be2009c
ruby: Changes necessary to get the hammer protocol to work in GEM5
2009-11-18 16:34:32 -08:00
Brad Beckmann
b0973035b4
ruby: added the original hammer protocols from old ruby
2009-11-18 16:34:31 -08:00
Brad Beckmann
2783a7b9ad
ruby: returns the number of LLC needed for broadcast
...
Added feature to CacheMemory to return the number of last level caches.
This count is need for broadcast protocols such as MOESI_hammer.
2009-11-18 16:34:31 -08:00
Brad Beckmann
7b8fcecf11
ruby: cache configuration fix to use bytes
...
Changed cache size to be in bytes instead of kb so that testers can use very
small caches and increase the chance of writeback races.
2009-11-18 16:34:31 -08:00
Brad Beckmann
99338a7460
ruby: fix CacheMemory destructor
2009-11-18 16:33:35 -08:00
Brad Beckmann
7ab484624f
ruby: split CacheMemory.hh into a .hh and a .cc
2009-11-18 16:33:35 -08:00
Brad Beckmann
8b0f970084
ruby: Added default names to message buffers
...
Added default names to message buffers created by the simple network.
2009-11-18 13:55:58 -08:00
Brad Beckmann
ed54ecf1c8
ruby: slicc method error fix
...
Added error message when a method call is not supported by an object.
2009-11-18 13:55:58 -08:00
Brad Beckmann
994169327a
ruby: slicc action error fix
...
Small fix to the State Machine error message when duplicate actions are defined.
2009-11-18 13:55:58 -08:00
Brad Beckmann
cc2db929cb
ruby: slicc state machine error fixes
...
Added error messages when:
- a state does not exist in a machine's list of known states.
- an event does not exist in a machine
- the actions of a certain machine have not been declared
2009-11-18 13:55:58 -08:00
Brad Beckmann
e84881b7a3
ruby: Removed unused action z_stall
2009-11-18 13:55:58 -08:00
Brad Beckmann
b5d2052fa0
m5: Fixed bug in atomic cpu destructor
2009-11-18 13:55:58 -08:00
Brad Beckmann
faf1d97f24
ruby: fixed dma mi example to work with multiple dma ports
2009-11-18 13:55:58 -08:00
Brad Beckmann
f54790977b
m5: removed master and slave deletions.
...
The unresolved destructor call caused a seg fault when called.
2009-11-18 13:55:58 -08:00
Brad Beckmann
4d731a522d
m5: fixed destructor to deschedule the tickEvent and event
2009-11-18 13:55:58 -08:00
Brad Beckmann
93f0069dd5
ruby: getPort function fix
...
Fixed RubyMemory::getPort function to not pass in a -1 for the idx parameter
2009-11-18 13:55:58 -08:00
Brad Beckmann
204d1776ca
ruby: Fixed Directory memory destructor
2009-11-18 13:55:58 -08:00
Brad Beckmann
6e1dc2546c
m5: Added isValidSrc and isValidDest calls to packet.hh
2009-11-18 13:55:58 -08:00
Brad Beckmann
90d6e2652f
ruby: included ruby config parameter ports per core
...
Slightly improved the major hack need to correctly assign the number of ports
per core. CPUs have two ports: icache + dcache. MemTester has one port.
2009-11-18 13:55:58 -08:00
Brad Beckmann
dce53610c3
ruby: Added error check for openning the ruby config file
2009-11-18 13:55:58 -08:00
Brad Beckmann
3cf24f9716
ruby: Support for merging ALPHA_FS and ruby
...
Connects M5 cpu and dma ports directly to ruby sequencers and dma
sequencers. Rubymem also includes a pio port so that pio requests
and be forwarded to a special pio bus connecting to device pio
ports.
2009-11-18 13:55:58 -08:00
Brad Beckmann
d7a4f665ed
ruby: Added more info to bridge error message
2009-11-18 13:55:57 -08:00
Brad Beckmann
17e14efa7e
ruby: Ruby 64-bit address output fixes.
2009-11-18 13:55:57 -08:00
Brad Beckmann
b7cc66af31
ruby: Ruby destruction fix.
2009-11-18 13:55:57 -08:00
Brad Beckmann
5492f71755
ruby: Ruby debug print fixes.
2009-11-18 13:55:57 -08:00
Derek Hower
9ef5e72917
ruby: added sequencer stats to track what requests are waiting on
2009-11-18 11:55:30 -06:00
Derek Hower
d11dd6ed2c
ruby: turned off randomization by default, turned on memory controller random arbitrate
2009-11-18 11:53:43 -06:00
Ali Saidi
422f0d9f10
ARM: Begin implementing CP15
2009-11-17 18:02:09 -06:00
Ali Saidi
0916c376a9
ARM: Differentiate between LDM exception return and LDM user regs.
2009-11-17 18:02:08 -06:00
Ali Saidi
1470dae8e9
ARM: Boilerplate full-system code.
...
--HG--
rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh
rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh
rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc
rename : src/arch/sparc/system.cc => src/arch/arm/system.cc
rename : src/arch/sparc/system.hh => src/arch/arm/system.hh
rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py
rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc
rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh
2009-11-17 18:02:08 -06:00
Ali Saidi
171e7f7b24
imported patch isa_fixes2.diff
2009-11-16 11:37:03 -06:00
Gabe Black
9127ee5ac8
ARM: Make the exception return form of ldm restore CPSR.
2009-11-15 00:23:14 -08:00
Gabe Black
903fb8c73d
ARM: Create a new type of load uop that restores spsr into cpsr.
2009-11-15 00:15:42 -08:00
Gabe Black
b41725f723
ARM: Check in the actual change from the last commit.
...
The last commit was somehow empty. This was what was supposed to go in it.
2009-11-14 21:03:10 -08:00
Gabe Black
c4042985d7
ARM: Fix up the implmentation of the msr instruction.
2009-11-14 19:22:30 -08:00
Gabe Black
e2ab64543b
ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.
2009-11-14 19:22:30 -08:00
Gabe Black
425ebf6bd7
ARM: Add a bitfield to indicate if an immediate should be used.
2009-11-14 19:22:30 -08:00
Gabe Black
e543f16247
ARM: Write some functions to write to the CPSR and SPSR for instructions.
2009-11-14 19:22:30 -08:00
Gabe Black
812e390693
ARM: Fix up the implmentation of the mrs instruction.
2009-11-14 19:22:29 -08:00
Gabe Black
1df0025e28
ARM: More accurately describe the effects of using the control operands.
2009-11-14 19:22:29 -08:00
Gabe Black
50b9149c75
ARM: Hook up the moded versions of the SPSR.
...
These registers can be accessed directly, or through MISCREG_SPSR which will
act as whichever SPSR is appropriate for the current mode.
2009-11-14 19:22:29 -08:00
Ali Saidi
4e9ce1805e
SE: Fix SE mode OS X compilation.
2009-11-14 11:49:01 -06:00
Ali Saidi
48bc573f5f
ARM: Move around decoder to properly decode CP15
2009-11-14 11:25:00 -06:00
Derek Hower
2f5839832e
ruby: added -A option to TwoLevel_SplitL1UnifiedL2 to set the L1 cache size
2009-11-13 09:45:23 -06:00
Derek Hower
f7f475a6f4
ruby: gave ALIASED_REQUEST priority over BUFFER_FULL in sequencer
2009-11-13 09:44:51 -06:00
Derek Hower
2ee04d6587
ruby: reduce the memory usage of ruby by making memory vector page based
2009-11-13 09:43:39 -06:00
Derek Hower
ceb8fde914
ruby: cache memory bugfix
2009-11-13 09:42:47 -06:00
Vince Weaver
8f6744c19c
X86: add ULL to 1's being shifted in 64-bit values
...
Some of the micro-ops weren't casting 1 to ULL before shifting,
which can cause problems. On the perl makerand input this
caused some values to be negative that shouldn't have been.
The casts are done as ULL(1) instead of 1ULL to match others
in the m5 code base.
2009-11-11 17:49:09 -05:00
Gabe Black
5524af83ef
ARM: Fix some bugs in the ISA desc and fill out some instructions.
2009-11-10 23:44:05 -08:00
Gabe Black
850eb54a7c
Merge with the head.
2009-11-10 21:12:53 -08:00
Gabe Black
b8120f6c38
Mem: Eliminate the NO_FAULT request flag.
2009-11-10 21:10:18 -08:00
Gabe Black
2e28da5583
ARM: Implement fault classes.
...
Implement some fault classes using the curriously recurring template pattern,
similar to SPARCs.
2009-11-10 20:34:38 -08:00
Gabe Black
4779020e13
ARM: Fix the integer register indexes.
...
The PC indexes in the various register sets was defined in the section for
unaliased registers which was throwing off the indexing. This moves those
where they belong. Also, to make detecting accesses to the PC easier and
because it's in the same place in all modes, the intRegForceUser function
now passes it through as index 15.
2009-11-10 20:19:55 -08:00
Vince Weaver
53e27c0277
X86: Fix bugs in movd implementation.
...
Unfortunately my implementation of the movd instruction had two bugs.
In one case, when moving a 32-bit value into an xmm register, the
lower half of the xmm register was not zero extended.
The other case is that xmm was used instead of xmmlm as the source
for a register move. My test case didn't notice this at first
as it moved xmm0 to eax, which both have the same register
number.
2009-11-10 11:29:30 -05:00
Vince Weaver
e81cc233a6
X86: Remove double-cast in Cvtf2i micro-op
...
This double cast led to rounding errors which caused
some benchmarks to get the wrong values, most notably lucas
which failed spectacularly due to CVTTSD2SI returning an
off-by-one value. equake was also broken.
2009-11-10 11:18:23 -05:00
Vince Weaver
7da221ca82
syscall: missing initializer in getcwd call
...
This one case was missed during the update to stack-based arguments.
Without this fix, m5 will crash during a gwtcwd call, at least
with X86.
2009-11-09 10:02:55 -05:00
Gabe Black
bbbfdee2ed
X86: Don't panic on faults on prefetches in SE mode.
2009-11-08 22:49:58 -08:00
Gabe Black
44e912c6bd
X86: Explain what really didn't work with unmapped addresses in SE mode.
2009-11-08 22:49:57 -08:00
Gabe Black
53086dfefe
X86: Make x86 use PREFETCH instead of PF_EXCLUSIVE.
2009-11-08 22:49:57 -08:00
Nathan Binkert
b1a1f9aec8
automerge
2009-11-08 20:15:54 -08:00
Steve Reinhardt
374d337693
scons: deal with generated .py files properly
2009-11-08 17:35:49 -08:00
Gabe Black
8a4af3668d
ARM: Support forcing load/store multiple to use user registers.
2009-11-08 15:49:03 -08:00
Gabe Black
bb903b6514
ARM: Simplify the load/store multiple generation code.
...
Specifically, get rid of the big switch statement so more cases can be
handled. Enumerating all the possible settings doesn't scale well. Also do
some minor style clean up.
2009-11-08 15:16:59 -08:00
Nathan Binkert
708faa7677
compile: wrap 64bit numbers with ULL() so 32bit compiles work
...
In the isa_parser, we need to check case statements.
2009-11-08 13:31:59 -08:00
Gabe Black
48525f581c
ARM: Split the condition codes out of the CPSR.
...
This allows those bits to be renamed while allowing the other fields to
control the behavior of the processor.
2009-11-08 02:08:40 -08:00
Gabe Black
d188821d37
ARM: Add in more bits for the mon mode.
2009-11-08 02:01:02 -08:00
Gabe Black
3a3e846151
ARM: Get rid of NumInternalProcRegs.
...
That constant is a carry over from Alpha and doesn't do anything in ARM.
2009-11-08 02:00:55 -08:00
Gabe Black
78bd8fe44f
ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR.
2009-11-08 01:59:20 -08:00
Gabe Black
f63c260d89
ARM: Get rid of the Raddr operand.
2009-11-08 01:57:34 -08:00
Gabe Black
43e9209c21
ARM: Initialize processes in user mode.
...
I accidentally left in a change to test using int registers in system mode.
This change reverts that.
2009-11-08 00:54:32 -08:00
Gabe Black
a2b76516c4
ARM: Implement the shadow registers using register flattening.
2009-11-08 00:07:49 -08:00
Gabe Black
4a454c4f47
ARM: Set up an intregs.hh for ARM.
...
Add constants for all the modes and registers, maps for aliasing, functions
that use the maps and range check, and use a named constant instead of a magic
number for the microcode register.
2009-11-08 00:07:35 -08:00
Gabe Black
18b21c1eca
ARM: Get rid of some unneeded register indexes.
2009-11-07 22:34:33 -08:00
Vince Weaver
5cf2e7ccf0
X86: Fix problem with movhps instruction
...
This problem is like the one fixed with movhpd a few weeks ago.
A +8 displacement is used to access memory when there should
be none.
This fix is needed for the perlbmk spec2k benchmark to run.
2009-11-04 13:22:15 -05:00
Steve Reinhardt
9098010e3f
slicc: tweak file enumeration for scons
...
Right now .cc and .hh files are handled separately, but then
they're just munged together at the end by scons, so it
doesn't buy us anything. Might as well munge from the start
since we'll eventually be adding generated Python files
to the list too.
2009-11-05 11:11:06 -08:00
Steve Reinhardt
058ccfc7fe
slicc: whack some of Nate's leftover debug code
2009-11-05 11:11:05 -08:00
Nathan Binkert
2c5fe6f95e
build: fix compile problems pointed out by gcc 4.4
2009-11-04 16:57:01 -08:00
Steve Reinhardt
fbfe92b5b8
o3: get rid of unused physmem pointer
2009-11-04 14:23:25 -08:00
Vince Weaver
a1042db290
X86: Enable x86_64 vsyscall support
...
64-bit vsyscall is different than 32-bit.
There are only two syscalls, time and gettimeofday.
On a real system, there is complicated code that implements these
without entering the kernel. That would be complicated to implement in m5.
Instead we just place code that calls the regular syscalls (this is how
tools such as valgrind handle this case).
This is needed for the perlbmk spec2k benchmark.
2009-11-04 00:47:12 -05:00
Vince Weaver
9b0a747dd4
X86: Hook up time syscall on X86
...
This has been tested and verified that it works.
2009-11-04 00:19:15 -05:00
Vince Weaver
a12557439b
X86: Add support for x86 psrldq and pslldq instructions
...
These are complicated instructions and the micro-code might be suboptimal.
This has been tested with some small sample programs (attached)
The psrldq instruction is needed by various spec2k programs.
2009-10-30 12:49:37 -04:00
Vince Weaver
5873ec2238
X86: Implement movd_Vo_Edp on X86
...
This patch implements the movd_Vo_Edp series of instructions.
It addresses various concerns by Gabe Black about which file the
instruction belonged in, as well as supporting REX prefixed
instructions properly.
This instruction is needed for some of the spec2k benchmarks, most
notably bzip2.
2009-10-30 15:52:33 -04:00
Vince Weaver
b2067840a6
X86: Implement the X86 sse2 haddpd instruction
...
This patch implements the haddpd instruction.
It fixes the problem in the previous version (pointed out by Gabe Black)
where an incorrect result would happen if you issue the instruction
with the same argument twice, i.e. "haddpd %xmm0,%xmm0"
This instruction is used by many spec2k benchmarks.
2009-10-30 14:19:06 -04:00
Vince Weaver
cf269025f9
X86: Hookup truncate/ftruncate syscalls on X86
...
This patch hooks up the truncate, ftruncate, truncate64 and ftruncate64
system calls on 32-bit and 64-bit X86.
These have been tested on both architectures.
ftruncate/ftruncate64 is needed for the f90 spec2k benchmarks.
2009-10-30 12:51:13 -04:00
Vince Weaver
9ad3acab5e
SysCalls: Implement truncate64 system call
...
This uses the new stack-based argument infrastructure.
Tested on x86 and x86_64.
2009-10-30 12:31:55 -04:00
Gabe Black
d6ff7929b3
Syscalls: Fix a warning turned error about an unused variable in m5.fast.
2009-10-31 13:20:22 -07:00
Gabe Black
3f722b991f
Syscalls: Make system calls access arguments like a stack, not an array.
...
When accessing arguments for a syscall, the position of an argument depends on
the policies of the ISA, how much space preceding arguments took up, and the
"alignment" of the index for this particular argument into the number of
possible storate locations. This change adjusts getSyscallArg to take its
index parameter by reference instead of value and to adjust it to point to the
possible location of the next argument on the stack, basically just after the
current one. This way, the rules for the new argument can be applied locally
without knowing about other arguments since those have already been taken into
account implicitly.
All system calls have also been changed to reflect the new interface. In a
number of cases this made the implementation clearer since it encourages
arguments to be collected in one place in order and then used as necessary
later, as opposed to scattering them throughout the function or using them in
place in long expressions. It also discourages using getSyscallArg over and
over to retrieve the same value when a temporary would do the job.
2009-10-30 00:44:55 -07:00
Nathan Binkert
25d9328689
license: Fix license on network model code
...
This mostly was a matter of changing the license owner to Princeton
which is as it should have been. The code was originally licensed
under the GPL but was relicensed as BSD by Li-Shiuan Peh on July 27,
2009. This relicensing was in an explicit e-mail to Nathan Binkert,
Brad Beckmann, Mark Hill, David Wood, and Steve Reinhardt.
2009-10-28 11:56:56 -07:00
Gabe Black
f9624e49f6
X86: Replace "DISPLACEMENT" with disp in movhpd.
2009-10-27 23:50:25 -07:00
Vince Weaver
87b97f28bd
Fix problem with the x86 sse movhpd instruction.
...
The movhpd instruction was writing to the wrong memory offset.
2009-10-27 14:11:06 -04:00
Vince Weaver
14691148cd
Implement X86 sse2 movdqu and movdqa instructions
...
The movdqa instruction should enforce 16-byte alignment.
This implementation does not do that.
These instructions are needed for most of x86_64 spec2k to run.
2009-10-21 13:40:43 -04:00
Vince Weaver
5b6f707a00
hook up stat syscall on 64-bit x86_SE
2009-10-20 16:48:00 -04:00
Derek Hower
22d9a53080
ruby: removed obsolete configuration files
2009-10-20 15:29:02 -05:00
Vince Weaver
2b473cb099
hook up stat64 syscall on 32-bit X86_SE
2009-10-20 14:44:51 -04:00
Vince Weaver
776f9405fa
Fix stat64 structure on 32-bit X86_SE
...
The st_size entry was in the wrong place
(see linux-2.6.29/arch/x86/include/asm/stat.h )
Also, the packed attribute is needed when compiling on a
64-bit machine, otherwise gcc adds extra padding that
break the layout of the structure.
2009-10-20 15:15:37 -04:00
Timothy M. Jones
835a55e7f3
POWER: Add support for the Power ISA
...
This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
2009-10-27 09:24:39 -07:00
Brad Beckmann
0fdfc82bde
fixed error message generation bug in SLICC ast files
2009-10-26 17:06:32 -07:00
Timothy M. Jones
1b2d75d6d2
syscall: Addition of an ioctl command code for Power.
2009-10-24 10:53:59 -07:00
Timothy M. Jones
03da1e53c2
syscall: Zero out memory that already exists during the brk system call.
...
Glibc often assumes that memory it receives from the kernel after a brk
system call will contain only zeros. This is important during a calloc,
because it won't clear the new memory itself. In the simulator, if the
new page exists, it will be cleared using this patch, to mimic the kernel's
functionality.
2009-10-24 10:53:58 -07:00
Timothy M. Jones
cc21f862e2
syscall: Fix conversion of the stat64 buffer during system calls.
2009-10-24 10:53:58 -07:00
Timothy M. Jones
c32d919bc0
syscall: Implementation of the ftruncate64 system call.
2009-10-24 10:53:58 -07:00
Timothy M. Jones
7cdd5316ab
syscall: Implementation of the time system call.
2009-10-24 10:53:57 -07:00
Timothy M. Jones
6c60db8ce9
syscall: Implementation of the times system call
2009-10-24 10:53:57 -07:00
Vince Weaver
56154cff5e
Enable getuid and getgid related syscalls on X86_SE
...
I've tested these on x86 and they work as expected.
In theory for 32-bit x86 we should have some sort of special
handling for the legacy 16-bit uid/gid syscalls, but in practice
modern toolchains don't use the 16-bit versions, and m5 sets the uid
and gid values to be less than 16-bits anyway.
This fix is needed for the perl spec2k benchmarks to run.
2009-10-19 17:29:34 -04:00
Derek Hower
909bac6840
ruby: add parameter to config to set # of l2 banks
2009-10-16 16:31:16 -05:00
Vince Weaver
22dc2b5595
Ignore rt_sigaction() syscalls on x86 and x86_64
...
This is currently how alpha handles this syscall.
This is needed for the gcc spec2k benchmarks to run.
2009-10-16 13:54:20 -04:00
Gabe Black
010b13c937
ISA: Fix compilation.
2009-10-17 01:13:41 -07:00
Brad Beckmann
28204b2a96
fixed MC146818 checkpointing bug and added isa serialization calls to simple_thread
2009-10-15 15:15:24 -07:00
Vince Weaver
30a185dcd0
Hook up the munmap() syscall for 32-bit x86.
...
This is straightforward, as munmapFunc() doesn't do anything.
I've tested it with code running munmap() just in case.
2009-10-10 22:31:56 -07:00
Derek Hower
4505216282
merge
2009-10-07 15:48:26 -05:00
Steve Reinhardt
8a761c44af
bus: add assertion to catch illegal retry
...
on mem-inhibited transaction.
2009-10-03 18:07:39 -07:00
Gabe Black
44ceb80c2d
X86: Make successive anonymous mmaps move down in 32 bit SE mode Linux.
2009-10-02 01:32:58 -07:00
Gabe Black
86f3bec76d
SE mode: Make the direction anonymous mmaps move through memory configurable.
2009-10-02 01:32:00 -07:00
Korey Sewell
f09f84da6e
inorder-debug: print out workload
2009-10-01 09:35:06 -04:00
Lisa Hsu
1290a5f340
commit Soumyaroop's bug catch about max_insts_all_threads
2009-09-29 18:03:10 -04:00
Nathan Binkert
160bcf4442
python: Fix m5.defines so grabbing flags works correctly
2009-09-26 12:51:37 -07:00
Steve Reinhardt
4bec4702e9
O3: Add flag to control whether faulting instructions are traced.
...
When enabled, faulting instructions appear in the trace twice
(once when they fault and again when they're re-executed).
This flag is set by the Exec compound flag for backwards compatibility.
2009-09-26 10:50:50 -07:00
Steve Reinhardt
f679630788
Minor cleanup: Use the blockAlign() method where it applies in the cache.
2009-09-26 10:50:50 -07:00
Steve Reinhardt
72cfed4164
Force prefetches to check cache and MSHRs immediately prior to issue.
...
This prevents redundant prefetches from being issued, solving the
occasional 'needsExclusive && !blk->isWritable()' assertion failure
in cache_impl.hh that several people have run into.
Eliminates "prefetch_cache_check_push" flag, neither setting of
which really solved the problem.
2009-09-26 10:50:50 -07:00
Steve Reinhardt
f28ea7a6c9
O3: Mark fetch stage as active if it faults.
...
Otherwise if the rest of the pipeline is idle then
fault will never propagate to commit to be handled,
causing CPU to deadlock.
2009-09-26 10:50:50 -07:00
Derek Hower
d9a2450054
protocol: cleaned up MESI...got rid of unneccessary virtual networks
2009-09-25 17:51:51 -05:00
Derek Hower
83a9dc2939
ruby: more helpful config error message
2009-09-25 17:51:12 -05:00
Derek Hower
26990dc492
slicc: removed unused atomics code from StateMachine
2009-09-25 17:47:38 -05:00
Korey Sewell
25d1f2728a
inorder-debug: fix cpu tick debug message
2009-09-25 11:18:55 -04:00
Nathan Binkert
baca1f0566
isa_parser: Turn the ISA Parser into a subclass of Grammar.
...
This is to prepare for future cleanup where we allow SCons to create a
separate grammar class for each ISA
2009-09-23 18:28:29 -07:00
Nathan Binkert
bae6a4a4d9
ply grammar: Fixup Tokenizer class so you can get lexer arguments
2009-09-23 18:28:29 -07:00
Nathan Binkert
be0d74d6f6
ruby: Disable all debug output by default
2009-09-23 18:17:11 -07:00
Nathan Binkert
d9f39c8ce7
arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
2009-09-23 08:34:21 -07:00
Nathan Binkert
2278363015
slicc: Pure python implementation of slicc.
...
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".
Slicc can easily be run manually by using util/slicc
2009-09-22 18:12:39 -07:00
Nathan Binkert
30d5d95b6a
params: small cleanup to param description internals
2009-09-22 15:24:16 -07:00
Nathan Binkert
e9288b2cd3
scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access
2009-09-22 15:24:16 -07:00
Nathan Binkert
9a8cb7db7e
python: Move more code into m5.util allow SCons to use that code.
...
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.
--HG--
rename : src/python/m5/convert.py => src/python/m5/util/convert.py
rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-09-22 15:24:16 -07:00
Nathan Binkert
0d58d32ad5
multiattrdict: make multilevel nesting work properly
2009-09-22 15:24:16 -07:00
Nathan Binkert
eec67312b5
attrdict: add pickle support to attrdict
2009-09-22 15:24:16 -07:00
Nathan Binkert
aa78db4ada
code_formatter: use __builtin__ which is correct, not __builtins__
2009-09-22 15:24:16 -07:00
Polina Dudnik
4f463b3a26
Atomics bug fix
2009-09-21 13:04:52 -05:00
Polina Dudnik
114d8724dd
Functionality migrated to sequencer.
2009-09-17 17:39:52 -05:00
Korey Sewell
b7094ec38b
mips: fix command line arguments
...
arguments were not being saved correctly into M5 memory
2009-09-17 15:59:43 -04:00
Korey Sewell
6f7e196113
inorder-mdu: multiplier latency fix
...
mdu was workign incorrectly for 4+ latency due to incorrectly assuming
multiply was finished the next stage
2009-09-17 15:45:27 -04:00
Gabe Black
931405da2f
X86: Fix the expected size of the immediate offset in MOV_MI.
2009-09-17 02:56:06 -07:00
Gabe Black
c876a781a5
X86: Sign extend the immediate of wripi like the register version.
2009-09-16 19:29:51 -07:00
Gabe Black
7a0ef6c36f
X86: Make the imm8 member of immediate microops really 8 bits consistently.
2009-09-16 19:28:57 -07:00
Gabe Black
239f1dea31
X86: Fix checking the NT bit during an IRET.
2009-09-16 19:28:30 -07:00
Gabe Black
eec6bfaa9d
X86: Fix setting the busy bit in the task descriptor in LTR.
2009-09-16 19:28:01 -07:00
Soumyaroop Roy
83eebe0464
inorder-smt: remove hardcoded values
...
allows for the 2T hello world example to work in inorder model
2009-09-16 09:47:38 -04:00
Vince Weaver
9b8e61beb3
Syscalls: Implement sysinfo() syscall.
2009-09-15 22:36:47 -07:00
Derek Hower
31a3ef03cb
ruby: improve libruby_issue_request feedback
2009-09-15 21:37:40 -05:00
Derek Hower
144459032a
removed isReady from the library interface
2009-09-15 20:49:54 -05:00
Derek Hower
20da0f788c
ruby: added broadcast mechanism
2009-09-15 20:39:00 -05:00
Derek Hower
a06cfa199f
ruby: added unified assert script
2009-09-15 11:32:11 -05:00
Derek Hower
803cf3b434
ruby: made configuration parameters uniform
2009-09-15 09:47:11 -05:00
Vince Weaver
0f569b4d9d
SPARC: Make resTemp in udivcc wide enough to hold all the bits we need.
2009-09-15 05:48:20 -07:00
Vince Weaver
9900ac95b5
[mq]: x86syscalls.patch
2009-09-15 05:30:08 -07:00
Korey Sewell
badb2382a8
inorder-alpha-fs: edit inorder model to compile FS mode
2009-09-15 01:44:48 -04:00
Derek Hower
11f3f83068
ruby:removed unused code from CacheMemory
2009-09-14 17:52:46 -05:00
Derek Hower
18e328cb63
ruby: configuration updates
2009-09-14 17:11:02 -05:00
Derek Hower
62b06f4a70
ruby: removed stray printf
2009-09-14 17:09:26 -05:00
Derek Hower
75c2baa81c
merge
2009-09-11 16:23:17 -05:00
Derek Hower
6fc2a4cadc
ruby: cleaned up unified MESI/MOESI configuration
2009-09-11 16:22:59 -05:00
Polina Dudnik
c7f0cf9803
Added new MESI files
2009-09-11 16:19:31 -05:00
Derek Hower
bd770274b0
merge
2009-09-11 14:17:21 -05:00
Polina Dudnik
8cdd7265ce
Config adjustments for MESI
2009-09-11 11:07:22 -05:00
Polina Dudnik
fc9ebc60db
Somayeh's MESI protocol with Polina's bug fixes
2009-09-11 11:04:55 -05:00
Polina Dudnik
7ef3e3b2c2
MI data corruption bug fix
2009-09-11 10:59:35 -05:00
Polina Dudnik
353a69eae7
Object print bug fix
2009-09-11 10:59:08 -05:00
Polina Dudnik
2af2e590e1
MOESI data corruption bug fix
2009-09-11 10:58:37 -05:00
Derek Hower
1e40ee4ea0
Automated merge with ssh://hg@m5sim.org/m5
2009-09-10 22:02:13 -05:00
Derek Hower
0637fe0bfd
ruby: removed SMT-related Sequencer assert
2009-09-10 21:19:54 -05:00
Derek Hower
ef87b6dc82
ruby: made randomization true by default
2009-09-10 21:19:34 -05:00
Derek Hower
26acdd4f34
protocol: made MI_example work with unordered networks
2009-09-10 21:18:09 -05:00
Derek Hower
e6e3ccf5c0
ruby: made L2 request/response latency based on cache latency by default
2009-09-10 13:32:16 -05:00
Derek Hower
3bb2fcfc84
ruby: made Locked read/write atomic requests within ruby
2009-09-09 12:39:10 -05:00
Polina Dudnik
ca0e0c3683
SCons fix to always make MemTest object
2009-09-01 10:38:25 -05:00
Derek Hower
edd522b30a
Automated merge with ssh://hg@m5sim.org/m5
2009-09-01 09:36:53 -05:00
Derek Hower
849bad7ad7
ruby: fixed config assertion failure
2009-09-01 09:35:48 -05:00
Polina Dudnik
041a8cefc7
[mq]: MOESI_patch
2009-08-31 16:38:22 -05:00
Polina Dudnik
a02dbd61f9
Reset the atomics flags if RMW_Read is not followed by a RMW_Read or RMW_Write
2009-08-28 15:09:41 -05:00
Polina Dudnik
95da6dc84c
imported patch mi_patch
2009-08-28 15:04:55 -05:00
Derek Hower
15aa180570
merge
2009-08-25 10:37:21 -05:00
Derek Hower
6cd552483b
Automated merge with ssh://hg@m5sim.org/m5
2009-08-25 10:10:23 -05:00
Derek Hower
03bf748ac7
ruby: CacheMemory tag lookup uses a hash instead of a loop
2009-08-25 10:09:47 -05:00
Gabe Black
e251b42c59
Merge with head.
2009-08-23 14:19:14 -07:00
Gabe Black
d0d597004f
X86: Preserve the NO_ACCESS flag when giving CDA a specialized interface.
2009-08-23 14:16:58 -07:00
Gabe Black
ce63e50364
Atomic CPU: Respect the NO_ACCESS request flag.
2009-08-23 14:15:15 -07:00
Polina Dudnik
a4fc1bad94
[mq]: first_patch
2009-08-21 15:52:46 -05:00
Nathan Binkert
890be77362
X86: fix some simple compile issues
...
static should not be used for constants that are not inside a class definition.
2009-08-21 09:10:25 -07:00
Gabe Black
f6bb7ec4eb
RTC: Make calls to writeData update the RTCs internal representation of time.
2009-08-20 23:09:03 -07:00
Gabe Black
da3c3bfa98
X86: Make the real time clock actually keep track of time.
2009-08-20 00:42:43 -07:00
Gabe Black
e8c0ca5cd1
X86: Fix the decoding for and fill out FST and FSTP.
2009-08-20 00:42:14 -07:00
Gabe Black
843d064668
X86: Add microassembler symbols for floating point stack register operands.
2009-08-20 00:41:27 -07:00
Gabe Black
bc67396ada
X86: Don't insist on binary encoding for the RTC since we implement BCD.
2009-08-20 00:40:14 -07:00
Derek Hower
efc1dddbd8
ruby: added random seed option to config scripts
2009-08-18 16:24:09 -05:00
Gabe Black
ed088ed15e
X86: Decode the immediate byte opcode extension for 3dNow! instructions.
2009-08-18 00:52:47 -07:00
Gabe Black
fd45c04cad
X86: Decode three byte opcodes.
2009-08-18 00:52:45 -07:00
Gabe Black
a1ea10d7ba
Merge with head.
2009-08-17 22:39:10 -07:00
Gabe Black
8f49cd1123
X86: Move the simulated date in X86_FS forward to 2012.
2009-08-17 20:25:15 -07:00
Gabe Black
9df74ab401
X86: Double check the two byte portion of the decoder and fix bugs/clean up.
2009-08-17 20:25:15 -07:00
Gabe Black
92867cac95
X86: Implement MOVNTI.
2009-08-17 20:25:15 -07:00
Gabe Black
6415252a0f
X86: Initialize the MXCSR in SE mode.
2009-08-17 20:25:14 -07:00
Gabe Black
56d87cdc08
X86: Implement MOVQ2DQ.
2009-08-17 20:25:14 -07:00
Gabe Black
317a9ac6d1
X86: Implement MOVDQ2Q.
2009-08-17 20:25:14 -07:00
Gabe Black
1606663aa9
X86: Implement the media instructions that convert fp values to ints.
2009-08-17 20:25:14 -07:00
Gabe Black
e3ef432a55
X86: Implement a microop for converting fp values to ints.
2009-08-17 20:25:14 -07:00
Gabe Black
123ea3b229
X86: Implement the instructions that compare fp values and write a mask as a result.
2009-08-17 20:25:14 -07:00
Gabe Black
288f428632
X86: Implement a microop that compares fp values and writes a mask as a result.
2009-08-17 20:25:14 -07:00
Gabe Black
87ad677209
X86: Implement the instructions that compare fp values and write to rflags.
2009-08-17 20:25:14 -07:00
Gabe Black
2c9ee52c37
X86: Implement a microop that compares fp values and writes to rflags.
2009-08-17 20:25:14 -07:00
Gabe Black
7d4db7266e
X86: Implement MOVSS.
2009-08-17 20:25:14 -07:00
Gabe Black
179fd4e536
X86: Implement LDMXCSR.
2009-08-17 20:25:14 -07:00
Gabe Black
b315c3effc
X86: Implement STMXCSR.
2009-08-17 20:25:13 -07:00
Gabe Black
7fbd9e1296
X86: Implement the shuffle media instructions.
2009-08-17 20:25:13 -07:00
Gabe Black
1fed0161d9
X86: Implement a shuffle media microop.
2009-08-17 20:25:13 -07:00
Gabe Black
d9970f139a
X86: Implement the mask move instructions.
2009-08-17 20:22:56 -07:00
Gabe Black
75528a497c
X86: Implement a mask move microop.
2009-08-17 20:22:56 -07:00
Gabe Black
90dc1abd0b
X86: Implement the instructions that move sign bits.
2009-08-17 20:22:56 -07:00
Gabe Black
90786e43fc
X86: Implement a microop that moves sign bits.
2009-08-17 20:22:56 -07:00
Gabe Black
4c23e631f2
X86: Implement the insert/extract instructions.
2009-08-17 20:22:56 -07:00
Gabe Black
c0e850c77a
X86: Fix a bug in the decoder where the insert/extract instructions go.
2009-08-17 20:22:56 -07:00
Gabe Black
965e546df3
X86: Extend mov2int and mov2fp so they can support insert and extract instructions.
2009-08-17 20:22:56 -07:00
Gabe Black
2beab367d7
X86: Implement the media average instructions.
2009-08-17 20:15:16 -07:00
Gabe Black
f6b12bfa8d
X86: Implement a media average microop.
2009-08-17 20:15:16 -07:00
Gabe Black
45bae0c70f
X86: Implement the multiply and add instructions.
2009-08-17 20:15:16 -07:00
Gabe Black
200fed31de
X86: Let the integer multiply microop use every other possible source value.
2009-08-17 20:15:16 -07:00
Gabe Black
cf2fc2613d
X86: Implement the media shifts that operate on 64 bits or less at a time.
2009-08-17 20:15:16 -07:00
Gabe Black
c8a0cf5df7
X86: Implement the media shift microops. These don't handle full 128 bit wide shifts.
2009-08-17 20:15:16 -07:00
Gabe Black
dabbc7d9d3
X86: Implement the sum of absolute differences instructions.
2009-08-17 20:15:16 -07:00
Gabe Black
470dcef229
X86: Implement a "sum of absolute differences" microop.
2009-08-17 20:15:16 -07:00
Gabe Black
31d29ee3f8
X86: Implement the media integer subtract instructions.
2009-08-17 20:15:15 -07:00
Gabe Black
a4437f8f14
X86: Implement an integer media subtract microop.
2009-08-17 20:15:15 -07:00
Gabe Black
c40698e315
X86: Implement the integer media multiply instructions.
2009-08-17 20:15:15 -07:00
Gabe Black
3424de2861
X86: Implement a media integer multiply microop.
2009-08-17 20:15:15 -07:00
Gabe Black
c76459e5a7
X86: Make larger blocks of instructions use the Inst format by default.
2009-08-17 20:04:03 -07:00
Gabe Black
5d834c28eb
X86: Implement the integer media max instructions.
2009-08-17 20:04:03 -07:00
Gabe Black
c9a954c77a
X86: Implement an integer media max microop.
2009-08-17 20:04:03 -07:00
Gabe Black
be6267e895
X86: Implement the integer media min instructions.
2009-08-17 20:04:03 -07:00
Gabe Black
e2759fe69c
X86: Add a media integer min microop.
2009-08-17 20:04:02 -07:00
Gabe Black
e678df6263
X86: Implement the media integer addition instructions.
2009-08-17 20:04:02 -07:00
Gabe Black
c278760da0
X86: Implement an integer media addition microop with optional saturation.
2009-08-17 20:04:02 -07:00
Gabe Black
f5ac4f51d9
X86: Implement the instructions that convert between forms of floating point.
2009-08-17 20:04:02 -07:00
Gabe Black
83df309a7e
X86: Implement a media microop that converts between floating point data types.
2009-08-17 20:04:02 -07:00
Gabe Black
35b0983ca9
X86: Implement the instructions that compare fp values and write masks as the result.
2009-08-17 20:04:02 -07:00
Gabe Black
f122c93faa
X86: Implement a microop that compares fp values and writes a mask as its result.
2009-08-17 20:04:02 -07:00
Gabe Black
df1b3fdcfb
X86: Implement the MOVDDUP instruction.
2009-08-17 18:50:29 -07:00
Gabe Black
cf9634a43f
X86: Implement many of the media mov instructions.
2009-08-17 18:44:44 -07:00
Gabe Black
ae64377afe
X86: Implement the media instructions that convert integer values to floating point.
2009-08-17 18:41:27 -07:00
Gabe Black
8e97cd9c8f
X86: Implement a media microop for converting integer values to floating point.
2009-08-17 18:41:25 -07:00
Gabe Black
b34b507fd8
X86: Implement the floating point media instructions.
2009-08-17 18:40:40 -07:00
Gabe Black
af3a53726b
X86: Implement a floating point media divide microop.
2009-08-17 18:40:38 -07:00
Gabe Black
fcb5b2226c
X86: Implement the floating point media multiply instructions.
2009-08-17 18:38:53 -07:00
Gabe Black
94e771e283
X86: Implement a floating point media multiply microop.
2009-08-17 18:38:51 -07:00
Gabe Black
dd81a34829
X86: Implement the floating point media subtract instructions.
2009-08-17 18:36:20 -07:00
Gabe Black
9fee8b75aa
X86: Implement a media floating point subtract microop.
2009-08-17 18:36:18 -07:00
Gabe Black
49c2610c04
X86: Implement the floating point media add instructions.
2009-08-17 18:35:06 -07:00
Gabe Black
df163284fc
X86: Implement a floating point media add microop.
2009-08-17 18:35:04 -07:00
Gabe Black
449db8a370
X86: Implement the media sqrt instructions.
2009-08-17 18:34:19 -07:00
Gabe Black
6a923c1c79
X86: Implement a media square root microop.
2009-08-17 18:34:16 -07:00
Gabe Black
09eed9ff62
X86: Implement the media floating point max instructions.
2009-08-17 18:33:28 -07:00
Gabe Black
8d37ce8652
X86: Implement the floating point media max microop.
2009-08-17 18:33:25 -07:00
Gabe Black
34f528bd95
X86: Implement the media floating point min instructions.
2009-08-17 18:32:12 -07:00
Gabe Black
1d706c0434
X86: Implement a floating point media min microop.
2009-08-17 18:32:09 -07:00
Gabe Black
e20c8a4b05
X86: Implement the pack instructions.
2009-08-17 18:32:08 -07:00
Gabe Black
1273277d3b
X86: Create a pack media microop.
2009-08-17 18:27:54 -07:00
Gabe Black
e6b5192c26
X86: Rename sel to ext for media microops.
2009-08-17 18:27:44 -07:00
Gabe Black
80b4456fec
X86: Move the MMX version of MOVD into the simd64 directory.
2009-08-17 18:27:30 -07:00
Gabe Black
63403bd562
X86: Implement the remaining unpack instructions.
2009-08-17 18:27:19 -07:00
Gabe Black
7b18f8a062
X86: Implement PANDN, ANDNPS, and ANDNPD.
2009-08-17 18:25:00 -07:00
Gabe Black
458521f055
X86: Implement a multimedia andn microop.
2009-08-17 18:24:58 -07:00
Gabe Black
3633392ec4
X86: Implement PAND, ANDPS, and ANDPD.
2009-08-17 18:24:18 -07:00
Gabe Black
ab49a34a4e
X86: Implement a multimedia and microop.
2009-08-17 18:24:16 -07:00
Gabe Black
83a78072df
X86: Implement POR, ORPD and ORPS.
2009-08-17 18:23:33 -07:00
Gabe Black
25c6b016a6
X86: Implement a media or microop.
2009-08-17 18:23:30 -07:00
Gabe Black
f9346d25c8
X86: Implement PXOR.
2009-08-17 18:23:04 -07:00
Gabe Black
69f0bf743c
X86: (Re)implement XORPS and XORPD.
2009-08-17 18:22:37 -07:00
Gabe Black
982b3ad1f0
X86: Implement a media xor microop.
2009-08-17 18:22:33 -07:00
Gabe Black
f3fb444af4
X86: Implement PUNPCKLQDQ.
2009-08-17 18:21:46 -07:00
Gabe Black
cfaeb5eaf7
X86: Implement PUNPCKHQDQ.
2009-08-17 18:21:09 -07:00
Gabe Black
aabbb22cca
X86: Implement PUNPCKHDQ.
2009-08-17 18:20:50 -07:00
Gabe Black
535ba241f8
X86: Implement PUNPCKHWD.
2009-08-17 18:19:43 -07:00
Gabe Black
093b5b3274
X86: Implement PUNPCKHBW.
2009-08-17 18:19:19 -07:00
Gabe Black
3ae2f03927
X86: Implement PUNPCKLDQ.
2009-08-17 18:19:01 -07:00
Gabe Black
673b19f5d4
X86: Implement PUNPCKLWD.
2009-08-17 18:18:40 -07:00
Gabe Black
ae4ee21ecd
X86: Implement the versions of PUNPCKLBW that use XMM registers.
2009-08-17 18:18:19 -07:00
Gabe Black
24496060e5
X86: Implement the MOVQ instruction.
2009-08-17 18:17:29 -07:00
Gabe Black
f1bfa9d6e4
X86: Implement the lfpimm microop.
2009-08-17 18:17:26 -07:00
Gabe Black
fca7cb83f0
X86: Implement the versions of MOVD that have an MMX source.
2009-08-17 18:16:07 -07:00
Gabe Black
247ed2379d
X86: Implement the versions of PUNPCKLBW that use MMX registers.
2009-08-17 18:15:42 -07:00
Gabe Black
ecc62e750e
X86: Implement an unpack microop.
2009-08-17 18:15:39 -07:00
Gabe Black
6457fb7003
X86: Implement the versions of MOVD that have an MMX destination.
2009-08-17 18:15:24 -07:00
Gabe Black
191590bcc4
X86: Ignore the size part of XMM/MMX operands. The instructions know what they want.
2009-08-17 18:15:23 -07:00
Gabe Black
33cb4c2f09
X86: Use suffixes to differentiate XMM/MMX/GPR operands.
2009-08-17 18:15:21 -07:00
Gabe Black
3a4438a868
X86: Add microcode assembler symbols for mmx registers.
2009-08-17 18:15:19 -07:00
Gabe Black
2f1001e95c
X86: Set up a media microop framework and create mov2int and mov2fp microops.
2009-08-17 18:15:18 -07:00
Gabe Black
cec4e3b39e
X86: Create base classes for use with media/SIMD microops.
2009-08-17 18:15:16 -07:00
Gabe Black
0b68fbdbe1
X86: Turn the DIV and IDIV microcode into templates and generate all the variants.
2009-08-17 18:15:14 -07:00
Gabe Black
a9b2bf5119
X86: Remove some FIXMEs from IDIV that have been fixed.
2009-08-17 18:15:13 -07:00
Gabe Black
3f2f3bede8
X86: Turn the CMPXCHG8B microcode into a template and generate each variant.
2009-08-17 18:15:00 -07:00
Polina Dudnik
c438b2e431
Branch Merge
2009-08-17 11:33:32 -05:00
Gabe Black
a43ae579dd
Merge with head.
2009-08-17 00:21:57 -07:00
Gabe Black
32c8514b45
X86: Fix a bug introduced to IDIV in a recent attempt to fix another bug.
2009-08-17 00:20:03 -07:00
Nathan Binkert
a6b39c07d9
code_formatter: Add a python class for writing code generator templates
2009-08-16 13:40:03 -07:00
Nathan Binkert
2ecaa99025
ply: add a base class called Grammar that encapsulates a ply grammar
2009-08-16 13:40:01 -07:00
Nathan Binkert
2334e6fdd5
orderdict: Use DictMixin and add orderdict to m5.util
2009-08-16 13:40:00 -07:00
Nathan Binkert
06c7ecb207
python: Make it possible to import the parts of m5 that are pure python
2009-08-16 13:39:59 -07:00
Polina Dudnik
6654fe02da
Made servicing_atomic a counter and added started writes:
...
a function for setting the flag to indicate that
the rmw_writes started issuing
2009-08-15 12:45:11 -05:00
Polina Dudnik
a8e11cf3bb
Bug fix: indicate when writes started coming in
2009-08-14 17:57:54 -05:00
Polina Dudnik
ee3226d973
Merge with current branch
2009-08-14 15:30:25 -05:00
Polina Dudnik
0b0f47ec16
Added proc_id to CacheMsg for SMT.
...
Not yet necessary, but in case each of the threads
is allowed to initiate an atomic, will come in handy
2009-08-14 15:30:07 -05:00
Polina Dudnik
de25decf37
Multi-line RMW handling
2009-08-14 14:24:15 -05:00
Polina Dudnik
4b924fd16c
SMT atomics modifications:
...
don't allow enquing from other threads if servicing and atomic for a thread
2009-08-14 14:06:14 -05:00
Derek Hower
bcaf93d182
Automated merge with ssh://hg@m5sim.org/m5
2009-08-13 10:37:37 -05:00
Derek Hower
db40cb8f51
ruby: config bugfix
2009-08-13 10:37:09 -05:00
Tushar Krishna
35082a67b6
ruby/network data_msg_size bug fix with updated stats
2009-08-11 15:19:04 -07:00
Brad Beckmann
b89add1e3f
merged Tushar's bug fix with public repository changes
2009-08-11 12:22:41 -07:00
Derek Hower
1c3efb48ad
Automated merge with ssh://hg@m5sim.org/m5
2009-08-09 13:59:14 -05:00
Derek Hower
1a452d228b
protocol: added recycle actions to MOESI DMA events
2009-08-09 13:58:40 -05:00
Gabe Black
c5fae51774
X86: Implement the CMPXCHG8B/CMPXCHG16B instruction.
2009-08-09 01:01:41 -07:00
Gabe Black
bbf117b20e
X86: Don't clobber the original dividend when doing signed divide.
2009-08-09 01:01:18 -07:00
Gabe Black
3b07a5829d
X86: Decode byte sized singed divide as byte sized.
2009-08-09 01:00:47 -07:00
Gabe Black
6e97feb8a5
X86: Make not taken conditional moves leave the destination alone. Adjust CMOVcc.
...
The manuals from both AMD and Intel say that when writing to a 32 bit
destination in 64 bit mode, the upper 32 bits of the register are filled with
zeros. They also both say that the CMOV instructions leave their destination
alone when their condition fails. Unfortunately, it seems that CMOV will zero
extend its destination register whether or not it was supposed to actually do
a move on both platforms. This seems to be the only case where this happens,
but it would be hard to say for sure.
2009-08-08 17:23:19 -07:00
Tushar Krishna
b952eb19c1
bug fix for data_msg_size in network/Network.cc
2009-08-07 13:59:40 -07:00
Gabe Black
7c606e3835
X86: (Re)Implemented SHRD.
2009-08-07 10:13:33 -07:00
Gabe Black
4f5270f946
X86: Implement SHLD.
2009-08-07 10:13:24 -07:00
Gabe Black
3a55fc5cac
X86: Implement shift right/left double microops.
...
This is my best guess as far as what these should do. Other existing microops
use implicit registers, mul1s and mul1u for instance, so this should be ok.
The microop that loads the implicit DoubleBits register would fall into one
of the microop slots for moving to/from special registers.
2009-08-07 10:13:20 -07:00
Gabe Black
62a2e85c9a
X86: Make the qaud width bswap instruction handle the fact that 32 bit operations zero extend.
2009-08-07 10:12:58 -07:00
Gabe Black
0526f453aa
X86: Use the right field when using legacy prefixes to distinguish instructions.
2009-08-07 10:12:52 -07:00
Gabe Black
2daba26359
X86: Don't truncate the immediate parameter for the ENTER instruction.
2009-08-07 10:12:29 -07:00
Gabe Black
2e3446a410
X86: Adjust the various sizes used for the enter and leave instructions.
2009-08-06 21:44:42 -07:00
Gabe Black
c7b894a06f
X86: Make scas compare its operands in the right order.
2009-08-06 21:44:41 -07:00
Gabe Black
011c1865ad
X86: Fix a copy/paste error for cmovnp.
2009-08-06 21:44:40 -07:00
Derek Hower
cbc52ef6c5
fixed MOESI_CMP_directory bug
2009-08-06 03:41:28 -05:00
Derek Hower
f5e0c56da2
protocol: fixed MOESI_CMP_directory bug
2009-08-06 01:15:55 -05:00
Derek Hower
a1b5a6320f
ruby: better configuration assert message
2009-08-06 01:15:23 -05:00
Derek Hower
dff7c9eaa0
merge
2009-08-05 14:23:32 -05:00
Derek Hower
fbf7391bb0
ruby: configuration supports multiple runs in same session
...
These changes allow to run Ruby-gems multiple times from the same
ruby-lang script with different configurations
2009-08-05 14:20:32 -05:00
Derek Hower
1276df51e2
protocol: made MI_example dma mapping generic
2009-08-05 14:17:23 -05:00
Gabe Black
60d4a0f6d7
Merge with head.
2009-08-05 03:12:39 -07:00
Gabe Black
da2df2fc25
X86: Make conditional moves zero extend their 32 bit destinations always.
2009-08-05 03:07:55 -07:00
Gabe Black
b64d0bdeda
X86: Fix condition code setting for signed multiplies with negative results.
2009-08-05 03:07:01 -07:00
Gabe Black
2914a8eb16
X86: Make the check for negative operands for sign multiply more direct.
2009-08-05 03:06:37 -07:00
Gabe Black
e2e0ae576a
X86: Make sure immediate values are truncated properly.
...
Register values will be "picked" which will assure they don't have junk beyond
the part we're using. Immediate values don't go through a similar process, so
we should truncate them explicitly.
2009-08-05 03:06:01 -07:00
Gabe Black
ef3896d851
X86: Use the new forced folding mechanism for the SAHF and LAHF instructions.
2009-08-05 03:04:17 -07:00
Gabe Black
664d50b439
X86: Fix the indexing for ah in byte division instructions.
2009-08-05 03:03:41 -07:00
Gabe Black
abe8fb3844
X86: Fix the indexing for ah in byte multiply instructions.
2009-08-05 03:03:28 -07:00
Gabe Black
df1abc4412
X86: Let microops force folding an index into the high byte of a register.
2009-08-05 03:03:07 -07:00
Gabe Black
c4140d7d60
X86: Handle rotate left with carry instructions that go all the way around or more.
2009-08-05 03:02:28 -07:00
Gabe Black
3990445354
X86: Set the flags on rotate left with carry instructions.
2009-08-05 03:02:05 -07:00
Gabe Black
d265f7683e
X86: Handle rotate right with carry instructions that go all the way around or more.
2009-08-05 03:01:49 -07:00
Gabe Black
77dc6b33ee
X86: Fix the overflow bit for rotate right with carry.
2009-08-05 03:01:23 -07:00
Gabe Black
c8b1a4583e
X86: Fix the computation of the bottom part of rotate right with carry.
2009-08-05 03:01:07 -07:00
Gabe Black
bab4597fc5
X86: Fix the computation of the upper part of rotate right with carry.
2009-08-05 03:00:43 -07:00
Gabe Black
4e4adcaaa8
X86: Set the flags for rotate right with carry instructions.
2009-08-05 03:00:23 -07:00
Gabe Black
64d7948692
X86: Handle rotating right all the way around or more.
2009-08-05 03:00:03 -07:00
Gabe Black
88041f75c4
X86: Set the flags on a rotate right instruction.
2009-08-05 02:59:39 -07:00
Gabe Black
029d360db2
X86: Make shifts/rotations that write to 32 bits of a register zero extend.
2009-08-05 02:59:25 -07:00
Gabe Black
7f9a3af250
X86: Handle left rotations that go all the way around or more.
2009-08-05 02:58:54 -07:00
Gabe Black
99adfd9dae
X86: Actually set the flags on a rotate left instruction.
2009-08-05 02:58:20 -07:00
Gabe Black
c087b60af3
X86: Fix the sar carry flag.
2009-08-05 02:58:03 -07:00
Gabe Black
860f0f8350
X86: Fix sign extension when doing an arithmetic shift right by 0.
2009-08-05 02:57:47 -07:00
Gabe Black
a238959c34
X86: Fix the carry flag for shr.
2009-08-05 02:56:49 -07:00
Gabe Black
22a5f66820
X86: Fix the carry flag for shl.
2009-08-05 02:56:38 -07:00
Gabe Black
df2c862a07
X86: Fix how the parity flag is computed.
...
It's only for the lowest order byte, and I had the polarity wrong.
2009-08-05 02:56:12 -07:00
Derek Hower
7f012ef8da
ruby: made mapAddressToRange based off a bit count
2009-08-04 23:05:37 -05:00
Derek Hower
33b28fde7a
slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized controllers
...
This changeset contains a lot of different changes that are too
mingled to separate. They are:
1. Added MOESI_CMP_directory
I made the changes necessary to bring back MOESI_CMP_directory,
including adding a DMA controller. I got rid of MOESI_CMP_directory_m
and made MOESI_CMP_directory use a memory controller. Added a new
configuration for two level protocols in general, and
MOESI_CMP_directory in particular.
2. DMA Sequencer uses a generic SequencerMsg
I will eventually make the cache Sequencer use this type as well. It
doesn't contain an offset field, just a physical address and a length.
MI_example has been updated to deal with this.
3. Parameterized Controllers
SLICC controllers can now take custom parameters to use for mapping,
latencies, etc. Currently, only int parameters are supported.
2009-08-04 12:52:52 -05:00
Derek Hower
c1e0bd1df4
slicc: generate html by default
2009-08-04 12:42:45 -05:00
Nathan Binkert
bd7af84d5e
slicc: better error messages when the python parser fails
2009-08-04 09:37:27 -07:00
Gabe Black
f5c21eaa1a
Merged with head.
2009-08-03 11:06:19 -07:00
Gabe Black
676dc6d292
X86: Fix segment override prefixes on instructions that use rbp/rsp and a displacement.
2009-08-03 11:01:40 -07:00
Derek Hower
ac15e42c17
Automated merge with ssh://hg@m5sim.org/m5
2009-08-03 11:39:08 -05:00
Gabe Black
38c2af17a5
X86: Set up the IDE device correctly, ie. with and using legacy ports.
2009-08-02 18:01:13 -07:00
Gabe Black
80aa771dbc
IDE: Configure the IDE control to reflect the initial value of the command register.
2009-08-02 18:01:09 -07:00
Gabe Black
aff57202b4
X86: Fix the high result of mul1s, and removed undefined shifts from the mult microops.
2009-08-02 08:39:29 -07:00
Steve Reinhardt
a13a706a20
Fix setting of INST_FETCH flag for O3 CPU.
...
It's still broken in inorder.
Also enhance DPRINTFs in cache and physical memory so we
can see more easily whether it's getting set or not.
2009-08-01 22:50:14 -07:00
Steve Reinhardt
1c28004654
Clean up some inconsistencies with Request flags.
2009-08-01 22:50:13 -07:00
Steve Reinhardt
c0755e6085
Rename internal Request fields to start with '_'.
...
The inconsistency was causing a subtle bug with some of the
constructors where the params had the same name as the fields.
This is also a first step to switching the accessors over to
our new "standard", e.g., getVaddr() -> vaddr().
2009-08-01 22:50:10 -07:00
Korey Sewell
aa75b9a7a7
merge mips fix and statetrace changes
2009-07-31 10:40:42 -04:00
Korey Sewell
60063cc700
mips: fix ll/sc pairs working incorrectly because of accidental clobber of LLFLAG
2009-07-31 09:34:29 -04:00
Nathan Binkert
3dd3de5feb
compile: fix accidental conversion of == into =
2009-07-30 17:42:57 -07:00
Gabe Black
4971331b4f
ARM: Mul and mla ignore the c and v flags, but we were setting them to 1.
2009-07-29 22:24:00 -07:00
Derek Hower
d9ff3021ba
ruby: fixed clearStats
2009-07-29 13:46:58 -05:00
Gabe Black
b066e717f4
ARM: Fix an instruction in the cmpxchg kernel provided routine.
...
The instruction was encoded as a load instead of the intended store.
2009-07-29 00:18:26 -07:00
Gabe Black
c2da5bae17
ARM: Get rid of a stray line in the set_tls handler.
2009-07-29 00:17:20 -07:00
Gabe Black
1e04b6281d
ARM: Make the ARM native tracer stop M5 if control diverges.
...
If the control flow of M5's executable and statetrace's target process get out
of sync even a little, there will be a LOT of output, very little of which
will be useful. There's also almost no hope for recovery. In those cases, we
might as well give up and not generate a huge, mostly worthless trace file.
2009-07-29 00:17:11 -07:00
Gabe Black
2871a13ab3
Simple CPU: Make the simple CPU handle the IntRegs trace flag.
2009-07-29 00:15:26 -07:00
Gabe Black
873112ea99
ARM: Make sure the target process doesn't run away from statetrace.
2009-07-29 00:14:43 -07:00
Ali Saidi
0a9eb59e6f
ARM: Ignore the "times" system call.
2009-07-29 00:09:46 -07:00
Ali Saidi
19a4fb0ff3
ARM: Fix an ioctl constant.
2009-07-29 00:09:44 -07:00
Derek Hower
469256d823
ruby: removed unused/incorrect profiler state
2009-07-27 21:43:43 -05:00
Ali Saidi
daf8718da9
ARM: Update some syscall constants and delete others that are Alpha only.
2009-07-27 00:54:55 -07:00
Gabe Black
d3f2992e39
ARM: Decode fstmx and fldmx instructions. We can ignore them for now.
2009-07-27 00:54:50 -07:00
Gabe Black
52b4a7c36f
ARM: Only send information that changed between statetrace and M5.
2009-07-27 00:54:30 -07:00
Gabe Black
90d3d3535b
imported patch nativetracestreamline.patch
2009-07-27 00:54:24 -07:00
Gabe Black
8ec235c7b1
ARM: Make native trace print out what instruction caused an error.
2009-07-27 00:54:09 -07:00
Gabe Black
c18d6cb1a7
ARM: Implement a basic version of the fmxr instruction.
2009-07-27 00:53:29 -07:00
Gabe Black
2828fa459d
ARM: Implement a basic version of the fmrx instruction.
2009-07-27 00:53:24 -07:00
Gabe Black
4079792f2b
ARM: Add in spots for the VFP control registers.
2009-07-27 00:53:10 -07:00
Gabe Black
b560acfe17
ARM: Fix the CLZ instruction.
2009-07-27 00:52:59 -07:00
Gabe Black
dc0df3f396
ARM: Initialize the CPSR so that we're in user mode.
2009-07-27 00:52:48 -07:00
Gabe Black
b8bf34be05
ARM: Set up the initial stack frame to match a recent Linux.
2009-07-27 00:52:31 -07:00
Gabe Black
ebc2897673
Elf: Add in some new aux vector type constants.
2009-07-27 00:52:19 -07:00
Gabe Black
a41e132007
ARM: Make native trace only print when registers are changing value.
...
When registers have incorrect values but aren't actively changing, it's likely
they're not being modified at all. The fact that they're still wrong isn't
very important.
2009-07-27 00:52:01 -07:00
Gabe Black
519ace4dfd
ARM: Add a native tracer.
...
--HG--
rename : src/arch/sparc/SparcNativeTrace.py => src/arch/arm/ArmNativeTrace.py
rename : src/arch/sparc/nativetrace.cc => src/arch/arm/nativetrace.cc
rename : src/arch/sparc/nativetrace.hh => src/arch/arm/nativetrace.hh
2009-07-27 00:51:35 -07:00
Ali Saidi
e7640227ca
ARM: Fix fstat/fstat64 structs to match EABI definitions.
2009-07-27 00:51:20 -07:00
Ali Saidi
99831ed938
ARM: Handle register indexed system calls.
2009-07-27 00:51:01 -07:00
Ali Saidi
0a18bc0d6c
ARM: Detect OABI binaries and complain that they're no-longer supported.
2009-07-27 00:50:55 -07:00
Gabe Black
ef4e8b04a6
SPARC: Fix a minor compile bug in native trace on gcc > 4.1.
2009-07-25 15:14:00 -07:00
Korey Sewell
44f80e7ca5
o3-smt: enforce numThreads parameter for SMT SE mode
2009-07-25 00:50:27 -04:00
Polina Dudnik
e7a3bda497
Fixed the licences plus minor fixes for compilation
2009-07-22 20:28:32 -05:00
Gabe Black
9ba2ed8532
MIPS: Small fix I forgot to qrefresh into my last change.
2009-07-22 01:57:55 -07:00
Gabe Black
7f0c07bf03
MIPS: Style/formatting sweep of the decoder itself.
2009-07-22 01:51:10 -07:00
Gabe Black
c874bfae3f
MIPS: Format the register index constants like the other ISAs.
...
Also a few more style fixes.
2009-07-21 23:38:26 -07:00
Derek Hower
c635d04642
Automated merge with ssh://m5sim.org//repo/m5
2009-07-21 21:27:54 -05:00
Derek Hower
7f34ee36ec
ruby: fixed sequencer RMW data bug
2009-07-21 19:42:09 -05:00
Derek Hower
80544cda8a
ruby: libruby_init now takes parsed Ruby-lang config text
...
libruby_init now expects to get a file that contains the output of
running a ruby-lang configuration, opposed to the ruby-lang
configuration itself.
2009-07-21 18:33:05 -05:00
Gabe Black
74584d79b6
MIPS: Get MIPS_FS to compile, more style fixes.
...
Some breakage was from my BitUnion change, some was much older.
2009-07-21 01:09:05 -07:00
Gabe Black
7548082d3b
MIPS: Many style fixes.
...
White space, commented out code, some other minor fixes.
2009-07-21 01:08:53 -07:00
Gabe Black
dc0a017ed0
isa_parser: Get rid of the now unused ControlBitfieldOperand.
2009-07-20 20:20:17 -07:00
Gabe Black
5161bc19d9
MIPS: Use BitUnions instead of bits() functions and constants.
...
Also fix style issues in regions around these changes.
2009-07-20 20:14:15 -07:00
Derek Hower
225de2eaff
merge
2009-07-20 09:41:28 -05:00
Derek Hower
e59d0e3e89
ruby: moved cache stats from Profiler to CacheMemory
...
Caches are now responsible for their own statistic gathering. This
requires a direct callback from the protocol on misses, and so all
future protocols need to take this into account.
2009-07-20 09:40:43 -05:00
Gabe Black
3e8e813218
CPU: Separate out native trace into ISA (in)dependent code and SimObjects.
...
--HG--
rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc
rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh
rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py
2009-07-19 23:54:56 -07:00
Gabe Black
a3a795769a
Tracing: Add accessors so tracers can get at data in trace records.
2009-07-19 23:54:31 -07:00
Gabe Black
f0cb698a87
X86: Move a displaced comment back to where it goes.
2009-07-19 23:51:47 -07:00
Gabe Black
563654275f
X86: Add some misc registers for FP control state.
2009-07-19 23:51:41 -07:00
Derek Hower
308419b947
scons: removed RubyConfig from scons
2009-07-19 12:34:11 -05:00
Derek Hower
7cd2d8f687
ruby: removed all refs to old RubyConfig
2009-07-18 18:20:03 -05:00
Derek Hower
4bd7fe4c53
ruby: removed dead files
2009-07-18 18:18:37 -05:00
Derek Hower
f3d8d29342
ruby: removed dead files
2009-07-18 18:17:48 -05:00
Derek Hower
926ab6e6db
merge
2009-07-18 17:40:20 -05:00
Derek Hower
4b7ea4cb51
ruby: fixed dma sequencer bug
...
The DMASequencer was still using a parameter from the old RubyConfig,
causing an offset error when the requested data wasn't block aligned.
This changeset also includes a fix to MI_example for a similar bug.
2009-07-18 17:03:51 -05:00
Derek Hower
340845b139
ruby: better debug print for DataBlock
2009-07-18 16:58:33 -05:00
Derek Hower
7433029cd5
slicc: made coherence profilers per-controller
2009-07-18 16:54:45 -05:00
Gabe Black
d85cd08113
X86: Set up a named constant for the "fold bit" for int register indices.
2009-07-17 18:49:22 -07:00
Gabe Black
7b6587fc9c
X86: Tame the wilds of def operands.
2009-07-17 00:29:56 -07:00
Gabe Black
df378285f8
X86: Shift some register flattening work into the decoder.
2009-07-17 00:29:42 -07:00
Polina Dudnik
e557b4beb5
merge
2009-07-16 15:40:48 -05:00
Gabe Black
e9eccf7225
X86: Add range checks for miscreg indexing utility functions.
2009-07-16 09:30:14 -07:00
Gabe Black
ba6b8389ee
X86: Take limitted advantage of the compilers type checking for microop operands.
2009-07-16 09:29:29 -07:00
Gabe Black
80c834ccac
X86: Fix a number of places where the wrong form of a microop was used.
2009-07-16 09:27:56 -07:00
Gabe Black
3f9b0cc5ca
X86: Fix x87 stack register indexing.
2009-07-16 09:26:38 -07:00
Polina Dudnik
23a405f5d8
Tester update
2009-07-15 10:46:22 -05:00
Gabe Black
6262b31515
Merge with head.
2009-07-14 18:06:30 -07:00
Jack Whitham
fce4412d76
ARM: Fix the "open" flag constants.
2009-07-14 21:03:33 -07:00
Polina Dudnik
289cd00326
Changed the state machine to generate code such that multiple processors can make atomic requests at once
2009-07-13 18:39:32 -05:00
Polina Dudnik
5f551d9ca2
1. Got rid of unused functions in DirectoryMemory
...
2. Reintroduced RMW_Read and RMW_Write
3. Defined -2 in the Sequencer as well as made a note about mandatory queue
Did not address the issues in the slicc because remaking the atomics altogether to allow
multiple processors to issue atomic requests at once
2009-07-13 17:22:29 -05:00
Derek Hower
100da6b326
merge
2009-07-13 14:49:51 -05:00
Derek Hower
d51445490d
regression: updated memtest-ruby stats
...
This also includes a change to the default Ruby random seed, which was
previously set using the wall clock. It is now set to 1234 so that
the stat files don't change for the regression tester.
2009-07-13 14:45:15 -05:00
Polina Dudnik
9a675a0391
Changes to add tracing and replaying command-line options
...
Trace is automatically ended upon a manual checkpoint
2009-07-13 12:50:10 -05:00
Polina Dudnik
b28058917c
Locked requests should actually be converted to ST rather than ATOMIC, because ATOMIC is for RMW.
2009-07-13 12:11:17 -05:00
Polina Dudnik
7a6bf67e47
Added atomics implementation which would work for MI_example
2009-07-13 12:06:23 -05:00
Polina Dudnik
c66af9f474
Minor fixes for compiling
2009-07-13 11:59:13 -05:00
Polina Dudnik
7606c71ea5
Replaced RMW with Locked. RMW will be used for the coherence-aided atomics other than LLSC
2009-07-13 11:37:56 -05:00
Polina Dudnik
faf823f947
Moved the lock check and clearing the lock into makeRequest
2009-07-13 11:34:38 -05:00
Polina Dudnik
86ce60e5cd
Forgot to replace one of the RubyRequest_RMW
2009-07-13 11:25:23 -05:00
Polina Dudnik
226981b2a6
Reintegrated Derek's functional implementation of atomics with a minor change: don't clear lock on failure
2009-07-13 11:13:29 -05:00
Gabe Black
60577eb4ca
ISAs: Get rid of the IControl operand type.
...
A separate operand type is not necessary to use two bitfields to generate the
index.
2009-07-10 01:21:04 -07:00
Gabe Black
64fe7af51a
SPARC: Set up a lookup table for integer register flattening.
...
Using a look up table changed the run time of the SPARC_FS solaris boot
regression from:
real 14m45.951s
user 13m57.528s
sys 0m3.452s
to:
real 12m19.777s
user 12m2.685s
sys 0m2.420s
2009-07-10 01:01:47 -07:00
Gabe Black
9993ca8280
X86: Fold the MiscRegFile all the way into the ISA object.
2009-07-09 20:29:02 -07:00
Gabe Black
60d47aa5f9
SPARC: Fold the MiscRegFile all the way into the ISA object.
2009-07-09 20:28:50 -07:00
Gabe Black
de7f462219
MIPS: Fold the MiscRegFile all the way into the ISA object.
2009-07-09 20:28:39 -07:00
Gabe Black
e14c408b62
ARM: Fold the MiscRegFile all the way into the ISA object.
2009-07-09 20:28:27 -07:00
Gabe Black
5643a222e3
Alpha: Missed a file in an earlier changeset.
2009-07-09 00:20:41 -07:00
Gabe Black
c9a27d85b9
Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.
2009-07-08 23:02:22 -07:00
Gabe Black
3d39b62132
Alpha: Pull the MiscRegFile fully into the ISA object.
2009-07-08 23:02:22 -07:00
Gabe Black
b398b8ff1b
Registers: Add a registers.hh file as an ISA switched header.
...
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.
--HG--
rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh
rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh
rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh
rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh
rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh
2009-07-08 23:02:21 -07:00
Gabe Black
997f36c711
Registers: Collapse ARM and MIPS regfile directories.
...
--HG--
rename : src/arch/arm/regfile/misc_regfile.hh => src/arch/arm/misc_regfile.hh
rename : src/arch/arm/regfile/regfile.cc => src/arch/arm/regfile.cc
rename : src/arch/mips/regfile/misc_regfile.cc => src/arch/mips/misc_regfile.cc
rename : src/arch/mips/regfile/misc_regfile.hh => src/arch/mips/misc_regfile.hh
2009-07-08 23:02:21 -07:00
Gabe Black
aa031e1c11
Alpha: Move reg_redir into its own files, and move some constants into regfile.hh.
2009-07-08 23:02:21 -07:00
Gabe Black
5c37d10624
Registers: Eliminate the ISA defined RegFile class.
2009-07-08 23:02:21 -07:00
Gabe Black
9bf22992ee
Alpha: Get rid of function prototypes with no implementations.
2009-07-08 23:02:21 -07:00
Gabe Black
43345bff6c
Registers: Move the PCs out of the ISAs and into the CPUs.
2009-07-08 23:02:21 -07:00
Gabe Black
1b29f1621d
ARM, Simple CPU: Fix an index and add assert checks.
2009-07-08 23:02:21 -07:00
Gabe Black
0338c83c9d
MIPS: Get rid of an orphaned MIPS .cc file.
2009-07-08 23:02:21 -07:00
Gabe Black
6ebce9d65a
Alpha: Phase out Alpha's intregfile.hh and intregfile.cc.
2009-07-08 23:02:21 -07:00
Gabe Black
faa6ebebe1
SPARC: Phase out SPARC's intregfile.hh.
2009-07-08 23:02:20 -07:00
Gabe Black
ecde884404
X86: Phase out x86's intregfile.hh.
2009-07-08 23:02:20 -07:00
Gabe Black
301df68c73
MIPS: Phase out MIPS's int_regfile.hh.
2009-07-08 23:02:20 -07:00
Gabe Black
27b6148f47
ARM: Flush out the ARM's int_regfile.hh.
2009-07-08 23:02:20 -07:00
Gabe Black
a480ba00b9
Registers: Eliminate the ISA defined integer register file.
2009-07-08 23:02:20 -07:00
Gabe Black
0cb180ea0d
Registers: Eliminate the ISA defined floating point register file.
2009-07-08 23:02:20 -07:00
Gabe Black
25884a8773
Registers: Get rid of the float register width parameter.
2009-07-08 23:02:20 -07:00
Gabe Black
32daf6fc3f
Registers: Add an ISA object which replaces the MiscRegFile.
...
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
2009-07-08 23:02:20 -07:00
Gabe Black
3e2cad8370
ARM: Use custom read/write code to alias R15 with the PC.
2009-07-08 23:02:20 -07:00
Gabe Black
b8b7c7314a
ISA parser: Allow alternative read/write code for operands.
2009-07-08 23:02:19 -07:00
Gabe Black
95392d3fb8
ARM: Move the remaining microops out of the decoder and into the ISA desc.
2009-07-08 23:02:19 -07:00
Gabe Black
1d4f338b39
ARM: Move the memory microops out of the decoder and into the ISA desc.
2009-07-08 23:02:19 -07:00
Gabe Black
70a75ceb84
ARM: Move the integer microops out of the decoder and into the ISA desc.
2009-07-08 23:02:19 -07:00
Gabe Black
4eb18cc07a
ARM: Improve memory instruction disassembly.
2009-07-08 23:02:19 -07:00
Gabe Black
2fb8d481ab
ARM: Tune up predicated instruction decoding.
2009-07-08 23:02:19 -07:00
Gabe Black
ddcf084f16
ARM: Get rid of the MemAcc and EAComp static insts.
2009-07-08 23:02:19 -07:00
Gabe Black
cae870eded
ARM: Get rid of end_addr in the ArmMacroStore constructor.
2009-07-08 23:02:19 -07:00
Gabe Black
311f77f33d
ARM: Add an AddrMode2 format for memory instructions that use address mode 2.
2009-07-08 23:02:19 -07:00
Gabe Black
826a3582ea
ARM: Don't always update CPSR.
2009-07-08 23:02:19 -07:00
Gabe Black
17f0943398
ARM: Add an AddrMode3 format for memory instructions that use address mode 3.
2009-07-08 23:02:19 -07:00
Gabe Black
dac0cb5c7e
ARM: Add load/store double instructions.
2009-07-08 23:02:10 -07:00
Gabe Black
1ca0688c4c
ARM: Add operands for the load/store double instructions.
2009-07-08 23:02:01 -07:00
Gabe Black
d029110fa1
X86: Fix a bug in IRET_PROT's microcode. The immediate form of sra was intended.
2009-07-08 23:01:54 -07:00
Derek Hower
15afc87f7c
slicc: fixed MI_example bug. The directory wasn't deallocating the TBE, leading to a leak. Also increased the default max TBE size to 256 to allow memtest to pass the regression.
2009-07-08 08:40:32 -05:00
Derek Hower
6a83bd5a03
ruby: set the default values of the debug object so that nothing is printed
2009-07-08 00:34:40 -05:00
Derek Hower
2f9d8bff5b
slicc: Fixed MI_example bug. The directory was not writing data to DRAM after a PUTX.
2009-07-08 00:31:33 -05:00
Derek Hower
96c36afea9
removed stray debug print
2009-07-07 23:01:35 -05:00
Nathan Binkert
7ffb8e5914
automerge
2009-07-06 15:54:18 -07:00
Nathan Binkert
da704f52e5
ruby: Fix RubyMemory to work with the newer ruby.
2009-07-06 15:49:47 -07:00
Nathan Binkert
a7904e2cf3
ruby: apply some fixes that were overwritten by the recent ruby import.
2009-07-06 15:49:47 -07:00
Nathan Binkert
5b080ae046
slicc: update parser.py for changes in slicc language.
2009-07-06 15:49:47 -07:00
Nathan Binkert
1f6933503d
scons: update SCons files for changes in ruby.
2009-07-06 15:49:47 -07:00
Nathan Binkert
92de70b69a
ruby: Import the latest ruby changes from gems.
...
This was done with an automated process, so there could be things that were
done in this tree in the past that didn't make it. One known regression
is that atomic memory operations do not seem to work properly anymore.
2009-07-06 15:49:47 -07:00
Nathan Binkert
05f6a4a6b9
ruby: replace strings that were missed in original ruby import.
2009-07-06 15:49:47 -07:00
Gabe Black
240e214236
SPARC: Fix the parenthesis in inUserMode.
2009-07-05 16:07:09 -07:00
Jack Whitham
a223a065e6
ARM: Fix how address mode bits are handled.
2009-07-02 23:23:06 -07:00
Jack Whitham
a738006397
ARM: Fix the code snippet for mla.
2009-07-02 23:22:58 -07:00
Nathan Binkert
7daed385bf
typo: correct spelling
2009-07-02 16:48:22 -07:00
Nathan Binkert
6fd3987b3f
attrdict: correct delattr
2009-07-02 16:48:22 -07:00
Gabe Black
26c70ce2cb
ARM: Make DataOps select from a set of ways to set the c and v flags.
2009-07-01 22:17:06 -07:00
Gabe Black
148c265cf3
ARM: Get rid of some bitfields that aren't used. A few may need to be readded.
2009-07-01 22:16:51 -07:00
Gabe Black
7172e26cc4
ARM: Add a findLsbSet function and use it to implement clz.
2009-07-01 22:16:36 -07:00
Gabe Black
f5141c23fd
ARM: Add defaults for DataOp flag code.
2009-07-01 22:16:19 -07:00
Gabe Black
22a1ac22f4
ARM: Get rid of the val2 variable.
2009-07-01 22:16:05 -07:00
Gabe Black
ce9cb1ecb5
ARM: Centralize the declaration of resTemp.
2009-07-01 22:15:39 -07:00
Gabe Black
776a06fd39
ARM: Add a DataImmOp format similar to DataOp.
2009-07-01 22:12:10 -07:00
Gabe Black
4f98171479
ARM: Decode some media instructions. These are untested.
2009-07-01 22:11:54 -07:00
Gabe Black
b8f064c88c
ARM: Use the new DataOp format to simplify the decoder.
2009-07-01 22:11:39 -07:00
Gabe Black
f409d7819d
ARM: Add in some new artificial fields that make decoding a little easier.
2009-07-01 22:11:27 -07:00
Gabe Black
1f0c0a6688
ARM: Recognize the IntRegs trace flag.
2009-07-01 22:11:12 -07:00
Gabe Black
065cb59427
ARM: Add a DataOp format so data op definitions can be aggregated.
2009-07-01 22:10:58 -07:00
Gabe Black
1ea14b8fac
ARM: Show more information when disassembling data processing intstructions.
...
This will need more work, but it should be a lot closer.
2009-06-27 00:30:23 -07:00
Gabe Black
56f1845471
ARM: Show branch targets relative to the nearest symbol.
2009-06-27 00:29:30 -07:00
Gabe Black
a4ac3fad7a
ARM: Write a function for printing mnemonics and predicates.
2009-06-27 00:29:12 -07:00
Gabe Black
38d8bc64ba
ARM: Fill out the printReg function.
2009-06-26 22:01:34 -07:00
Jack Whitman
7b5386d390
ARM: Fix signed multiply long and add some unimplemented loads.
2009-06-24 21:22:52 -07:00
Jack Whitman
853a0858f3
ARM: Link register is trashed by non-executed branch and link operations.
2009-06-24 21:22:46 -07:00
Jack Whitman
6dd4272804
ARM: Added unimplemented load/store multiple instructions.
2009-06-23 23:23:25 -07:00
Gabe Black
d744525273
ARM: Simplify some utility functions.
2009-06-21 22:51:13 -07:00
Gabe Black
5c2a362cb7
ARM: Move util functions out of the isa desc.
2009-06-21 22:50:33 -07:00
Gabe Black
d4a03f1900
ARM: Simplify the ISA desc by pulling some classes out of it.
2009-06-21 17:21:25 -07:00
Gabe Black
2a39570b78
ARM: Remove the currently unecessary FPAOp class.
2009-06-21 17:14:51 -07:00
Gabe Black
d1d733f636
ARM: Make inst bitfields accessible outside of the isa desc.
2009-06-21 16:41:21 -07:00
Gabe Black
47e71d674a
ARM: Don't downconvert ExtMachInsts to MachInsts.
2009-06-21 16:41:07 -07:00
Gabe Black
f1657a890e
BitUnion: Add more constiness.
2009-06-21 16:40:33 -07:00
Gabe Black
7e4f132369
ARM: Get rid of a few more unused operands.
2009-06-21 09:48:51 -07:00
Gabe Black
4415e2dcd6
ARM: Get rid of unnecessary Re operand.
2009-06-21 09:48:44 -07:00
Gabe Black
7d4ef8a398
ARM: Clear out some inherited hangers on in util.isa and utility.hh.
2009-06-21 09:43:55 -07:00
Gabe Black
5bc1373050
ARM: Get rid of unnecessary fp_enable_checks.
2009-06-21 09:41:04 -07:00
Gabe Black
3964709711
ARM: Adjust simplify rotate_imm slightly.
2009-06-21 09:38:54 -07:00
Gabe Black
c20ce20e4c
ARM: Make the isa parser aware that CPSR is being used.
2009-06-21 09:37:41 -07:00
Gabe Black
71e0d1ded2
ARM: Pull some static code out of the isa desc and create miscregs.hh.
2009-06-21 09:21:07 -07:00
Gabe Black
19a1966079
ARM: Get rid of unused postacc_code.
2009-06-21 09:16:55 -07:00
Nathan Binkert
e1eacc8d92
scons: Make shared library builds work again
...
Compile gzstream as position independent code
use the PIC version of date for shared libs...oops
2009-06-12 21:19:16 -07:00
Nathan Binkert
d3d8a5a83b
copyright: I missed some copyrights during ruby integration
2009-06-10 00:41:56 -07:00
Gabe Black
b394242240
ARM: Hook in the mmap2 system call. Make ArmLinuxProcess handle 5,6 syscall params.
2009-06-09 23:41:45 -07:00
Gabe Black
c913c64be2
ARM: Add a memory_barrier function to the "comm page".
...
This function doesn't actually provide a memory barrier (I don't think they're
implemented) and instead just returns.
2009-06-09 23:41:35 -07:00
Gabe Black
3ff1e922c2
ARM: Add a cmpxchg implementation to the "comm page".
...
This implementation does what it's supposed to (I think), but it's not atomic
and doesn't have memory barriers like the kernel's version.
2009-06-09 23:41:03 -07:00
Gabe Black
37ac2871d5
ARM: Implement TLS. This is not tested.
2009-06-09 23:39:07 -07:00
Gabe Black
5daeefc505
ARM: Make ArmLinuxProcess understand "ARM private" system calls.
2009-06-09 23:38:50 -07:00
Gabe Black
fbf4dc9da2
ARM: Update the kernel version M5 reports to 2.6.16.19
2009-06-09 23:37:41 -07:00
Nathan Binkert
baa0d695b2
cleanup: Make use of types properly and make the loop a little more clear.
2009-06-05 17:01:19 -07:00
Nathan Binkert
c76a8b1c15
scons: Make it so that the processing of trace flags does not depend on order
2009-06-05 15:20:09 -07:00
Nathan Binkert
a01437ab03
types: need typename keyword to get the type.
2009-06-05 11:40:02 -07:00
Nathan Binkert
6faf377b53
types: clean up types, especially signed vs unsigned
2009-06-04 23:21:12 -07:00
Nathan Binkert
4e34266245
move: put predictor includes and cc files into the same place
...
--HG--
rename : src/cpu/2bit_local_pred.cc => src/cpu/pred/2bit_local.cc
rename : src/cpu/o3/2bit_local_pred.hh => src/cpu/pred/2bit_local.hh
rename : src/cpu/btb.cc => src/cpu/pred/btb.cc
rename : src/cpu/o3/btb.hh => src/cpu/pred/btb.hh
rename : src/cpu/ras.cc => src/cpu/pred/ras.cc
rename : src/cpu/o3/ras.hh => src/cpu/pred/ras.hh
rename : src/cpu/tournament_pred.cc => src/cpu/pred/tournament.cc
rename : src/cpu/o3/tournament_pred.hh => src/cpu/pred/tournament.hh
2009-06-04 21:50:20 -07:00
Nathan Binkert
e30c62ad99
style: cleanup style
2009-06-04 21:41:46 -07:00
Nathan Binkert
b08c361911
swig: %include Event before PythonEvent so python gets the subclass correct.
...
Before this change, some versions of swig would cause PythonEvent to be
derived from object instead of Event
2009-06-01 16:38:57 -07:00
Nathan Binkert
a0104b6ff6
request: add accessor and constructor for setting time other than curTick
2009-05-29 15:30:16 -07:00
Gabe Black
7f50ea05ac
X86: Keep track of more descriptor state to accomodate KVM.
2009-05-28 23:27:56 -07:00
Nathan Binkert
47877cf2db
types: add a type for thread IDs and try to use it everywhere
2009-05-26 09:23:13 -07:00
Gabe Black
d93392df28
X86: Really set up the GDT and various hidden/visible segment registers.
2009-05-26 02:23:08 -07:00
Steve Reinhardt
b3d0a01eb3
igbe: Fix descriptor cache bug.
2009-05-20 21:52:32 -07:00
Nathan Binkert
8d2e51c7f5
includes: sort includes again
2009-05-17 14:34:52 -07:00
Nathan Binkert
709d859530
includes: use base/types.hh not inttypes.h or stdint.h
2009-05-17 14:34:51 -07:00
Nathan Binkert
eef3a2e142
types: Move stuff for global types into src/base/types.hh
...
--HG--
rename : src/sim/host.hh => src/base/types.hh
2009-05-17 14:34:50 -07:00
Nathan Binkert
cbf237897f
stats: tidy up the Distribution type a little bit
2009-05-13 07:18:03 -07:00
Nathan Binkert
cfa9c78100
stats: fancy is a bad name
2009-05-13 07:18:02 -07:00
Nathan Binkert
74c595d739
stats: clean up the code for printing stats
2009-05-13 07:18:01 -07:00
Korey Sewell
97a04b16eb
mips-merge: merge hello world regress for inorder cpu
...
w/latest changes
2009-05-13 02:02:05 -04:00
Nathan Binkert
5207586b26
ruby: deal with printf warnings and convert some to cprintf
2009-05-12 22:33:05 -07:00
Nathan Binkert
016d472c46
ruby: remove random uint typedef and use unsigned
2009-05-12 22:33:05 -07:00
Nathan Binkert
7389dc63b2
ruby: Make ruby's Map use hashmap.hh to simplify things.
2009-05-12 22:33:05 -07:00
Nathan Binkert
82c9e6a5fc
gcc: work around a bogus gcc error
2009-05-12 22:33:05 -07:00
Nathan Binkert
0c2b9cf90d
slicc: work around improper initialization of a global in slicc.
2009-05-12 22:33:05 -07:00
Nathan Binkert
d923ce0f8c
slicc: clean up the slicc environment so things build properly on mac.
2009-05-12 22:33:04 -07:00
Korey Sewell
1f4c954590
inorder-mips: Remove eaComp & memAcc; use 'visible' eaComp
...
Inorder expects eaComp to be visible through StaticInst object. This mirrors a similar change
to ALPHA... Needs to be done for SPARC and whatever other ISAs want to use InOrderCPU
2009-05-13 01:26:46 -04:00
Korey Sewell
bc69e7947c
arch-mips: add regWidth constant to float regfile
2009-05-13 01:26:38 -04:00
Korey Sewell
a032d91016
cpus: add InOrderCPU to default build
...
regressions need this so they build the model
2009-05-12 20:55:21 -04:00
Korey Sewell
5d810c30e6
alpha-isa: add mt.hh so it can compile with inorder
2009-05-12 20:18:34 -04:00
Korey Sewell
6c88730540
inorder-resources: delete events
...
make sure unrecognized events in the resource pool are deleted and also delete resource events in destructor
2009-05-12 15:01:16 -04:00
Korey Sewell
db2b721380
inorder-tlb-cunit: merge the TLB as implicit to any memory access
...
TLBUnit no longer used and we also get rid of memAccSize and memAccFlags functions added to ISA and StaticInst
since TLB is not a separate resource to acquire. Instead, TLB access is done before any read/write to memory
and the result is checked before it's sent out to memory.
* * *
2009-05-12 15:01:16 -04:00
Korey Sewell
3a057bdbb1
inorder-tlb: squash insts in TLB correctly
...
TLB had a bug where if it was stalled and waiting , it would not squash all instructions older than squashed instruction correctly
* * *
2009-05-12 15:01:16 -04:00
Korey Sewell
f1c97e830b
inorder-faults: ignore unalign translation faults for prefetches
2009-05-12 15:01:16 -04:00
Korey Sewell
fe4cd9847d
inorder-stc: update interface to handle store conditionals
2009-05-12 15:01:15 -04:00
Korey Sewell
6211fe5d2e
inorder-float: Fix storage of FP results
...
inorder was incorrectly storing FP values and confusing the integer/fp storage view of floating point operations. A big issue was knowing trying to infer when were doing single or double precision access
because this lets you know the size of value to store (32-64 bits). This isnt exactly straightforward since alpha uses all 64-bit regs while mips/sparc uses a dual-reg view. by getting this value from
the actual floating point register file, the model can figure out what it needs to store
2009-05-12 15:01:15 -04:00
Korey Sewell
3603dd25ef
inorder-fetch: update model to use predecoder
2009-05-12 15:01:15 -04:00
Korey Sewell
c9a03f549b
inorder-mem: clean up allocation/deletion of requests/packets
...
* * *
2009-05-12 15:01:15 -04:00
Korey Sewell
1c7e988272
inorder-mem: skeleton support for prefetch/writehints
2009-05-12 15:01:15 -04:00
Korey Sewell
f41df0ee08
inorder-o3: allow both to compile together
...
allow InOrder and O3CPU to be compiled at the same time: need to make branch prediction filed shared by both models
2009-05-12 15:01:14 -04:00
Korey Sewell
5127ea226a
inorder-unified-tlb: use unified TLB instead of old TLB model
2009-05-12 15:01:14 -04:00
Korey Sewell
98b1452058
inorder-miscregs: Fix indexing for misc. reg operands and update result-types for better tracing of these types of values
2009-05-12 15:01:14 -04:00
Korey Sewell
2012202b06
inorder/alpha-isa: create eaComp object visible to StaticInst through ISA
...
Remove subinstructions eaComp/memAcc since unused in CPU Models. Instead, create eaComp that is visible from StaticInst object. Gives InOrder model capability of generating address without actually initiating access
* * *
2009-05-12 15:01:14 -04:00
Korey Sewell
b569f8f0ed
inorder-bpred: edits to handle non-delay-slot ISAs
...
Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline
2009-05-12 15:01:14 -04:00
Korey Sewell
1c8dfd9254
inorder-alpha-port: initial inorder support of ALPHA
...
Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions
* * *
Remove namespace from header file. Causes compiler issues that are hard to find
* * *
Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time
* * *
Expose memory access size and flags through instruction object
(temporarily memAccSize and memFlags to get TLB stuff working.)
2009-05-12 15:01:13 -04:00
Korey Sewell
63db33c4b1
isa-parser: made a few changes, but not author-worthy
2009-05-12 15:01:13 -04:00
Nathan Binkert
f21e80ec72
ruby: assert(false) should be panic.
...
This also fixes some compiler warnings
2009-05-11 16:32:32 -07:00
Nathan Binkert
c2c68c66b7
stats: remove a few compat leftovers
2009-05-11 11:18:09 -07:00
Nathan Binkert
20f1da8b96
python: pull out common code from main that processes arguments
2009-05-11 11:18:09 -07:00
Nathan Binkert
5de3b2b6f0
stats: forgot an include for the mysql stuff
2009-05-11 11:18:09 -07:00
Nathan Binkert
5b752c1e31
scons: add include guards to info.hh
2009-05-11 11:18:09 -07:00
Nathan Binkert
cf6b4ef734
ruby: add RUBY sticky option that must be set to add ruby to the build
...
Default is false
2009-05-11 10:38:46 -07:00
Daniel Sanchez
93f2f69657
ruby: Working M5 interface and updated Ruby interface.
...
This changeset also includes a lot of work from Derek Hower <drh5@cs.wisc.edu>
RubyMemory is now both a driver for Ruby and a port for M5. Changed
makeRequest/hitCallback interface. Brought packets (superficially)
into the sequencer. Modified tester infrastructure to be packet based.
and Ruby can be used together through the example ruby_se.py
script. SPARC parallel applications work, and the timing *seems* right
from combined M5/Ruby debug traces. To run,
% build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c
tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t
2009-05-11 10:38:46 -07:00
Steve Reinhardt
ebf2f5aadd
ruby: Check stderr and not stdin before hanging on an assert.
2009-05-11 10:38:46 -07:00
Polina Dudnik
7769cc9092
ruby: decommission code
...
1. Set.* and BigSet.* are replaced with OptBigSet.* which was renamed Set.*
2. Decomissioned all bloom filters
3. Decomissioned ruby/simics directory
2009-05-11 10:38:46 -07:00
Derek Hower
0ccf8f35a5
ruby: removed dead functions from the sequencer
2009-05-11 10:38:46 -07:00
Polina Dudnik
29f82f265a
ruby: Removed g_SIMULATING flag
...
1. removed checks from tester files
2. removed else clause in Sequencer and DirectoryMemory else clause is
needed by the tester, it is up to Derek to revive it elsewhere when he
gets to it
Also:
1. Changed m_entries in DirectoryMemory to a map
2. And replaced SIMICS_read_physical_memory with a call to now-dummy
Derek's-to-be readPhysMem function
2009-05-11 10:38:46 -07:00
Polina Dudnik
b271090923
ruby: Remove transactional access types (e.g. LD_XACT) from CacheRequestType
...
1. Modified enumeration
2. Also modified profiler
3. Remove transactions from Tester
4. Edited XACT_MEM out of Synthetic Driver
2009-05-11 10:38:46 -07:00
Polina Dudnik
9f34659c52
ruby: reordered Debug and RubyConfig::init to fix segfault
...
due to uninitialized output file pointer.
2009-05-11 10:38:46 -07:00
Dan Gibson
8cbf8df5b7
ruby: Disabled RubyEventQueue's deletion of its home-grown priority heap.
...
Temporarily to fix unusual memory problem.
2009-05-11 10:38:46 -07:00
Nathan Binkert
7311fd7182
ruby: Migrate all of ruby and slicc to SCons.
...
Add the PROTOCOL sticky option sets the coherence protocol that slicc
will parse and therefore ruby will use. This whole process was made
difficult by the fact that the set of files that are output by slicc
are not easily known ahead of time. The easiest thing wound up being
to write a parser for slicc that would tell me. Incidentally this
means we now have a slicc grammar written in python.
2009-05-11 10:38:46 -07:00
Nathan Binkert
e40b8e34c8
ruby: clean up a few warnings
2009-05-11 10:38:45 -07:00
Dan Gibson
8b9f70b9e4
ruby: Fixed some unresolved references.
2009-05-11 10:38:45 -07:00
Nathan Binkert
24da30e317
ruby: Make ruby #includes use full paths to the files they're including.
...
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
2009-05-11 10:38:45 -07:00
Dan Gibson
d8c592a05d
ruby: remove unnecessary code.
...
1) Removing files from the ruby build left some unresovled
symbols. Those have been fixed.
2) Most of the dependencies on Simics data types and the simics
interface files have been removed.
3) Almost all mention of opal is gone.
4) Huge chunks of LogTM are now gone.
5) Handling 1-4 left ~hundreds of unresolved references, which were
fixed, yielding a snowball effect (and the massive size of this
delta).
2009-05-11 10:38:45 -07:00
Derek Hower
6ceaffd724
ruby: Cleaned up sequencer. Removed LogTM specific code.
2009-05-11 10:38:45 -07:00
Derek Hower
3d2acc547c
ruby: added Packet interface to makeRequest and isReady.
...
Also pushed Packet usage into the Sequencer
2009-05-11 10:38:45 -07:00
Nathan Binkert
e1915f16d1
ruby: fold the debugging options into Debug.cc
2009-05-11 10:38:45 -07:00
Derek Hower
6e8373fad6
ruby: Renamed Ruby's EventQueue to RubyEventQueue
...
--HG--
rename : src/mem/ruby/eventqueue/EventQueue.cc => src/mem/ruby/eventqueue/RubyEventQueue.cc
rename : src/mem/ruby/eventqueue/EventQueue.hh => src/mem/ruby/eventqueue/RubyEventQueue.hh
rename : src/mem/ruby/eventqueue/EventQueueNode.cc => src/mem/ruby/eventqueue/RubyEventQueueNode.cc
rename : src/mem/ruby/eventqueue/EventQueueNode.hh => src/mem/ruby/eventqueue/RubyEventQueueNode.hh
2009-05-11 10:38:45 -07:00
Daniel Sanchez
ab5e4a22b3
ruby: Removed System name clash by renaming ruby's System to RubySystem
2009-05-11 10:38:44 -07:00
Nathan Binkert
84a18e7fdc
ruby: rename config.include to config.hh and clean up the macro stuff.
...
I did the macro cleanup because I was worried that the SCons scanner
would get confused. This code will hopefully go away soon anyway.
--HG--
rename : src/mem/ruby/config/config.include => src/mem/ruby/config/config.hh
2009-05-11 10:38:44 -07:00
Nathan Binkert
b05da09cd6
ruby: strip out some unused defines
2009-05-11 10:38:44 -07:00
Nathan Binkert
2f30950143
ruby: Import ruby and slicc from GEMS
...
We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
2009-05-11 10:38:43 -07:00
Korey Sewell
c70241810d
cpus: fix cpu progress event
...
this was double scheduling itself (once in constructor and once in cpu code). also add support for stopping / starting
progress events through repeatEvent flag and also changing the interval of the progress event as well
2009-05-05 02:51:31 -04:00
Nathan Binkert
dc35d2f125
scons: re-work the *Source functions to take more information.
...
Start by turning all of the *Source functions into classes
so we can do more calculations and more easily collect the data we need.
Add parameters to the new classes for indicating what sorts of flags the
objects should be compiled with so we can allow certain files to be compiled
without Werror for example.
2009-05-04 16:58:24 -07:00
Gabe Black
7146eb79f1
X86: Precompute the default and alternate address and operand size and the stack size.
2009-04-26 16:49:24 -07:00
Gabe Black
b6bfe8af26
X86: Split out the internal memory space from the regular translate() and precompute mode.
2009-04-26 16:48:44 -07:00
Gabe Black
4ee34dfb4e
X86: Centralize updates to the handy M5 reg.
2009-04-26 16:47:48 -07:00
Gabe Black
06b3e3c303
X86: Implement lowest priority interrupts more correctly.
...
Lowest priority interrupts are now delivered based on a rotating offset into
the list of potential recipients. There could be parasitic cases were a
processor gets picked on and ends up at that rotating offset all the time, but
it's much more likely that the group will stay consistent and the pain will be
distributed evenly.
2009-04-26 02:09:54 -07:00
Gabe Black
2f34a7eaeb
X86: Tell the function that sends int messages who to send to instead of figuring it out itself.
2009-04-26 02:09:27 -07:00
Gabe Black
88ab4bb257
X86: Make the local APICs register themselves with the IO APIC.
...
This is a hack so that the IO APIC can figure out information about the local
APICs. The local APICs still have no way to find out about each other.
Ideally, when the local APICs update state that's relevant to somebody else,
they'd send an update to everyone. Without being able to do a broadcast, that
would still require knowing who else there is to notify. Other broadcasts are
implemented using assumptions that may not always be true.
2009-04-26 02:09:13 -07:00
Gabe Black
c5e2cf841d
X86: Record the initial APIC ID which identifies an APIC in M5.
...
The ID as exposed to software can be changed. Tracking those changes in M5
would be cumbersome, especially since there's no guarantee the IDs will remain
unique.
2009-04-26 02:06:21 -07:00
Gabe Black
8d84f81e70
X86, Config: Make makeX86System consider the number of CPUs, and clean up interrupt assignment.
2009-04-26 02:04:32 -07:00
Gabe Black
9d0fa27d09
SPARC: Tighten up the clone system call and SPARCs copyRegs.
2009-04-24 23:11:21 -07:00
Steve Reinhardt
7c056e44e5
request: reorganize flags to group related flags together.
2009-04-23 06:44:32 -07:00
Gabe Black
ee7055c289
X86: Put the StoreCheck flag with the others, and don't collide with other flags.
2009-04-23 01:43:00 -07:00
Nathan Binkert
b4816037ba
stats: expose statistics to python
2009-04-22 13:38:01 -07:00
Nathan Binkert
aa9b4e6a68
stats: Move flags into info.hh and use base/flags.hh to manage the flags
2009-04-22 13:38:01 -07:00
Nathan Binkert
8c3eb1a192
stats: Shuffle around info stuff so it can be accessed separately
2009-04-22 13:38:00 -07:00
Nathan Binkert
4d9f25b75c
stats: Rename the info classes to hopefully make things a bit clearer
...
FooInfoBase became FooInfo
FooInfo became FooInfoProxy
2009-04-22 13:38:00 -07:00
Nathan Binkert
ca3d82b38a
stats: remove simplescalar compatibility for printing
2009-04-22 10:25:14 -07:00
Nathan Binkert
61a68371be
stats: fix initialization bug in distribution text output
2009-04-22 06:44:29 -07:00
Steve Reinhardt
e7fa4f2f8e
i8254xGBe: major style overhaul.
...
Moved DescCache template functions from .hh to .cc file.
Also fixed lots of line-wrapping problems, and some irregular indentation.
2009-04-22 01:58:53 -04:00
Steve Reinhardt
6629d9b2bc
mem: use single BadAddr responder per system.
...
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond. Now there is just one on
the main memory bus. The default bus responder on all other buses
is now the downstream cache's cpu_side port. Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
2008-07-16 11:10:33 -07:00
Nathan Binkert
4d001e43da
Automated merge with ssh://m5sim.org//repo/m5
2009-04-21 16:04:55 -07:00
Nathan Binkert
fcc142463d
pseudo: only include kernel stats if FULL_SYSTEM.
2009-04-21 15:40:26 -07:00
Nathan Binkert
43c7698f49
arm: include missing file for arm
2009-04-21 15:40:26 -07:00
Nathan Binkert
50f1570352
arm: Unify the ARM tlb. We forgot about this when we did the rest.
...
This code compiles, but there are no tests still
2009-04-21 15:40:25 -07:00
Steve Reinhardt
03b3925e58
syscall_emul: style fixes (mostly wrapping overly long lines)
2009-04-21 08:17:36 -07:00
Steve Reinhardt
52b6764f31
syscall: Resolve conflicts between m5threads and Gabe's recent SE changes.
2009-04-21 08:17:36 -07:00
Daniel Sanchez
b0e9654f86
Commit m5threads package.
...
This patch adds limited multithreading support in syscall-emulation
mode, by using the clone system call. The clone system call works
for Alpha, SPARC and x86, and multithreaded applications run
correctly in Alpha and SPARC.
2009-04-21 08:17:36 -07:00
Nathan Binkert
b0489d18ed
SCons: Export export_vars so SConsopts files can add to them
2009-04-21 08:17:36 -07:00
Steve Reinhardt
97b6947eb7
Minor tweaks for future Ruby compatibility.
2009-04-21 08:17:36 -07:00
Steve Reinhardt
eb3b6935d3
request: add PREFETCH flag.
2009-04-21 08:17:10 -07:00
Steve Reinhardt
3083268d60
request: rename INST_READ to INST_FETCH.
2009-04-20 18:54:02 -07:00
Steve Reinhardt
7f8ea68a30
request: split public and private flags into separate fields.
...
This frees up needed space for more public flags. Also:
- remove unused Request accessor methods
- make Packet use public Request accessors, so it need not be a friend
2009-04-20 18:40:00 -07:00
Gabe Black
9e9a34fed1
Mem: Fill out the comment that describes the LOCKED request flag.
2009-04-19 22:00:24 -07:00
Gabe Black
bd6f2bb538
Mem: Change isLlsc to isLLSC.
2009-04-19 21:44:15 -07:00
Gabe Black
089b384086
X86: Fix the functions that manipulate large bit arrays in the local APIC.
2009-04-19 13:47:15 -07:00
Gabe Black
eee74ba427
X86: Fix up a copyright.
2009-04-19 13:17:35 -07:00
Gabe Black
6910baa015
X86: Fix how the TLB handles the storecheck flag.
2009-04-19 04:57:51 -07:00
Gabe Black
0a6ff60caa
X86: Recognize and handle the lock legacy prefix.
2009-04-19 04:57:28 -07:00
Gabe Black
61edc9ba66
X86: Implement a locking version of XADD.
2009-04-19 04:56:49 -07:00
Gabe Black
209cfc89fd
X86: Implement a locking version of BTC.
2009-04-19 04:56:45 -07:00
Gabe Black
e475cf85f0
X86: Implement a locking version of BTR.
2009-04-19 04:56:43 -07:00
Gabe Black
43f58927d6
X86: Implement a locking version of CMPXCHG.
2009-04-19 04:56:40 -07:00
Gabe Black
b493906eb9
X86: Implement a locking version of BTS.
2009-04-19 04:56:36 -07:00
Gabe Black
985d959ea6
X86: Implement a locking version of DEC.
2009-04-19 04:56:34 -07:00
Gabe Black
4f2d4f466a
X86: Implement a locking version of INC.
2009-04-19 04:56:31 -07:00
Gabe Black
2394f73f90
X86: Implement a locking version of NEG.
2009-04-19 04:56:28 -07:00
Gabe Black
9b9b7a412c
X86: Implement a locking version of NOT.
2009-04-19 04:56:25 -07:00
Gabe Black
b8f81c62a2
X86: Implement a locking version of XCHG.
2009-04-19 04:56:22 -07:00
Gabe Black
750f5a0a67
X86: Implement a locking version of XOR.
2009-04-19 04:56:20 -07:00
Gabe Black
cfb289ebeb
X86: Implement a locking version of SUB.
2009-04-19 04:56:16 -07:00
Gabe Black
789b3191b9
X86: Implement a locking version of AND.
2009-04-19 04:56:14 -07:00
Gabe Black
e742cad6f4
X86: Implement a locking version of SBB.
2009-04-19 04:56:11 -07:00
Gabe Black
193265c6e5
X86: Implement a locking version of ADC.
2009-04-19 04:56:08 -07:00
Gabe Black
2f607b882c
X86: Implement a locking version of OR.
2009-04-19 04:56:06 -07:00
Gabe Black
a7f79c9049
X86: Implement a locking version of ADD.
2009-04-19 04:56:02 -07:00
Gabe Black
d90456a486
X86: Implement the stul microop.
...
This microop does a store and unlocks the requested address. The RISC86
microop ISA doesn't seem to have an equivalent to this, so I'm guessing that
the store following an ldstl is automatically unlocking. We don't do it this
way for performance reasons since the behavior is the same.
2009-04-19 04:55:58 -07:00
Gabe Black
d2554ff030
X86: Implement the ldstl microop.
...
This microop does a load, checks that a store would succeed, and locks the
requested address.
2009-04-19 04:55:43 -07:00
Gabe Black
1a8a765a5c
CPUs: Make the atomic CPU support locked memory accesses.
2009-04-19 04:50:07 -07:00
Gabe Black
742c3f045e
Memory: Add a LOCKED flag back in for x86 style locking.
2009-04-19 04:39:25 -07:00
Gabe Black
3e5f487663
Memory: Rename LOCKED for load locked store conditional to LLSC.
2009-04-19 04:25:01 -07:00
Gabe Black
ca85981478
SE mode: Make keeping track of the number of syscalls less hacky.
2009-04-19 04:15:32 -07:00
Gabe Black
e174239bd8
X86: Mask the PIC at startup to avoid a glitch which causes an NMI.
2009-04-19 04:15:06 -07:00
Gabe Black
5f164ba720
X86: Actually handle 16 bit mode modrm.
2009-04-19 04:14:31 -07:00
Gabe Black
93cccf7d19
X86: Make the TEST instruction set all the flags it's supposed to.
2009-04-19 04:14:16 -07:00
Gabe Black
f82c123242
X86: Implement broadcast IPIs.
2009-04-19 04:14:01 -07:00
Gabe Black
829e424353
X86: Fix the ordering of the vendor string reported by CPUID.
2009-04-19 04:13:45 -07:00
Gabe Black
8b2ac20753
X86: Keep track of what the initial count value was in the LAPIC timer.
2009-04-19 03:56:57 -07:00
Gabe Black
18b3863127
X86: Only recognize the first startup IPI after INIT or reset.
2009-04-19 03:56:36 -07:00
Gabe Black
4d32cd10ce
X86: Use recvResponse to implement the idle bit in the Local APIC ICR.
2009-04-19 03:56:24 -07:00
Gabe Black
bdda224d41
X86: Add a function which gets called when an interrupt message has been delivered.
2009-04-19 03:54:11 -07:00
Gabe Black
3031af21c7
X86: Fix the flags for interrupt response messages.
2009-04-19 03:53:29 -07:00
Gabe Black
3eed59768c
X86: Explicitly use the right width in a few places that need a 64 bit value.
2009-04-19 03:47:59 -07:00
Gabe Black
8761057c78
X86: Keep track of the pioAddr for the local APIC.
2009-04-19 03:47:12 -07:00
Gabe Black
038225a6ca
X86: Implement far jmp.
2009-04-19 03:42:41 -07:00
Gabe Black
3b1b21cb15
X86: Some segment selectors can be used when "NULL".
2009-04-19 03:41:10 -07:00
Gabe Black
a0cc081997
X86: Fix a bug in the chks microop where it ignored that it found a fault.
2009-04-19 03:40:08 -07:00
Gabe Black
f2ff5b9249
X86: Make the interrupt entering microcode record the value to use, not actually use it.
2009-04-19 03:36:57 -07:00
Gabe Black
35eea4191b
X86: LEA calculates an address before segmentation.
2009-04-19 03:24:51 -07:00
Gabe Black
bdd55ec8b6
X86: Implement the save machine status word instruction (SMSW).
2009-04-19 03:22:38 -07:00
Gabe Black
d86cd1d2a0
X86: Implement the load machine status word instruction (LMSW).
2009-04-19 03:17:14 -07:00
Gabe Black
eba640c963
X86: Only use %eax to select a function and look like we support sse2.
2009-04-19 03:11:24 -07:00
Gabe Black
27e54982b4
X86: Fix the mov to segment selector in real mode instruction microcode.
2009-04-19 03:08:40 -07:00
Gabe Black
633c96bd85
X86: The startup IPI delivery mode is not reserved.
2009-04-19 03:01:46 -07:00
Gabe Black
08f021aad0
X86: Implement the STARTUP IPI.
2009-04-19 02:56:03 -07:00
Gabe Black
d277feb925
X86: Implement the INIT IPI.
2009-04-19 02:53:00 -07:00
Gabe Black
a340b214cf
X86: Fix the halt microop.
2009-04-19 02:51:09 -07:00
Gabe Black
641513fe08
X86: Start implementing the interrupt command register in the local APIC.
2009-04-19 02:43:22 -07:00
Gabe Black
9549694ecd
X86: Make code that sends an interrupt from the IO APIC available for IPIs.
2009-04-19 02:42:19 -07:00
Gabe Black
d10195b1a4
CPU: If the simple CPU is already idle, just return from suspendContext, don't assert.
2009-04-19 02:23:29 -07:00
Gabe Black
05b5861419
X86: Condense the startupCPU code.
2009-04-19 02:20:57 -07:00
Gabe Black
f668340f2c
X86: Set the local APIC ID to something meaningful.
2009-04-19 02:16:49 -07:00
Gabe Black
79a3a6aecb
X86: Don't pretend to be an AMD CPU any more. We're not good enough at it.
2009-04-19 02:06:51 -07:00
Korey Sewell
d8a34a9745
mips-tlb-fix: check for alignment faults.\nMIPS was never updated to use TLBS correcty in SE mode. The error was forwarding translations directly to pageTable. The TLB should check for alignment faults at bare minimum here but in the long run we should be using TLBs in SE mode for MIPS.
2009-04-18 10:42:29 -04:00
Korey Sewell
e501e1af54
mips-syscall: mark with correct flag. \nMIPS was using wrong serialization flag on syscall instructions allowing O3 to handle SE mode syscalls incorrectly and speculate on instructions after a syscall
2009-04-18 10:42:29 -04:00
Korey Sewell
5c1742b822
o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode stage was not setting the predicted PC correctly or passing that information back to fetch correctly
2009-04-18 10:42:29 -04:00
Korey Sewell
cc9e834e93
mips-shadowsets: fix calcuations. \n Remove Shadowsets from Int & Arch. Reg Calculations
2009-04-18 10:42:28 -04:00
Steve Reinhardt
14808ecac9
o3, inorder: fix FS bug due to initializing ThreadState to Halted.
...
For some reason o3 FS init() only called initCPU if the thread state
was Suspended, which was no longer the case. There's no apparent
reason to check, so I whacked the test completely rather than
changing the check to Halted.
The inorder init() was also updated to be symmetric, though the
previous code was just a fancy no-op.
2009-04-17 16:54:58 -07:00
Steve Reinhardt
b146131d18
o3: handle fetch with no active threads correctly.
...
This situation can arise now on the first fetch cycle after
the last active thread is halted. It seems easy enough to
deal with when it happens rather than trying to avoid it.
2009-04-15 23:12:00 -07:00
Steve Reinhardt
bb974d5a47
o3: fix {read,set}ArchFloatReg* functions.
...
Register indices were not being calculated properly.
2009-04-15 23:10:43 -07:00
Steve Reinhardt
7617dcf736
ThreadState: initialize status to Halted in constructor.
...
This provides a common initial status for all threads independent
of CPU model (unlike the prior situation where CPUs initialized
threads to inconsistent states).
This mostly matters for SE mode; in FS mode, ISA-specific startupCPU()
methods generally handle boot-time initialization of thread contexts
(since the right thing to do is ISA-dependent).
2009-04-15 13:18:24 -07:00
Steve Reinhardt
8882dc1283
Get rid of the Unallocated thread context state.
...
Basically merge it in with Halted.
Also had to get rid of a few other functions that
called ThreadContext::deallocate(), including:
- InOrderCPU's setThreadRescheduleCondition.
- ThreadContext::exit(). This function was there to avoid terminating
simulation when one thread out of a multi-thread workload exits, but we
need to find a better (non-cpu-centric) way.
2009-04-15 13:13:47 -07:00
Gabe Black
5c79191603
X86: Fix minor bug in the page table walker from TLB shuffling.
2009-04-13 04:14:15 -07:00
Nathan Binkert
c87c9950df
stats: disallow duplicate statistic names.
2009-04-08 22:22:50 -07:00
Nathan Binkert
18a30524d6
alpha: get rid of all turbolaser remnants
2009-04-08 22:22:49 -07:00
Nathan Binkert
e0de2c3443
tlb: More fixing of unified TLB
2009-04-08 22:21:27 -07:00
Gabe Black
7b5a96f06b
tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
2009-04-08 22:21:27 -07:00
Gabe Black
d080581db1
Merge ARM into the head. ARM will compile but may not actually work.
2009-04-06 10:19:36 -07:00
Stephen Hines
7a7c4c5fca
arm: add ARM support to M5
2009-04-05 18:53:15 -07:00
Ali Saidi
639cb0a42d
CPA: Fix a typo that managed to sneak in.
2009-03-25 20:06:54 -04:00
Nathan Binkert
4eea8acaf2
stats: fix compiler error
2009-03-16 15:16:58 -07:00
Steve Reinhardt
758bfe4eb5
cache: set dirty bit on swaps (oops!)
2009-03-11 23:05:26 -07:00
Steve Reinhardt
61ff48a1f8
cpu: fix minor endian issue with trace output
...
(no functional change)
2009-03-11 23:05:24 -07:00
Steve Reinhardt
a94c68228a
prefetch: don't panic on requests w/o contextID (e.g., writebacks).
2009-03-10 17:37:15 -07:00
Nathan Binkert
ac64586a99
build: fix compiler warnings in g++ 3.4
2009-03-07 21:34:50 -08:00
Steve Reinhardt
4f1855484c
Fix up regression execution to better handle tests that end abnormally.
...
E.g., mark aborts due to assertion failures as failed tests,
but those that get killed by the user as needing to be rerun, etc.
2009-03-07 16:58:51 -08:00
Nathan Binkert
ac7bda0212
stats: fix duplicate statistics names.
...
This generally requires providing a more meaningful name() function for a
class.
2009-03-07 14:30:54 -08:00
Nathan Binkert
fcaf1b74b0
stats: cleanup text output stuff and fix mysql output
2009-03-07 14:30:53 -08:00
Nathan Binkert
66a85b54e2
build: fix errors for compilers other than g++ 4.3
2009-03-07 14:30:52 -08:00
Nathan Binkert
6f787e3d36
stats: create an enable phase, and a prepare phase.
...
Enable more or less takes the place of check, but also allows stats to
do some other configuration. Prepare moves all of the code that readies
a stat for dumping into a separate function in preparation for supporting
serialization of certain pieces of statistics data.
While we're at it, clean up the visitor code and some of the python code.
2009-03-05 19:09:53 -08:00
Nathan Binkert
9f45fbaaa6
stats: clean up how templates are used on the data side.
...
This basically works by taking advantage of the curiously recurring template
pattern in an intelligent way so as to reduce the number of lines of code
and hopefully make things a little bit clearer.
2009-03-05 19:09:53 -08:00
Nathan Binkert
cc95b57390
stats: Fix all stats usages to deal with template fixes
2009-03-05 19:09:53 -08:00
Nathan Binkert
c7e82f965f
stats: remove the template wart left over from the ancient binning stuff
2009-03-05 19:09:53 -08:00
Nathan Binkert
244c2a517a
stats: stick the distribution's fancy parameter into the parameters structure.
2009-03-05 19:09:53 -08:00
Nathan Binkert
e19fd1d521
stats: Add a wrapper class for the information side of things.
...
This provides an easy way to provide the callbacks into the data side
of things from the info side of things. Rename Wrap to DataWrap so it
is more easily distinguishable from InfoWrap
2009-03-05 19:09:53 -08:00
Nathan Binkert
c7bd1ec261
stats: better naming of template parameters for the wrapper stuff
...
Parent and Child are bad names. Derived and Base are better.
2009-03-05 19:09:53 -08:00
Nathan Binkert
2dd5a5b3dc
stats: get rid of meaningless uses of virtual
2009-03-05 19:09:53 -08:00
Nathan Binkert
ec209953e7
stats: miscellaneous cleanup
2009-03-05 19:09:53 -08:00
Nathan Binkert
a767819d56
serialize: Allow floats and doubles to be serialized
2009-03-05 19:09:53 -08:00
Steve Reinhardt
e3d6e8882e
Get rid of 'using namespace' declarations in headers.
2009-03-05 17:15:31 -08:00
Korey Sewell
9e1dc7f205
InOrderCPU: Clean up Constructors to initialize variables correctly (i.e. in a way for the compiler to play *nice*)
2009-03-04 22:37:45 -05:00
Korey Sewell
7c8d544216
Give each resource in InOrder it's own TraceFlag instead of just standard 'Resource' flag
2009-03-04 13:17:09 -05:00
Korey Sewell
30cd2d21fa
Remove unused functions/comments cluttering up the code.
2009-03-04 13:17:08 -05:00
Korey Sewell
f69b018571
make handling of interstage buffers (i.e. StageQueues) more consistent: (1)number from 0-n, not 1-n+1, (2) always check nextStageValid before a stageNum+1 and prevStageValid for a stageNum-1 reference (3) add skidSize() to get StageQueue size for all threads
2009-03-04 13:17:07 -05:00
Korey Sewell
f98e9161a8
InOrder didnt have all it's params set to a default value, which is now required for M5 objects; Also, a # of values need to be reset to 0 (or the appropriate value) before we assume they are OK for use.
2009-03-04 13:17:05 -05:00
Korey Sewell
846f953c2b
Give TimeBuffer an ID that can be set. Necessary because InOrder uses generic stages so w/o an ID there is no way to differentiate buffers when debugging
2009-03-04 13:16:49 -05:00
Korey Sewell
e4aa4ca40c
use numCycles instead of simTicks to determine CPI stat in InOrder
2009-03-04 13:16:48 -05:00
Steve Reinhardt
9ee8e685a4
O3: Make numThreads error message more helpful.
2009-03-04 09:25:53 -05:00
Steve Reinhardt
307905095c
Fix Num_Syscall_Descs check bug in non-x86 ISAs.
...
(See cset d35d2b28df38 for x86 fix.)
2009-02-28 20:14:22 -05:00
Nathan Binkert
4523741c1c
quell gcc 4.3 warning
2009-02-27 17:29:58 -08:00
Gabe Black
b69a9ad45a
X86: Install the exit system call.
2009-02-27 09:26:41 -08:00
Gabe Black
9265b3d598
X86: Install the 32 bit write system call.
2009-02-27 09:26:32 -08:00
Gabe Black
b36f28472d
X86: Implement shrd.
2009-02-27 09:26:26 -08:00
Gabe Black
2fe87e62ba
X86: Add a structure to allow mapping between the host and guest fstat formats.
2009-02-27 09:26:17 -08:00
Gabe Black
27b751ec46
X86: Don't treat the REX prefixes as prefixes in 32 bit modes. These are inc/dec instructions.
2009-02-27 09:26:09 -08:00
Gabe Black
aa51c01d69
X86: Set address size to 64 bits when generating addresses internally.
2009-02-27 09:26:01 -08:00
Gabe Black
db3c51d3a0
X86: Add a vsyscall page for 32 bit processes to use.
2009-02-27 09:25:51 -08:00
Gabe Black
c3d7d7ed0e
X86: Implement sysenter as a system call interface.
2009-02-27 09:25:43 -08:00
Gabe Black
5c1cc99d48
X86: Add a 32 bit mmap2 system call.
2009-02-27 09:25:33 -08:00
Gabe Black
04dbed79f8
X86: Install a 32 bit fstat64 system call.
2009-02-27 09:25:26 -08:00
Gabe Black
8a1eb7e8be
X86: Take address size into account when computing an effective address.
2009-02-27 09:25:16 -08:00
Gabe Black
1d18eb9043
X86: Make instructions that use intseg preserve all 8 bytes of their addresses.
2009-02-27 09:25:02 -08:00
Gabe Black
79bc1b3740
X86: Fix a decoder bug and add in some missing instructions.
2009-02-27 09:24:10 -08:00
Gabe Black
3dfa564e70
X86: Respect segment override prefixes even when there's no ModRM byte.
2009-02-27 09:23:58 -08:00
Gabe Black
9dfa3f7f73
X86: Fix segment limit checks.
2009-02-27 09:23:50 -08:00
Gabe Black
9491debaa6
X86: Implement the 32 bit set_thread_area system call.
2009-02-27 09:23:42 -08:00
Gabe Black
1786f20058
X86: Set an initial value for the LDT selector.
2009-02-27 09:23:27 -08:00
Gabe Black
e23d688d8f
X86: Set up a space for a GDT in SE so we can set up TLS or LDT segments.
2009-02-27 09:23:17 -08:00
Gabe Black
281ef8111a
X86: Compute shift instruction flags correctly.
2009-02-27 09:23:00 -08:00
Gabe Black
14fc06640e
X86: Install some 32 bit system calls.
2009-02-27 09:22:50 -08:00
Gabe Black
6ca53f8675
X86: Handle 32 bit system call arguments.
2009-02-27 09:22:30 -08:00
Gabe Black
9a000c5173
Processes: Make getting and setting system call arguments part of a process object.
2009-02-27 09:22:14 -08:00
Gabe Black
60aab03e85
X86: Implement the int system call interface in the decoder.
2009-02-27 09:21:58 -08:00
Gabe Black
05de9f4e2c
X86: Distinguish the width of values on the stack between 32 and 64 bit processes.
2009-02-27 09:21:36 -08:00
Gabe Black
932f6440a1
X86: Add a class to support 32 bit x86 linux process.
2009-02-27 09:21:14 -08:00
Ali Saidi
bebbc9dc89
CPA: Add annotations to IGbE and CopyEngine device models.
2009-02-26 19:29:17 -05:00
Ali Saidi
d447ccb2c6
CPA: Add code to automatically record function symbols as CPU executes.
2009-02-26 19:29:17 -05:00
Ali Saidi
6fd4bc34a1
CPA: Add new object for gathering critical path annotations.
2009-02-26 19:29:17 -05:00
Ali Saidi
894925f135
Trace: fix the --trace-start option
2009-02-26 19:29:16 -05:00
Gabe Black
4a64493158
Devices: Make the RTC device reflect the use of BCD in its status registers.
2009-02-25 10:22:49 -08:00
Gabe Black
7400769768
X86: Implement IST stack switching.
2009-02-25 10:22:43 -08:00
Gabe Black
5c546e3504
CPU: Only look up the nearest symbol in the kernel if you're actually in kernel code.
2009-02-25 10:22:36 -08:00
Gabe Black
437b02884d
ISA: Get rid of the get*RegName functions.
2009-02-25 10:22:31 -08:00
Gabe Black
3b01535ec1
SPARC: Get rid of the state keeping track of register frames.
2009-02-25 10:22:25 -08:00
Gabe Black
4633677145
ISA: Set up common trace flags for tracing registers.
2009-02-25 10:22:17 -08:00
Gabe Black
44d5351071
ISA: Get rid of FlattenIntIndex function.
2009-02-25 10:22:09 -08:00
Gabe Black
c1c61d52a0
SPARC: Get rid of flattenIndex in the int register file.
2009-02-25 10:21:59 -08:00
Gabe Black
ce2e50a64c
ISA: Use the "Stack" traceflag for DPRINTFs about the initial stack frame.
2009-02-25 10:21:52 -08:00
Gabe Black
9d5b6e377f
SPARC: Get rid of the setGlobals function.
2009-02-25 10:21:46 -08:00
Gabe Black
f41ce6b5e9
SPARC: Get rid of the setCWP function.
2009-02-25 10:21:40 -08:00
Gabe Black
88ee7d4c32
SPARC: Add a traceflag for register windows.
2009-02-25 10:21:33 -08:00
Gabe Black
7aa875f4f3
X86: Implement the lldt instruction.
2009-02-25 10:21:27 -08:00
Gabe Black
bda7077c64
X86: Add segmentation checks for ldt related descriptors and selectors.
2009-02-25 10:21:21 -08:00
Gabe Black
e08d60389d
X86: Make the TSS type check actually return a fault if it fails.
2009-02-25 10:21:14 -08:00
Gabe Black
68300cfb8c
X86: Make rdcr use merge and the mov to control register instructions use the right operand size.
2009-02-25 10:21:08 -08:00
Gabe Black
9842f1ca9d
X86: Implement CLTS.
2009-02-25 10:21:02 -08:00
Gabe Black
b035c917a5
X86: Make the segment register reading microops use merge.
2009-02-25 10:20:47 -08:00
Gabe Black
28efb3c6e3
X86: Implement the mov to debug register intructions.
2009-02-25 10:20:42 -08:00
Gabe Black
c39ed53d05
X86: Rename oszForPseudoDesc maxOsz to reflect its more general use.
2009-02-25 10:20:30 -08:00
Gabe Black
3ca2451d81
X86: Add code to interpret debug register values.
2009-02-25 10:20:25 -08:00
Gabe Black
1e70401c08
X86: Fix a few bugs with the segment register instructions in real mode.
...
Fix a few instances where the register form of zext was used where zexti was
intended. Also get rid of the 64 bit only rip relative addressed version since
64 bit and real mode are mutually exclusive.
2009-02-25 10:20:19 -08:00
Gabe Black
8813168b5a
X86: Do a merge for the zero extension microop.
2009-02-25 10:20:10 -08:00
Gabe Black
28a35a6adb
X86: Add microops for reading/writing debug registers.
2009-02-25 10:20:01 -08:00
Gabe Black
11fbed02ea
X86: Add classes that break out the bits of the DR6 and DR7 registers.
2009-02-25 10:19:54 -08:00
Gabe Black
cb4141f6e6
X86: Check src1 for illegal values since that's the index we actually use.
2009-02-25 10:19:47 -08:00
Gabe Black
d48214a656
X86: Implement the fence instructions. These are not microcoded.
2009-02-25 10:19:41 -08:00
Gabe Black
9940e21fa9
CPU: Add a flag to identify a read barrier to the static inst class.
2009-02-25 10:19:33 -08:00
Gabe Black
06ff83e1b9
X86: Implement a basic prefetch instruction.
2009-02-25 10:19:22 -08:00
Gabe Black
5f0428ef9f
X86: Use the right portion of a register for stores.
2009-02-25 10:19:14 -08:00
Gabe Black
c849ef58c0
X86: Actually check page protections.
2009-02-25 10:18:58 -08:00
Gabe Black
f35a37ca9e
X86: Update CS later so stack accesses have the right permission checks.
2009-02-25 10:18:51 -08:00
Gabe Black
da61c4b3ee
CPU: Don't fetch when executing a macroop.
...
If the CPL changes mid macroop, the end of the instruction might not be
priveleged enough to execute the beginning.
2009-02-25 10:18:36 -08:00
Gabe Black
ba69184630
X86: Use atCPL0 for accesses that are part of CPU machinery.
2009-02-25 10:18:29 -08:00
Gabe Black
dc53ca89f6
X86: Add a flag to force memory accesses to happen at CPL 0.
2009-02-25 10:18:22 -08:00
Gabe Black
897c374892
X86: Move where CS is set so CPL checks work out.
2009-02-25 10:18:16 -08:00
Gabe Black
710b43dfbd
X86: Implement inUserMode for x86.
2009-02-25 10:18:06 -08:00
Gabe Black
1cedc748d4
X86: Add a trace flag for tracing faults.
2009-02-25 10:17:59 -08:00
Gabe Black
eec3f49a57
X86: Implement the sysret instruction in long mode.
2009-02-25 10:17:54 -08:00
Gabe Black
6325245e3e
X86: Implement the longmode versions of the syscall instruction.
2009-02-25 10:17:49 -08:00
Gabe Black
dadc30b0a4
X86: Make the microcode assembler recognize r8-r15.
2009-02-25 10:17:43 -08:00
Gabe Black
fcad6e3b13
X86: Add a wrattr microop.
2009-02-25 10:17:38 -08:00
Gabe Black
e4ede69b2f
X86: Add a trace flag for the page table walker.
2009-02-25 10:17:27 -08:00
Gabe Black
99aa121fca
X86: Make exceptions handle stack switching.
2009-02-25 10:17:19 -08:00
Gabe Black
aa7bc1be74
X86: Implement the LTR instruction.
2009-02-25 10:17:14 -08:00
Gabe Black
08f3a126d5
X86: Fix segment limit checking.
2009-02-25 10:17:08 -08:00
Gabe Black
2f31643db5
X86: Add a check to chks to verify a task state segment descriptor.
2009-02-25 10:17:02 -08:00
Gabe Black
7b1cb74ac3
X86: Add a check to chks which raises #GP(selector) if selector is NULL or not in the GDT.
2009-02-25 10:16:54 -08:00
Gabe Black
82288e7c3e
X86: Add makeAtomicResponse to the read/write functions of x86 devices.
2009-02-25 10:16:43 -08:00
Gabe Black
7462cb0842
X86: Fix the timing mode of the page table walker.
2009-02-25 10:16:34 -08:00
Gabe Black
40fdba2454
X86: Make the X86 TLB take advantage of delayed translations, and get rid of the fake TLB miss faults.
2009-02-25 10:16:21 -08:00
Gabe Black
6ed47e9464
CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it.
2009-02-25 10:16:15 -08:00
Gabe Black
15940d06b5
SPARC: Adjust a few instructions to not write registers in initiateAcc.
2009-02-25 10:16:04 -08:00
Gabe Black
1b336a8fe7
X86: Make the stupd microop not update registers in initiateAcc.
2009-02-25 10:15:56 -08:00
Gabe Black
5605079b1f
ISA: Replace the translate functions in the TLBs with translateAtomic.
2009-02-25 10:15:44 -08:00
Gabe Black
a1aba01a02
CPU: Get rid of translate... functions from various interface classes.
2009-02-25 10:15:34 -08:00
Nathan Binkert
f3090e5b70
stats: reorganize how parameters are stored and accessed.
2009-02-23 12:22:19 -08:00
Nathan Binkert
aaf98aaa32
stats: move the limits stuff into the types.hh file
2009-02-23 12:22:18 -08:00
Nathan Binkert
80d5f34da6
stats: get rid of the convoluted 'database' code.
...
Just use the stuff directly and things ought to be more clear
2009-02-23 12:22:17 -08:00
Nathan Binkert
fb74987c52
stats: Try to make the names of things more intuitive.
...
Basically, this means renaming several things called data to info, which
is information about the statistics. Things that are named data now are
actual data stored for the statistic.
2009-02-23 12:22:15 -08:00
Nathan Binkert
bcb7e70178
stats: clean up the statistics unittest
2009-02-23 12:04:52 -08:00
Nathan Binkert
d940a2b741
stats: fix text printout for distributions
2009-02-23 12:04:50 -08:00
Nathan Binkert
f69ea20fc6
stats: cleanup static stats to make startup work.
...
This is mainly to allow the unit test to run without requiring the standard
M5 stats from being initialized (e.g. sim_seconds, sim_ticks, host_seconds)
2009-02-23 12:03:06 -08:00
Nathan Binkert
3fa9812e1d
debug: Move debug_break into src/base
2009-02-23 11:48:40 -08:00
Gabe Black
e8c1c3e72e
X86: Pass whether an access was a read/write/fetch so faults can behave accordingly.
2009-02-23 00:20:34 -08:00
Korey Sewell
6c5afe6346
Remove unnecessary building of FreeList/RenameMap in InOrder. Clean-up comments and O3 extensions InOrder Thread Context
2009-02-20 11:02:48 -05:00
Nathan Binkert
c41c9cf3a6
events: Make trace events happen at the right priority.
...
Also, while we're at it, remember that priorities are in the Event class
and add a disable method to disable tracing.
2009-02-18 10:00:15 -08:00
Steve Reinhardt
6cfff91d43
Make etherdump timestamps zero-based.
...
We previously used the actual wall time for the base timestamps,
making etherdumps non-deterministic. This fixes that problem and
gets rid of the "malformed packet" at the front that we needed to
provide the right base timestamp to wireshark/tcpdump.
2009-02-17 19:24:46 -08:00
Lisa Hsu
5d029ff11e
sycalls: implement mremap() and add DATA flag for getrlimit(). mremap has been tested on Alpha, compiles for the rest but not tested. I don't see why it wouldn't work though.
2009-02-16 17:47:39 -05:00
Steve Reinhardt
89a7fb0393
Fixes to get prefetching working again.
...
Apparently we broke it with the cache rewrite and never noticed.
Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part
of these changes (and for inspiring me to work on the rest).
Some other overdue cleanup on the prefetch code too.
2009-02-16 08:56:40 -08:00
Gabe Black
6923282fb5
X86: Make the loader recognize 32 bit x86 processes.
2009-02-15 23:43:39 -08:00
Nathan Binkert
e0f425bb94
traceflags: fix --trace-help
2009-02-15 20:39:12 -08:00
Nathan Binkert
f255957b90
style
2009-02-10 22:19:27 -08:00
Korey Sewell
cf4a00ca41
Configs: Add support for the InOrder CPU model
2009-02-10 15:49:29 -08:00
Korey Sewell
973d8b8b13
InOrder: Import new inorder CPU model from MIPS.
...
This model currently only works in MIPS_SE mode, so it will take some effort
to clean it up and make it generally useful. Hopefully people are willing to
help make that happen!
2009-02-10 15:49:29 -08:00
Korey Sewell
36d9065f5f
syscall: Expose ioctl for MIPS
2009-02-10 15:49:29 -08:00
Korey Sewell
34a5cd8870
ExeTrace: Allow subclasses of the tracer to define their own prefix to dump
2009-02-10 15:49:29 -08:00
Korey Sewell
2d0a66cbc1
CPU: Prepare CPU models for the new in-order CPU model.
...
Some new functions and forward declarations are necessary to make things work
2009-02-10 15:49:29 -08:00
Nathan Binkert
20c5ec6e1c
copyright: This file need not have had the more restrictive copyright.
2009-02-09 20:10:15 -08:00
Nathan Binkert
dd6ea8797f
scons: Require SCons version 0.98.1
...
This allows me to clean things up so we are up to date with respect to
deprecated features. There are many features scheduled for permanent failure
in scons 2.0 and 0.98.1 provides the most compatability for that. It
also paves the way for some nice new features that I will add soon
2009-02-09 20:10:14 -08:00
Nathan Binkert
9e268ae63f
scons: Don't build the intermediate static library unless explicitly requested.
...
This means that similar to libm5_fast.so, you need to explicitly build
build/ALPHA_SE/libm5_fast.a if you want it.
2009-02-09 20:10:12 -08:00
Nathan Binkert
e1798d063e
Quell g++ 4.3 warning about operator ambiguity
2009-02-06 20:55:50 -08:00
Nathan Binkert
64eb0dc9cd
some new files are missing copyright notices
2009-02-04 16:26:15 -08:00
Gabe Black
73f579a804
X86: Add some missing default arguments.
2009-02-01 22:40:51 -08:00
Gabe Black
5a4eed5d34
X86: All x86 fault classes now attempt to do something useful.
2009-02-01 17:09:08 -08:00
Gabe Black
923a14dde7
X86: Make the fault classes handle error codes better.
2009-02-01 17:08:32 -08:00
Gabe Black
2f8cec849d
X86: Make the long mode interrupt/exception microcode handle an error code.
2009-02-01 17:07:43 -08:00
Gabe Black
9b4d1e0f9a
X86: Distinguish between hardware and software interrupts/exceptions
2009-02-01 17:07:18 -08:00
Gabe Black
041402a949
X86: Fix the upper bound on some ranges that were setting up the micro code assembler.
2009-02-01 17:06:25 -08:00
Gabe Black
6b53b8387e
X86: Make the chks microop check for the right int descriptor type.
2009-02-01 17:05:37 -08:00
Gabe Black
c0cd58812e
X86: Touch up the interrupt entering microcode.
2009-02-01 17:04:21 -08:00
Gabe Black
03a00735c2
X86: Keep track of the vector for all exceptions/faults.
2009-02-01 17:03:11 -08:00
Gabe Black
7b58511470
CPU: Don't always reset the micro pc on faults. Let the faults handle it.
2009-02-01 00:30:54 -08:00
Gabe Black
6b60a29706
X86: Fix the time keeping of the Local APIC timer.
2009-02-01 00:30:11 -08:00
Gabe Black
ca6e0d75c8
X86: Fix the microcode for the LODS instruction.
2009-02-01 00:28:28 -08:00
Gabe Black
57be1dfe48
X86: Implement pciToDma.
2009-02-01 00:27:15 -08:00
Gabe Black
70cd5bfce5
X86: Configure the first PCI interrupt.
2009-02-01 00:26:10 -08:00
Gabe Black
f1b43b39a7
X86: Hook up the IDE controller interrupt line.
2009-02-01 00:25:15 -08:00
Gabe Black
d432bd13b2
X86: Fix some incorrect register widths.
2009-02-01 00:18:13 -08:00
Gabe Black
f3b8371dfc
X86: Add extended Intel MP entries correctly.
2009-02-01 00:15:38 -08:00
Gabe Black
06cdbe5ea7
X86: Compute PCI config addresses correctly.
2009-02-01 00:11:49 -08:00
Gabe Black
483c3e96b7
X86: Calculate flags based on the actual result.
2009-02-01 00:08:16 -08:00
Gabe Black
7720968949
X86: Make sure the predecoder is cleared out for interrupts.
2009-02-01 00:04:34 -08:00
Gabe Black
3ecc38cb8b
Devices: Add support for legacy fixed IO locations in BARs.
2009-02-01 00:02:21 -08:00
Gabe Black
bb7ad80bbe
X86: Plug in an IDE controller.
2009-02-01 00:00:03 -08:00
Gabe Black
c2c5740b98
X86: Refactor and clean up the keyboard controller.
2009-01-31 23:59:25 -08:00
Gabe Black
7cf276bed3
X86: Add a keyboard controller device.
2009-01-31 23:59:01 -08:00
Gabe Black
0287f19ede
X86: Set up the console interrupt and add some DPRINTFs.
2009-01-31 23:56:46 -08:00
Gabe Black
e1c412cec6
X86: Configure the IO APIC more.
2009-01-31 23:44:05 -08:00
Gabe Black
6a3f255a84
X86: Rework interrupt pins to allow one to many connections.
2009-01-31 23:33:54 -08:00
Gabe Black
64b663c607
X86: Initialize the value behind port 61 so unused bits are consistent.
2009-01-31 23:26:43 -08:00
Gabe Black
953e4bba59
X86: Set/correct some default values for x86 parameters.
2009-02-01 16:59:34 -08:00
Ali Saidi
be5d350afc
SCons: Fix how we get Mercurial revision information since internals keep changing.
2009-01-30 20:04:57 -05:00
Ali Saidi
e7293dd24e
Errors: Use the correct panic/warn/fatal/info message in some places.
2009-01-30 20:04:17 -05:00
Ali Saidi
f4291aac25
Errors: Print a URL with a hash of the format string to find more information about an error.
2009-01-30 20:04:15 -05:00
Ali Saidi
35a85a4e86
Config: Cause a fatal() when a parameter without a default value isn't set(FS #315 ).
2009-01-30 19:08:13 -05:00
Nathan Binkert
0b228fc1ab
Fix typo
2009-01-29 22:27:11 -08:00
Gabe Black
56e182a6a9
X86: Add a dummy minimal DMA controller that doesn't do anything.
2009-01-25 20:35:00 -08:00
Gabe Black
151bc018dd
X86: Add a device to back the non-existant floppy drive controller.
2009-01-25 20:34:17 -08:00
Gabe Black
dbe28da1be
X86: Add fake devices for non-existant serial ports.
2009-01-25 20:33:52 -08:00
Gabe Black
52defeb4e7
X86: Implement the xadd instruction.
2009-01-25 20:33:27 -08:00
Gabe Black
3c5988b86c
X86: Implement the bswap instruction.
2009-01-25 20:32:43 -08:00
Gabe Black
919c3e7fb6
Dev: Make the RTC device ignore writes to a read only bit.
2009-01-25 20:32:26 -08:00
Gabe Black
0449fb2b7a
X86: Fix a bug in the iret microcode.
2009-01-25 20:31:17 -08:00
Gabe Black
389fbfdab1
X86: Make the interrupt object wake up the CPU when something becomes pending.
2009-01-25 20:30:51 -08:00
Gabe Black
d9794784ba
CPU: Add a setCPU function to the interrupt objects.
2009-01-25 20:29:03 -08:00
Gabe Black
3f9e2350a1
Devices: Make the destructor virtual on the CopyEnginChannel object.
...
This fixes a compile warning which becomes an error.
2009-01-25 20:26:53 -08:00
Nathan Binkert
64ed39f61b
pseudo inst: Add new wake cpu instruction for sending a message to wake a cpu.
...
It's instantaneous and so it's somewhat bogus, but it's a first step.
2009-01-24 07:27:22 -08:00
Nathan Binkert
f0fb3ac060
cpu: provide a wakeup mechanism that can be used to pull CPUs out of sleep.
...
Make interrupts use the new wakeup method, and pull all of the interrupt
stuff into the cpu base class so that only the wakeup code needs to be updated.
I tried to make wakeup, wakeCPU, and the various other mechanisms for waking
and sleeping a little more sane, but I couldn't understand why the statistics
were changing the way they were. Maybe we'll try again some day.
2009-01-24 07:27:21 -08:00
Ali Saidi
56d5212ba7
Trace: Add DPRINTFS macro that takes parameter to call name() for trace printing.
2009-01-23 17:19:48 -05:00
Ali Saidi
37ffe52ca4
IGbE: Fix two e1000 driver bugs that I missed before.
2009-01-23 17:19:47 -05:00
Nathan Binkert
10fc45da27
o3cpu: give a name to the activity recorder for better tracing
2009-01-21 14:56:18 -08:00
Nathan Binkert
dbac448b08
thread_context: move getSystemPtr so SE mode can get to it.
...
There was really no reason that it should be FS only.
2009-01-19 20:36:49 -08:00
Nathan Binkert
81b8c0c79a
python: add fatal() function to the m5 package and use it
2009-01-19 14:43:09 -08:00
Nathan Binkert
da14789c32
python: Try to isolate the stuff that's in the m5.internal package a bit more.
2009-01-19 09:59:15 -08:00
Nathan Binkert
c9d3113015
tracing: Add help strings for some of the trace flags
2009-01-19 09:59:14 -08:00
Nathan Binkert
0876c822dd
tracing: panic() if people try to use tracing, but TRACING_ON is not set.
...
Also clean things up so that help strings can more easily be added.
Move the help function into trace.py
2009-01-19 09:59:13 -08:00
Nathan Binkert
f15f252d4e
python: Rework how things are imported
2009-01-19 09:59:13 -08:00
Nathan Binkert
51d780fa4d
scons: Don't add all objects to the library twice
2009-01-19 09:03:41 -08:00
Ali Saidi
b4227bd7f6
Fix issue 326: glibc non-deterministic because it reads /proc
2009-01-17 18:56:46 -05:00
Ali Saidi
140b4b891e
CopyEngine: Implement a I/OAT-like copy engine.
2009-01-17 18:55:09 -05:00
Nathan Binkert
8153790d00
SCons: centralize the Dir() workaround for newer versions of scons.
...
Scons bug id: 2006 M5 Bug id: 308
2009-01-13 14:17:50 -08:00
Richard Strong
81180a3bf0
This fix addresses an ill formed if statement that fails
...
to compile. The fix was the simple addition of another set
of parenthesis to ensure the correct condition resolution.
2009-01-11 22:45:03 -08:00
Steve Reinhardt
c370a9cb98
FastAlloc: track allocation tick in debug mode,
...
minor enhancements to debug output
2009-01-08 14:13:33 -08:00
Gabe Black
b23633ad1b
X86: Hook in the M5 pseudo insts.
2009-01-06 23:55:46 -08:00
Gabe Black
115b1a7ed3
X86: Autogenerate macroop generateDisassemble function.
2009-01-06 22:55:27 -08:00
Gabe Black
8cab1805f9
X86: Move the function that prints memory args into the inst base class.
2009-01-06 22:46:28 -08:00
Gabe Black
9e24d8c599
X86: Move the macroop class out of the isa description into C++.
2009-01-06 22:44:59 -08:00
Gabe Black
7b7a72158a
X86: Change indentation on microop disassembly.
2009-01-06 22:40:41 -08:00
Gabe Black
b0ab5c894d
Tracing: Make tracing aware of macro and micro ops.
2009-01-06 22:34:18 -08:00
Ali Saidi
2adc60795b
IGbE: Implement header splitting with large MTU
2009-01-06 10:36:57 -05:00
Ali Saidi
11ac0c7acf
INET: Add functions to header types to get offset in packet and start of payload; add function to split packet at last known header
2009-01-06 10:36:56 -05:00
Ali Saidi
9f89d43b65
IGbE: Remove is8257 variable
2009-01-06 10:36:55 -05:00
Steve Reinhardt
1704ba2273
Make Alpha pseudo-insts available from SE mode.
2008-12-17 09:51:18 -08:00
Gabe Black
02cd18f536
SPARC: Truncate syscall args and return values appropriately.
2008-12-16 23:06:37 -08:00
Gabe Black
f0d1a20971
PCI: Add some missing breaks to a couple case statements.
2008-12-15 00:47:01 -08:00
Author Name
13f7fdcf67
The ide_ctrl serialize and unserialize were broken.
...
Multiple channels were saving their state under the
same name. This patch separates the saved state of
the primary and secondary channel.
2008-12-14 23:29:49 -08:00
Richard Strong
dae531c049
IDE: Fix serialization for the IDE controller.
2008-12-09 10:34:08 -08:00
Nathan Binkert
d0c0c25ebc
eventq: Add some debugging code to the eventq.
2008-12-08 07:17:48 -08:00
Nathan Binkert
19273164da
output: Change default output directory and files and update tests.
...
--HG--
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stderr => tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stdout => tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stderr => tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stdout => tests/long/00.gzip/ref/sparc/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stderr => tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stdout => tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stderr => tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stdout => tests/long/00.gzip/ref/sparc/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr => tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout => tests/long/00.gzip/ref/x86/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stderr => tests/long/00.gzip/ref/x86/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stdout => tests/long/00.gzip/ref/x86/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/m5stats.txt => tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stderr => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stdout => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/m5stats.txt => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stderr => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stdout => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/m5stats.txt => tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stderr => tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stdout => tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stderr => tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stdout => tests/long/10.mcf/ref/sparc/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr => tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout => tests/long/10.mcf/ref/x86/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stderr => tests/long/10.mcf/ref/x86/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stdout => tests/long/10.mcf/ref/x86/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/m5stats.txt => tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stderr => tests/long/20.parser/ref/x86/linux/simple-atomic/simerr
rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stdout => tests/long/20.parser/ref/x86/linux/simple-atomic/simout
rename : tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/20.parser/ref/x86/linux/simple-timing/stderr => tests/long/20.parser/ref/x86/linux/simple-timing/simerr
rename : tests/long/20.parser/ref/x86/linux/simple-timing/stdout => tests/long/20.parser/ref/x86/linux/simple-timing/simout
rename : tests/long/20.parser/ref/x86/linux/simple-timing/m5stats.txt => tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stderr => tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stdout => tests/long/30.eon/ref/alpha/tru64/o3-timing/simout
rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stderr => tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stdout => tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stderr => tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stdout => tests/long/30.eon/ref/alpha/tru64/simple-timing/simout
rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stderr => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stdout => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout
rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stderr => tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stdout => tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stderr => tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stdout => tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stderr => tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stdout => tests/long/50.vortex/ref/sparc/linux/simple-timing/simout
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout
rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stderr => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stdout => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stderr => tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr
rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stdout => tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout
rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stderr => tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr
rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stdout => tests/long/60.bzip2/ref/x86/linux/simple-timing/simout
rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/m5stats.txt => tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stderr => tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stdout => tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/m5stats.txt => tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stderr => tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stdout => tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stderr => tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout => tests/long/70.twolf/ref/sparc/linux/simple-timing/simout
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt => tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr => tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout => tests/long/70.twolf/ref/x86/linux/simple-atomic/simout
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt => tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/stderr => tests/long/70.twolf/ref/x86/linux/simple-timing/simerr
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/stdout => tests/long/70.twolf/ref/x86/linux/simple-timing/simout
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/m5stats.txt => tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stderr => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stdout => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/m5stats.txt => tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stderr => tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stdout => tests/quick/00.hello/ref/alpha/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stderr => tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stdout => tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stderr => tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout => tests/quick/00.hello/ref/alpha/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stderr => tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stdout => tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stdout => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stderr => tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout => tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt => tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stderr => tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stdout => tests/quick/00.hello/ref/mips/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stderr => tests/quick/00.hello/ref/mips/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stdout => tests/quick/00.hello/ref/mips/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/mips/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stderr => tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stdout => tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stderr => tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stdout => tests/quick/00.hello/ref/sparc/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr => tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout => tests/quick/00.hello/ref/x86/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt => tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stderr => tests/quick/00.hello/ref/x86/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stdout => tests/quick/00.hello/ref/x86/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/x86/linux/simple-timing/m5stats.txt => tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt
rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr
rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt => tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stderr => tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stdout => tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stderr => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stderr => tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stdout => tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/m5stats.txt => tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stderr => tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stdout => tests/quick/20.eio-short/ref/alpha/eio/detailed/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stderr => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stdout => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/m5stats.txt => tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stderr => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stdout => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/m5stats.txt => tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stderr => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stdout => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/m5stats.txt => tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stderr => tests/quick/50.memtest/ref/alpha/linux/memtest/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stdout => tests/quick/50.memtest/ref/alpha/linux/memtest/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt => tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
2008-12-08 07:16:40 -08:00
Gabe Black
9192b7f1ef
Devices: Clean up the IDE controller.
2008-12-07 12:59:48 -08:00
Lisa Hsu
993b7be4bb
imported patch aux-fix.patch
2008-12-07 15:07:42 -05:00
Gabe Black
e4790bcbe2
X86: Add add_entry back in.
2008-12-06 14:48:59 -08:00
Nathan Binkert
489e3e7381
eventq: use the flags data structure
2008-12-06 14:18:18 -08:00
Nathan Binkert
cbbc4501c8
eventq: move virtual function definitiions to the .cc file.
2008-12-06 14:18:18 -08:00
Nathan Binkert
a0d322be40
traceflags: Make "All" a valid trace flag.
2008-12-06 14:18:18 -08:00
Nathan Binkert
e08c6be9fe
SimObject: change naming of vectors so there are the same numbers of digits.
...
i.e. we used to have Foo0, Foo1, ..., Foo10, Foo11, ..., Foo100
now we have Foo000, Foo001, ..., Foo010, Foo011, ..., Foo100
2008-12-06 14:18:18 -08:00
Nathan Binkert
e141cb7441
flags: Change naming of functions to be clearer
2008-12-06 14:18:18 -08:00
Ali Saidi
dd788a23c9
IGbE: Add support for newer 8257x based Intel NICs
2008-12-05 13:58:22 -05:00
Ali Saidi
400e516261
IGbE: Add support for TCP segment offload
2008-12-05 13:58:21 -05:00
Ali Saidi
aab595a306
INet: Allow updating on id, len, seq, and flag field for TCP segment offload
2008-12-05 13:58:21 -05:00
Lisa Hsu
854aa60fdc
Automated merge with ssh://m5sim.org//repo/m5
2008-12-05 12:11:46 -05:00
Lisa Hsu
f1430941cf
This brings M5 closer to modernity - the kernel being advertised is newer so it won't die on binaries compiled with newer glibc's, and enables use of TLS-toolchain built binaries for ALPHA_SE by putting auxiliary vectors on the stack. There are some comments in the code to help. Finally, stats changes for ALPHA are from slight perturbations to the initial stack frame, all minimal diffs.
2008-12-05 12:09:29 -05:00
Lisa Hsu
e2c7618e50
This patch pulls out the auxiliary vector struct from individual ISA
...
LiveProcesses to the base LiveProcess definition so anyone can use them.
2008-12-04 18:03:35 -05:00
Nathan Binkert
74f10be526
cprintf: support a configurable width and precision ("*" in printf)
2008-12-03 04:57:54 -08:00
Steve Reinhardt
041ca19edc
Assume files w/o obvious OS are Linux (with warning)
...
instead of giving a fatal error.
2008-11-20 19:08:46 -08:00
Steve Reinhardt
ce4c9a7c10
Sort trace flags before printing them.
2008-11-17 12:41:50 -08:00
Clint Smullen
3087be945d
Output: Include gzstream package to allow automatically-gzipped output
...
The gzstream package provides an ostream-interface for writing gzipped files.
The package comes from:
http://www.cs.unc.edu/Research/compgeom/gzstream/
And is distributed under the LGPL license. Both the license and version
information has been preservered, though all other files in the package have
been purged. Minor modifications to the code have been made. The output module
detects when a filename ends in .gz and constructs an ogzstream object instead
of an ofstream object. This works for both the create(...) and find(...)
commands. Additionally, since gzstream objects needs to be closed to ensure
proper file termination, I have the output deconstructor deleting all ostream's
that it manages on behalf of find(...). At the moment, the only output file
that I know this functionality works for is stats, i.e. by specifying
"--stats-file=m5stats.txt.gz" on the command line.
2008-11-15 23:42:11 -05:00
Steve Reinhardt
4514f565e3
syscalls: fix latent brk/obreak bug.
...
Bogus calls to ChunkGenerator with negative size were triggering
a new assertion that was added there.
Also did a little renaming and cleanup in the process.
2008-11-15 09:30:10 -08:00
Steve Reinhardt
640b415688
Cache: get rid of obsolete Tag methods.
...
I think readData() and writeData() were used for Erik's compression
work, but that code is gone, these aren't called anymore, and they
don't even really do what their names imply.
2008-11-14 14:14:35 -08:00
Nathan Binkert
5711282f87
Fix a bunch of bugs I introduced when I changed the flags stuff for packets.
...
I did some of the flags and assertions wrong. Thanks to Brad Beckmann
for pointing this out. I should have run the opt regressions instead
of the fast. I also screwed up some of the logical functions in the Flags
class.
2008-11-14 04:55:30 -08:00
Gabe Black
7a4d75bae3
CPU: Refactor read/write in the simple timing CPU.
2008-11-13 23:30:37 -08:00
Nathan Binkert
4d64d7664c
SCons: Allow top level directory of EXTRAS able to contain SConscripts.
...
The current EXTRAS will fail if the top level directory pointed to by EXTRAS
has a SConscript file in it. We allow this by including the directory name
of the EXTRA in the build directory which prevents a clash between
src/SConscript and extra/SConscript. Maintain compatibility with older uses
of EXTRAS by adding a -I for each top level extra directory.
2008-11-10 11:51:18 -08:00
Nathan Binkert
eb5d9ba72b
pseudo inst: Add rpns (read processor nanoseconds) instruction.
...
This instruction basically returns the number of nanoseconds that the CPU
has been running.
2008-11-10 11:51:18 -08:00
Nathan Binkert
c25d966b06
Clean up the SimpleTimingPort class a little bit.
...
Move the constructor into the .cc file and get rid of the typedef for
SendEvent.
2008-11-10 11:51:18 -08:00
Nathan Binkert
ea70a44c9f
clean: Move some stuff from the hh file to the cc file.
2008-11-10 11:51:18 -08:00
Nathan Binkert
4e02e7c217
python: Fix the reference counting for python events placed on the eventq.
...
We need to add a reference when an object is put on the C++ queue, and remove
a reference when the object is removed from the queue. This was not happening
before and caused a memory problem.
2008-11-10 11:51:18 -08:00
Clint Smullen
1adfe5c7f3
O3CPU: Make the instcount debugging stuff per-cpu.
...
This is to prevent the assertion from firing if you have a large multicore.
Also make sure that it's not compiled in when NDEBUG is defined
2008-11-10 11:51:18 -08:00
Nathan Binkert
9c49bc7b00
mem: update stuff for changes to Packet and Request
2008-11-10 11:51:17 -08:00
Nathan Binkert
3535d746ab
style: clean up the Packet stuff
2008-11-10 11:51:17 -08:00
Nathan Binkert
2dd699ed3d
flags: Provide an object for managing boolean flags for an object.
...
In many cases it might be preferable to use bitset, but this object
allows the user more easily manipulate groups of flags because the
underlying type (e.g. uint64_t) is exposed.
2008-11-10 11:51:17 -08:00
Nathan Binkert
194f0310d3
safe_cast: add a new cast function for casts that should always succeed.
...
In DEBUG mode, this does a dynamic_cast and asserts that the result is
non null. Otherwise, it just does a static_cast. Again, this is only
intended for cases where the cast should always succeed and what's
desired is a debugging check to make sure.
2008-11-10 11:51:17 -08:00
Steve Reinhardt
27e8f3c98a
DmaDevice: fix minor type in error message.
2008-11-10 14:45:31 -08:00
Steve Reinhardt
63127cbf37
mem: Assert that requests have non-negative size.
...
Would have saved me much debugging time if these
had been in there previously.
2008-11-10 14:11:07 -08:00
Steve Reinhardt
42bd460d7f
Cache: Refactor packet forwarding a bit.
...
Makes adding write-through operations easier.
2008-11-10 14:10:28 -08:00
Gabe Black
846cb450f9
CPU: Make unaligned accesses work in the timing simple CPU.
2008-11-09 21:56:28 -08:00
Gabe Black
8c15518f30
X86: Fix completeAcc get call.
2008-11-09 21:55:43 -08:00
Gabe Black
909380f3ee
X86: Make the timing simple CPU handle variable length instructions.
2008-11-09 21:55:01 -08:00
Nathan Binkert
44839d6b71
Fix a few more places where the context stuff wasn't changed
2008-11-05 07:20:03 -08:00
Lisa Hsu
46b56bb7b6
Fix SPARC_FS compile
2008-11-05 16:19:17 -05:00
Lisa Hsu
07969dbbf1
Right now a single thread cpu 1 could get assigned context Id != 1, depending
...
on the order in which it's registered with the system. To make them match,
here is a little change.
2008-11-05 15:30:49 -05:00
Lisa Hsu
c68032ddcb
decouple eviction from insertion in the cache.
2008-11-04 11:35:58 -05:00
Lisa Hsu
4ab52cb986
Change the findBlock(addr, lat) to accessBlock, which I think has better connotations for what is really happening and how it should be used.
2008-11-04 11:35:57 -05:00
Lisa Hsu
dd99ff23c6
get rid of all instances of readTid() and getThreadNum(). Unify and eliminate
...
redundancies with threadId() as their replacement.
2008-11-04 11:35:42 -05:00
Lisa Hsu
d857faf073
Add in Context IDs to the simulator. From now on, cpuId is almost never used,
...
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
2008-11-02 21:57:07 -05:00
Lisa Hsu
67fda02dda
Make it so that all thread contexts are registered with the System, even in
...
SE. Process still keeps track of the tc's it owns, but registration occurs
with the System, this eases the way for system-wide context Ids based on
registration.
2008-11-02 21:57:06 -05:00
Lisa Hsu
c55a467a06
make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
...
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
2008-11-02 21:56:57 -05:00
Clint Smullen
95af120e60
CPU: The API change to EventWrapper did not get propagated to the entirety of TimingSimpleCPU.
...
The constructor no-longer schedules an event at construction and the implict conversion between int and bool was allowing the old code to compile without warning.
Signed-off By: Ali Saidi
2008-10-27 18:18:04 -04:00
Clint Smullen
cfa32d8de7
Checkpointing: createCountedDrain function, it was only returning an Event, which does not expose a setCount method to Python.
...
Signed-off By: Ali Saidi
2008-10-27 19:46:01 -04:00
Lisa Hsu
8788d703f8
s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in
...
comments.
2008-10-23 16:49:17 -04:00
Lisa Hsu
546a6c0c1b
probe function no longer used anywhere.
2008-10-23 16:49:13 -04:00
Lisa Hsu
7a28ab2d18
remove the totally obsolete split cache
2008-10-23 16:11:28 -04:00
Nathan Binkert
9836d81c2b
style: Use the correct m5 style for things relating to interrupts.
2008-10-21 07:12:53 -07:00
Ali Saidi
b760b99f4d
O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes
...
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.
Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.
Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
2008-10-20 16:22:59 -04:00
Lisa Hsu
4fac54f227
Automated merge with ssh://daystrom.m5sim.org//z/repo/m5
2008-10-19 22:50:53 -04:00
Nathan Binkert
9b8011e255
need to add packet_access.hh in order to get tempalte definition
2008-10-16 22:22:47 -07:00
Nathan Binkert
81f5da1e89
get rid of local variable that's only used in an assert so fast compiles
2008-10-16 22:22:17 -07:00
Lisa Hsu
101c2d9174
Automated merge with ssh://daystrom.m5sim.org//z/repo/m5
2008-10-16 14:16:26 -04:00
Lisa Hsu
90e40ca982
This function declaration isn't used anywhere.
...
HG: user: Lisa Hsu <hsul@eecs.umich.edu> HG: branch default HG: changed
src/mem/cache/cache.hh
2008-10-14 17:22:03 -04:00
Nathan Binkert
5b07448cf1
eventq: make python events actually work
2008-10-14 09:34:11 -07:00
Nathan Binkert
ff2eea1ba3
eventq: revert code for unserializing events.
...
Since I never implemented a proper solution, put it back to something that
at least works for now. Once I add more event queues, I'll have to really
fix this though
2008-10-14 09:33:52 -07:00
Gabe Black
809f6cb6d1
CPU: Explain why some code is commented out.
2008-10-12 23:52:02 -07:00
Gabe Black
34ca72d16d
Get rid of some commented out code.
2008-10-12 23:50:22 -07:00
Gabe Black
3c4567f2a6
X86: Set the delayed commit flag in x86 microops appropriately.
2008-10-12 23:29:10 -07:00
Gabe Black
33ebd04474
X86: Make the local APIC timer event generate an interrupt.
2008-10-12 23:28:49 -07:00
Gabe Black
bdc28d793d
X86: Implement the EOI register in the local APIC.
2008-10-12 23:28:11 -07:00
Gabe Black
fd37688294
X86: Add some DPRINTFs to the local APIC.
2008-10-12 23:27:45 -07:00
Gabe Black
be6055e0f2
X86: Make auto eoi mode work in the I8259 PIC.
2008-10-12 23:27:08 -07:00
Gabe Black
fb5bb434a9
X86: Make non-specific EOI commands work.
2008-10-12 23:25:48 -07:00
Gabe Black
8e664f3959
X86: Make the I8259 PIC accept a specific EOI command.
2008-10-12 23:22:58 -07:00
Gabe Black
e3004c579f
X86: Fix the segment setting code in IRET, and make it restore the flags.
2008-10-12 23:05:22 -07:00
Gabe Black
349a155b6e
X86: Panic when an unimplemented fault is invoked, rather than spinning forever
2008-10-12 23:00:28 -07:00
Gabe Black
564eda827b
X86: Implement the swapgs instruction.
2008-10-12 23:00:07 -07:00
Gabe Black
a2e0d539d8
X86: Add wrval/rdval microops for reading significant miscregs.
2008-10-12 22:55:55 -07:00
Gabe Black
9e8e2f9ec6
X86: Make the x86 interrupt fault kick off the interrupt microcode.
2008-10-12 22:42:10 -07:00
Gabe Black
4c19c56a77
X86: Implement entering an interrupt in microcode.
2008-10-12 22:42:03 -07:00
Gabe Black
f813a4be49
X86: Make sure register microops set fault rather than returning one.
2008-10-12 22:24:06 -07:00
Gabe Black
961b40cdb5
X86: Implement an wrdh microop which loads bases/offsets from 16 byte descriptors.
2008-10-12 22:16:53 -07:00
Gabe Black
989fa4fc0f
X86: Make the MicroPC type 16 bit.
2008-10-12 20:48:24 -07:00
Gabe Black
6074b1abf2
X86: Implement local labels for the ROM that actually refer into the ROM.
2008-10-12 20:44:11 -07:00
Gabe Black
6b46e5204d
X86: Implement the chks check of interrupt gate target code segments.
2008-10-12 20:38:22 -07:00
Gabe Black
30feb90c1c
X86: Add a check type for interrupt gates.
2008-10-12 20:33:37 -07:00
Gabe Black
15f5bb3055
X86: Fix chks checking the submode for stack segments.
2008-10-12 20:29:52 -07:00
Gabe Black
9e1fe2050a
X86: Let segment manipulation microops be conditional.
2008-10-12 20:25:06 -07:00
Gabe Black
e9158d763a
X86: Let the microassembler know about the microcode only H segment.
2008-10-12 20:17:38 -07:00
Gabe Black
223fc41c07
X86: Fix the rdbase microop
2008-10-12 20:07:46 -07:00
Gabe Black
0756dbb37a
X86: Don't fetch in the simple CPU if you're in the ROM.
2008-10-12 19:32:06 -07:00
Gabe Black
f245358343
Get rid of old RegContext code.
2008-10-12 17:57:46 -07:00
Gabe Black
cefb768131
X86: Create a handy way to access labels from the ROM in microcode.
2008-10-12 17:52:51 -07:00
Gabe Black
e5f8092467
X86: Make X86's microcode ROM actually do something.
2008-10-12 17:48:44 -07:00
Gabe Black
c9ea0b7349
CPU: Make the highest order bit in the micro pc determine if it's combinational or from the ROM.
2008-10-12 16:59:55 -07:00
Gabe Black
2736086d7c
CPU: Create a microcode ROM object in the CPU which is defined by the ISA.
2008-10-12 15:59:21 -07:00
Gabe Black
6fd4eff68f
X86: Create an eret microop which returns from ROM to combinational decoding.
2008-10-12 15:53:04 -07:00
Gabe Black
4aa18aa800
X86: Make Br never report itself as the last microop.
2008-10-12 15:43:35 -07:00
Gabe Black
77c0e1d110
X86: Create a SeqOp class of microops and make Br one of them.
2008-10-12 15:33:17 -07:00
Gabe Black
a76c4b8ca1
X86: Implement CPUID with a magical function instead of microcode.
2008-10-12 15:31:28 -07:00
Gabe Black
d0a43ce2b2
X86: Fix the ordering of special physical address ranges.
2008-10-12 14:01:06 -07:00
Gabe Black
3a1905157e
X86: Create a mechanism for the IO APIC to access I8259 vectors.
2008-10-12 13:54:57 -07:00
Gabe Black
c35da8e495
X86: Actually use the extra vector bits we get from ICW2.
2008-10-12 13:51:48 -07:00
Gabe Black
ec9d3aad71
X86: Make the local APIC process interrupts and send them to the CPU.
2008-10-12 13:45:21 -07:00
Gabe Black
876f4845f2
X86: Make the local APIC handle interrupt messages from the IO APIC.
2008-10-12 13:44:24 -07:00
Gabe Black
4d5c7f7038
X86: Change the default value for the IO APIC redirection table.
2008-10-12 13:35:26 -07:00
Gabe Black
3420ad7644
X86: Make the bases for x86 fault class public.
2008-10-12 13:29:26 -07:00
Gabe Black
557bde43c3
X86: Make APICs communicate through the memory system.
2008-10-12 13:28:54 -07:00
Gabe Black
e459013182
Create a message port for sending messages as apposed to reading/writing a memory range.
2008-10-12 12:08:51 -07:00
Gabe Black
e0f137a87c
X86: Add a LocalApic trace flag.
2008-10-12 12:07:25 -07:00
Gabe Black
42ebebf99a
X86: Make the local APIC accessible through the memory system directly, and make the timer work.
2008-10-12 11:08:00 -07:00
Gabe Black
d9f9c967fb
Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
2008-10-12 09:09:56 -07:00
Gabe Black
c4f1cc3b48
CPU: Eliminate the get_vec function.
2008-10-12 08:24:09 -07:00
Gabe Black
0c3848732e
CPU: Add a getInterruptController function
2008-10-11 16:13:58 -07:00
Gabe Black
168e524b9b
X86: Create an IO APIC device.
2008-10-11 16:08:14 -07:00
Gabe Black
a2599e4fc1
X86: Set up a mechanism for the I8254 timer to cause interrupts.
2008-10-11 15:15:34 -07:00
Gabe Black
526933e5d0
X86: Add an Intel MP table to the simulation.
2008-10-11 15:14:37 -07:00
Gabe Black
f621b7b81f
CPU: Eliminate the simPalCheck funciton.
2008-10-11 12:17:24 -07:00
Gabe Black
da7209ec93
CPU: Eliminate the hwrei function.
2008-10-11 02:27:21 -07:00
Gabe Black
3af428606a
X86: Rename the PC device to Pc.
...
--HG--
rename : src/dev/x86/PC.py => src/dev/x86/Pc.py
2008-10-11 02:23:40 -07:00
Gabe Black
826621eb17
X86: Bring the South Bridge device into dev/x86 and get rid of south_bridge directory.
...
--HG--
rename : src/dev/x86/south_bridge/SouthBridge.py => src/dev/x86/SouthBridge.py
rename : src/dev/x86/south_bridge/south_bridge.cc => src/dev/x86/south_bridge.cc
rename : src/dev/x86/south_bridge/south_bridge.hh => src/dev/x86/south_bridge.hh
2008-10-11 02:21:44 -07:00
Gabe Black
bc2217eefc
X86: Change I8254 and PCSpeaker devices from subdevices to SimObjects and eliminate subdevices.
...
--HG--
rename : src/dev/x86/south_bridge/i8254.cc => src/dev/x86/i8254.cc
rename : src/dev/x86/south_bridge/i8254.hh => src/dev/x86/i8254.hh
rename : src/dev/x86/south_bridge/speaker.cc => src/dev/x86/speaker.cc
rename : src/dev/x86/south_bridge/speaker.hh => src/dev/x86/speaker.hh
2008-10-11 02:16:11 -07:00
Gabe Black
a6600fdd88
Devices: Make the Intel8254Timer device only use pointers to its counters.
2008-10-11 01:49:39 -07:00
Gabe Black
539563e04b
X86: Make the CMOS and I8259 devices use IntDev and IntPin.
2008-10-11 01:45:25 -07:00
Gabe Black
119e127d71
X86: Create the IntDev and IntPin system.
...
The IntDev class is a base for anything that supports IntPins. IntPins allow
devices to generically trigger interrupts on a particular pin of an IntDev
device without having to know what the device is or what pin they're attached
to.
2008-10-11 01:37:04 -07:00
Gabe Black
8c532d6297
X86: Hook the CMOS device to the I8259 PICs.
2008-10-11 01:31:32 -07:00
Gabe Black
cf9afbba51
X86: Make the I8259 decipher the commands it's given, and add some of it's registers.
2008-10-11 01:28:35 -07:00
Gabe Black
2753c07dc5
X86: Change the I8259 from a subdevice into a real SimObject.
...
--HG--
rename : src/dev/x86/south_bridge/i8259.cc => src/dev/x86/i8259.cc
rename : src/dev/x86/south_bridge/i8259.hh => src/dev/x86/i8259.hh
2008-10-11 01:22:20 -07:00
Gabe Black
f22c7d48f3
X86: Change the CMOS from a sub-device to a real SimObject
...
--HG--
rename : src/dev/x86/south_bridge/cmos.cc => src/dev/x86/cmos.cc
rename : src/dev/x86/south_bridge/cmos.hh => src/dev/x86/cmos.hh
2008-10-11 01:13:11 -07:00
Gabe Black
8c5dfa4532
TLB: Make all tlbs derive from a common base class in both python and C++.
2008-10-10 23:47:42 -07:00
Gabe Black
3d1734ec29
X86: Create SimObjects in python and C++ to represent the ACPI system description tables.
2008-10-10 23:43:33 -07:00
Gabe Black
f85a7f00c0
X86: Make the time on the RTC configurable.
2008-10-10 23:42:31 -07:00
Gabe Black
b03c95d075
X86: Create SimObjects in python and C++ to represent the Intel MP tables.
2008-10-10 23:39:53 -07:00
Nathan Binkert
89f016aacb
cprintf: properly deal with pointer types
2008-10-10 21:45:35 -07:00
Nathan Binkert
1f57193439
swig: Add in a %rename to allow the same name to appear in multiple namespaces.
2008-10-10 21:45:34 -07:00
Nathan Binkert
96936c6bf5
Rename the info function to inform to avoid likely name conflicts
2008-10-10 12:17:53 -07:00
Nathan Binkert
8ac63c48a4
automerge
2008-10-10 10:38:53 -07:00
Nathan Binkert
afb279b1bb
output: Make panic/fatal/warn more flexible so we can add some new ones.
...
The major thrust of this change is to limit the amount of code
duplication surrounding the code for these functions. This code also
adds two new message types called info and hack. Info is meant to be
less harsh than warn so people don't get confused and start thinking
that the simulator is broken. Hack is a way for people to add runtime
messages indicating that the simulator just executed a code "hack"
that should probably be fixed. The benefit of knowing about these
code hacks is that it will let people know what sorts of inaccuracies
or potential bugs might be entering their experiments. Finally, I've
added some flags to turn on and off these message types so command
line options can change them.
2008-10-10 10:18:28 -07:00
Nathan Binkert
b25e56b32a
gdb: add a debugging function that enters the python interpreter.
2008-10-10 10:15:01 -07:00
Nathan Binkert
70dbe61ffc
jobfile: Add support for dictionaries as jobfile options.
...
If the same dictionary option is seen in several options, those
dictionaries are composed. If you define the same dictionary key in
multiple options, the system flags an error.
Also, clean up the jobfile code so that it is more debuggable.
2008-10-10 10:15:01 -07:00
Nathan Binkert
84364f36d0
python: Add a utility for nested attribute dicts.
...
Change attrdict so that attributes that begin with an underscore don't
go into the dict.
2008-10-10 10:15:00 -07:00
Nathan Binkert
5586b1539b
misc: remove #include <cassert> from misc.hh since not everyone needs it.
2008-10-10 10:15:00 -07:00
Gabe Black
ec0fb05d64
X86: Turn SMBios structures into simobjects.
2008-10-10 03:50:51 -07:00
Gabe Black
9be6e08227
X86: Add a couple comments to the bios SConscript
2008-10-10 03:50:42 -07:00
Gabe Black
d897aa939f
X86: Move the smbios objects into a folder for BIOS objects.
2008-10-10 03:50:18 -07:00
Gabe Black
57d663877e
X86: Fix compilation with new eventq API.
2008-10-10 03:50:07 -07:00
Nathan Binkert
94b08bed07
SimObjects: Clean up handling of C++ namespaces.
...
Make them easier to express by only having the cxx_type parameter which
has the full namespace name, and drop the cxx_namespace thing.
Add support for multiple levels of namespace.
2008-10-09 22:19:39 -07:00
Nathan Binkert
4ecc5d53a3
range_map: Add a method to find which range a single value falls into.
2008-10-09 22:19:38 -07:00
Nathan Binkert
6ccf28c896
style: conform to M5 style.
2008-10-09 09:25:41 -07:00
Nathan Binkert
b556dc4119
mem: Add a method for setting the time on a packet.
2008-10-09 04:58:24 -07:00
Nathan Binkert
e06321091d
eventq: convert all usage of events to use the new API.
...
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
2008-10-09 04:58:24 -07:00
Nathan Binkert
8291d9db0a
eventq: Major API change for the Event and EventQueue structures.
...
Since the early days of M5, an event needed to know which event queue
it was on, and that data was required at the time of construction of
the event object. In the future parallelized M5, this sort of
requirement does not work well since the proper event queue will not
always be known at the time of construction of an event. Now, events
are created, and the EventQueue itself has the schedule function,
e.g. eventq->schedule(event, when). To simplify the syntax, I created
a class called EventManager which holds a pointer to an EventQueue and
provides the schedule interface that is a proxy for the EventQueue.
The intent is that objects that frequently schedule events can be
derived from EventManager and then they have the schedule interface.
SimObject and Port are examples of objects that will become
EventManagers. The end result is that any SimObject can just call
schedule(event, when) and it will just call that SimObject's
eventq->schedule function. Of course, some objects may have more than
one EventQueue, so this interface might not be perfect for those, but
they should be relatively few.
2008-10-09 04:58:23 -07:00
Nathan Binkert
68c75c589b
pdb: Try to make pdb work better.
...
I've done a few things here. First, I invoke the script a little bit
differently so that pdb doesn't get confused. Second, I've stored the
actual filename in the module's __file__ so that pdb can find the
source file on your machine.
2008-10-09 04:58:23 -07:00
Nathan Binkert
886c5f8fe5
SINIC: Commit old code from ASPLOS 2006 studies.
...
NOTE: This code was written by Nathan Binkert in 2006 and is properly copyright
"The Regents of the University of Michigan"
2008-10-09 04:58:23 -07:00
Nathan Binkert
eb89a23556
eventq: Don't use inline friend function when a static function will do.
...
Another good reason to avoid this is that swig will try to wrap the friend,
but it won't try to wrap a private static function.
2008-10-09 04:58:23 -07:00
Nathan Binkert
a589eb4053
SCons: add code to provide a libm5 shared library.
...
Targets look like libm5_debug.so. This target can be dynamically
linked into another C++ program and provide just about all of the M5
features. Additionally, this library is a standalone module that can
be imported into python with an "import libm5_debug" type command
line.
2008-10-09 04:58:23 -07:00
Nathan Binkert
0b83563a9c
eventq: I'm sick of the warning about MaxTick being unused.
2008-10-09 04:58:23 -07:00
Nathan Binkert
7cc2a88038
stats: use properly signed types for looping and comparison
2008-10-09 04:58:23 -07:00
Nathan Binkert
a52dce6d62
style: Bring statistics code in line with the proper style.
2008-10-09 04:58:23 -07:00
Gabe Black
b66eb3b8d1
O3: Generaize the O3 IMPL class so it isn't split out by ISA.
...
--HG--
rename : src/cpu/o3/sparc/cpu_builder.cc => src/cpu/o3/cpu_builder.cc
rename : src/cpu/o3/sparc/dyn_inst.cc => src/cpu/o3/dyn_inst.cc
rename : src/cpu/o3/sparc/impl.hh => src/cpu/o3/impl.hh
rename : src/cpu/o3/sparc/thread_context.cc => src/cpu/o3/thread_context.cc
2008-10-09 00:10:02 -07:00
Gabe Black
f57c286d2c
O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA.
...
--HG--
rename : src/cpu/o3/dyn_inst.hh => src/cpu/o3/dyn_inst_decl.hh
rename : src/cpu/o3/alpha/dyn_inst_impl.hh => src/cpu/o3/dyn_inst_impl.hh
2008-10-09 00:09:26 -07:00
Gabe Black
e09c403d32
O3: Generalize the O3 CPU object so it isn't split out by ISA.
2008-10-09 00:08:50 -07:00
Gabe Black
975c9e3af8
Microcode: Fix a silent typo error in the microcode assembler.
2008-10-09 00:07:38 -07:00
Gabe Black
523531a40e
Microcode: Fix a very old bug with parsing external labels in microcode.
2008-10-09 00:07:21 -07:00
Gabe Black
c5c6ad7ed6
CPU: Fix where setMicroPC was being called instead of setNextMicroPC.
2008-10-09 00:06:05 -07:00
Gabe Black
e1b306fa53
X86: Fix the debugging microops. The debug functions can't handle a string object format.
2008-10-09 00:05:39 -07:00
Gabe Black
569db520ad
X86: Make far ret modify CS instead of some random selector.
2008-10-09 00:04:36 -07:00
Nathan Binkert
6b2bb53fd6
python: cleanup options parsing stuff so that it properly deals with defaults.
...
While we're at it, make it possible to run main.py in a somewhat
standalone mode again so that we can test things without compiling.
2008-10-06 09:31:51 -07:00
Korey Sewell
6c046a28dc
fix shadow set bugs in MIPS code that caused out of bounds access...
...
panic rdpgpr/wrpgpr instructions until a better impl.
of MIPS shadow sets is available.
2008-10-06 02:07:04 -04:00
Nathan Binkert
b25755993b
unittest: Add unit tests to the scons framework.
...
Also fix the unit tests so they actually compile correctly.
2008-10-02 11:27:01 -07:00
Nathan Binkert
52493b2720
unittest: Cleanup unit tests. Follow style. Garbage Collect.
...
--HG--
rename : src/unittest/rangemaptest2.cc => src/unittest/rangemultimaptest.cc
2008-10-02 11:26:59 -07:00
Nathan Binkert
67a2918abc
stats: Fix small bug pointed out by unit testing.
2008-10-02 11:26:59 -07:00
Ali Saidi
0a1613abe1
Output: Verify output files are open after opening them.
2008-10-02 12:46:57 -04:00
Steve Reinhardt
7bf6a219db
Make overriding port assignments in Python work,
...
and print better error messages when it doesn't.
2008-09-29 23:30:14 -07:00
Steve Reinhardt
45cba35fc1
Fix EVENTQ_DEBUG vs DEBUG_EVENTQ #define inconsistency.
2008-09-29 23:30:14 -07:00
Nathan Binkert
1e9c428522
alpha: Need to include cstring so that g++ 4.3 works.
2008-09-29 07:15:30 -07:00
Nathan Binkert
80d9be86e6
gcc: Add extra parens to quell warnings.
...
Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off. Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.
2008-09-27 21:03:49 -07:00
Nathan Binkert
cf7ddd8e8a
style: Make a style pass over the whole arch/alpha directory.
2008-09-27 21:03:48 -07:00
Nathan Binkert
82f5723c7a
alpha: Clean up namespace usage.
2008-09-27 21:03:47 -07:00
Nathan Binkert
8ea5176b7f
arch: TheISA shouldn't really ever be used in the arch directory.
...
We should always refer to the specific ISA in that arch directory.
This is especially necessary if we're ever going to make it to the
point where we actually have heterogeneous systems.
2008-09-27 21:03:46 -07:00
Nathan Binkert
0b30c345f1
alpha: Get rid fo the namespace called EV5.
...
We're never going to do an alpha platform other than the one we've got.
2008-09-27 21:03:45 -07:00
Nathan Binkert
819023b8e2
style
2008-09-27 07:25:04 -07:00
Nathan Binkert
83f3bff643
add a bit of style
2008-09-27 00:15:45 -07:00
Nathan Binkert
ca4baf3871
style: missed space after switch
2008-09-26 09:37:21 -07:00
Nathan Binkert
9838be2521
When nesting if statements, use braces to avoid ambiguous else clauses.
2008-09-26 08:18:57 -07:00
Nathan Binkert
abca171e24
Use logical operator instead of bitwise operator for correctness.
2008-09-26 08:18:56 -07:00
Nathan Binkert
6798aa14ed
style: bring this file into M5 style, use the new pte translate function.
2008-09-26 08:18:55 -07:00
Nathan Binkert
a053055e17
scons: disable several gcc warnings for swig autogenerated wrapper code.
2008-09-26 08:18:54 -07:00
Nathan Binkert
0309c877f3
style: These files didn't even come close to following the M5 style guide.
2008-09-26 08:18:53 -07:00
Kevin Lim
b784903207
O3CPU: Fix thread writeback logic.
...
Fix the logic in the LSQ that determines if there are any stores to
write back. In the commit stage, check for thread specific writebacks
instead of just any writeback.
2008-09-26 07:44:07 -07:00
Kevin Lim
712a8ee700
O3CPU: Add a hack to ensure that nextPC is set correctly after syscalls.
...
Just check CPU's nextPC before and after syscall and if it changes,
update this instruction's nextPC because the syscall must have changed
the nextPC.
2008-09-26 07:44:06 -07:00
Nathan Binkert
70ec46de17
sparc: Fix style, create a helper function for translation.
...
The translate function simplifies code and removes some compiler
warnings in gcc 3.4
2008-09-23 20:38:02 -07:00
Nathan Binkert
38dd9687ce
scons: Separate swig environment so we can have different flags.
...
Swig code isn't quite perfect, so let's not turn on all of the warnings.
2008-09-22 08:25:58 -07:00
Nathan Binkert
6efb930e19
gcc: Version 4.3 is pretty anal about shadowing types, placate it.
...
In the future, it would be nice to put the O3CPU into its own
namespace so that we don't end up hardcoding pointers to the global
namespace.
2008-09-22 08:25:57 -07:00
Nathan Binkert
f3f4b17c5b
style
2008-09-22 08:21:47 -07:00
Nathan Binkert
4826610d86
We're using the static keyword improperly in some cases.
2008-09-19 09:42:54 -07:00
Nathan Binkert
ce3d8c2b03
atomicio: provide atomic read and write functions.
...
These functions keep trying to read and write until all data has been
transferred, or an error occurrs. In the case where an end of file
hasn't been reached, but all of the bytes have not been read/written,
try again. On EINTR, try again.
2008-09-19 09:42:31 -07:00
Nathan Binkert
af9c5e05f7
Use C++ limits where applicable for portability
2008-09-19 09:11:43 -07:00
Nathan Binkert
befae3c0b0
Use the proper version of C++ headers
2008-09-19 09:11:43 -07:00
Nathan Binkert
ea83cedcf6
Check the return value of I/O operations for failure
2008-09-19 09:11:42 -07:00
Nathan Binkert
f066db7fcd
inifile: Whack preprocessor access.
...
We haven't used the preprocessor feature of the inifile stuff in a
very long time, so let's get rid of it since it would otherwise take
effort to maintain.
2008-09-19 09:11:40 -07:00
Ali Saidi
3a3e356f4e
style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
2008-09-10 14:26:15 -04:00
Nathan Binkert
09a8fb0b52
style: this file did not conform to style
2008-09-09 16:27:17 -07:00
Nathan Binkert
496d3f2789
style: This file hugely violated the M5 style.
...
Remove a bunch of unused cruft from the interface while we're at it
2008-09-08 18:03:52 -07:00
Gabe Black
30bc897613
X86: Fix the microcode for sign/zero extending moves that use high byte registers.
2008-09-03 00:52:54 -04:00
Clint Smullen
4aa017affc
Device: Fix bug in DmaPort::recvRetry. The interface attempts to send the same packet again.
...
It doesn't cause a problem currently, however with a different Memory Object it could cause
problems
2008-08-26 02:37:26 -04:00
Ali Saidi
3d5fe0c372
IGbE: Patches I neglected to apply before pushing the previous igbe changeset
2008-08-24 15:27:49 -04:00
Gabe Black
3633a916c2
CPU: Get rid of two more duplicated CPU params.
2008-08-19 21:59:09 -07:00
Richard Strong
8d018aef0f
Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its
...
python type of a latency. In addition, the multiple definitions of profile in the different cpu models caused
problems for intialization of the interval value. If a child class's profile value was defined, the parent
BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the
multiple redifitions of profile in the child CPU classes.
2008-08-18 10:50:58 -07:00
Ali Saidi
6248e12704
Add the ability to specify a think time before descriptor fetch/writeback starts/ends as well as after read/write dmas
2008-08-13 17:41:58 -04:00
Ali Saidi
549c43b2d0
Add the ability for a DMA to tack on an extra delay after the DMA is actually finished.
2008-08-13 17:41:56 -04:00
Ali Saidi
05954e1ba7
More subtle fixes to how interrupts are supposed to work in the device. Fix postedInterrupts statistics.
2008-08-13 16:30:30 -04:00
Ali Saidi
91d968783e
Return an UnimpFault for an ITB translation of an uncachable address. We don't support fetching from uncached addresses in Alpha and it means that a speculative fetch can clobber device registers.
2008-08-13 16:29:59 -04:00
Nathan Binkert
1b1a7e33e7
style
2008-08-11 14:47:49 -07:00
Nathan Binkert
9cf8ad3a17
params: Get rid of the remnants of the old style parameter configuration stuff.
2008-08-11 12:22:17 -07:00
Nathan Binkert
ee62a0fec8
params: Convert the CPU objects to use the auto generated param structs.
...
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
2008-08-11 12:22:16 -07:00
Steve Reinhardt
3448a12208
Make time format in 'started' line same as 'compiled'.
...
Also make -B output consistent with normal header, and
only include actual build options.
2008-08-04 01:46:46 -04:00
Steve Reinhardt
58c63ea8b1
Get rid of outputStream... wasn't really being used
...
(except for warn()) and new -r/-e options make it
not worth fixing.
2008-08-04 01:45:12 -04:00
Steve Reinhardt
fe8aeff362
Add -r/-e options to redirect stdout/stderr.
...
Better than using shell since it automatically uses -d directory
for output files (creating it as needed).
2008-08-04 00:40:31 -04:00
Nathan Binkert
50ef39af82
sockets: Add a function to disable all listening sockets.
...
When invoking several copies of m5 on the same machine at the same
time, there can be a race for TCP ports for the terminal connections
or remote gdb. Expose a function to disable those ports, and have the
regression scripts disable them. There are some SimObjects that have
no other function than to be used with ports (NativeTrace and
EtherTap), so they will panic if the ports are disabled.
2008-08-03 18:19:55 -07:00
Nathan Binkert
ede89c2d54
libm5: Create a libm5 static library for embedding m5.
...
This should allow m5 to be more easily embedded into other simulators.
The m5 binary adds a simple main function which then calls into the m5
libarary to start the simulation. In order to make this work
correctly, it was necessary embed python code directly into the
library instead of the zipfile hack. This is because you can't just
append the zipfile to the end of a library the way you can a binary.
As a result, Python files that are part of the m5 simulator are now
compile, marshalled, compressed, and then inserted into the library's
data section with a certain symbol name. Additionally, a new Importer
was needed to allow python to get at the embedded python code.
Small additional changes include:
- Get rid of the PYTHONHOME stuff since I don't think anyone ever used
it, and it just confuses things. Easy enough to add back if I'm wrong.
- Create a few new functions that are key to initializing and running
the simulator: initSignals, initM5Python, m5Main.
The original code for creating libm5 was inspired by a patch Michael
Adler, though the code here was done by me.
2008-08-03 18:19:54 -07:00
Nathan Binkert
678abbc364
syscall: Avoid a compiler warning which turns into a bug.
...
Simply cast the result to an int and life is good.
2008-08-03 18:19:53 -07:00
Steve Reinhardt
62c08a75ad
Make default PhysicalMemory latency slightly more realistic.
...
Also update stats to reflect change.
2008-08-03 18:13:29 -04:00
Gabe Black
b179c3f4cd
X86: Make hint nops consume their modrm byte.
2008-08-03 14:43:24 -07:00
Nathan Binkert
e98ccd309b
kill unused code
2008-08-02 20:42:15 -07:00
Nathan Binkert
4b1e0d235d
scons: Get rid of generate.py in the build system.
...
I decided that separating some of the scons code into generate.py was
just a bad idea because it caused the dependency system to get all
messed up. If separation is the right way to go in the future, we
should probably use the sconscript mechanism, not the mechanism that I
just removed.
2008-07-31 08:01:38 -07:00
Michael Adler
f3a3ab7f2c
syscall: Fix TTY emulation in fstat() user-mode simulation for fd 1 (stdout).
...
The code didn't set S_IFCHR in the st_mode
2008-07-24 16:31:33 -07:00
Michael Adler
5f42bfcd56
process: separate stderr from stdout
...
- Add the option of redirecting stderr to a file. With the old
behaviour, stderr would follow stdout if stdout was to a file, but
stderr went to the host stderr if stdout went to the host stdout. The
new default maintains stdout and stderr going to the host. Now the
two can specify different files, but they will share a file descriptor
if the name of the files is the same.
- Add --output and --errout options to se.py to go with --input.
2008-07-23 14:41:34 -07:00
Michael Adler
2cd04fd6da
syscalls: Add a bunch of missing system calls.
...
readlink, umask, truncate, ftruncate, mkdir, and getcwd.
2008-07-23 14:41:33 -07:00
Michael Adler
8c4f18f6f5
RemoteGDB: add an m5 command line option for setting or disabling remote gdb.
2008-07-23 14:41:33 -07:00
Steve Reinhardt
aa2bb4f7b9
Get rid of useless m5_assert macro.
...
Its only purpose was to print the cycle number but that already
happens in the SIGABRT handler. No one used it anyway.
2008-07-15 14:38:51 -04:00
Steve Reinhardt
8e7ddce284
Use ReadResp instead of LoadLockedResp for LoadLockedReq responses.
2008-07-15 14:38:51 -04:00
Steve Reinhardt
6262e0d909
Add missing newlines to Bus DPRINTFs.
2008-07-15 14:38:51 -04:00
Nathan Binkert
f9a597ddf3
m5ops: clean up the m5ops stuff.
...
- insert warnings for deprecated m5ops
- reserve opcodes for Ali's stuff
- remove code for stuff that has been deprecated forever
- simplify m5op_alpha
2008-07-11 08:52:50 -07:00
Nathan Binkert
88766f7c71
style: fix indentation and formatting of the pseudo insts.
2008-07-11 08:52:50 -07:00
Nathan Binkert
f90b08a5cc
eventq: change the event datastructure back to LIFO.
...
The status quo is preferred since it is less likely that people will
rely on LIFO than FIFO, and when we move to a parallelized M5, no
ordering between events of the same time/priority will be guaranteed.
2008-07-11 08:48:50 -07:00
Nathan Binkert
10df68dd72
eventq: new eventq data structure. The new data structure is singly
...
linked list sorted by time and priority. For things of the same time
and priority, a second, circularly linked list maintains the data
structure. Events of the same time and priority are now inserted in
FIFO order instead of LIFO order. This dramatically improves the
performance of systems that schedule multiple events at the same time.
The FIFO order version is not preferred to LIFO (because it may cause
people to rely on it), but I'm going to commit it anyway and
immediately commit the preferred LIFO version on top.
2008-07-11 08:38:31 -07:00
Nathan Binkert
93517dd90c
eventq: Clean up the Event class so that it uses fewer bytes. This
...
will hopefullly allow it to fit in a cache line.
2008-07-10 21:35:42 -07:00
Ali Saidi
7a83c50a59
Fix cases where RADV interrupt timer is used and make ITR interrupt moderation not always delay if no interrupts have been posted for the ITR value.
2008-07-01 10:30:08 -04:00
Ali Saidi
a4a7a09e96
Remove delVirtPort() and make getVirtPort() only return cached version.
2008-07-01 10:25:07 -04:00
Ali Saidi
c5fbbf376a
Change everything to use the cached virtPort rather than created their own each time.
...
This appears to work, but I don't want to commit it until it gets tested a lot more.
I haven't deleted the functionality in this patch that will come later, but one question
is how to enforce encourage objects that call getVirtPort() to not cache the virtual port
since if the CPU changes out from under them it will be worse than useless. Perhaps a null
function like delVirtPort() is still useful in that case.
2008-07-01 10:24:19 -04:00
Ali Saidi
50e3e50e1a
Make the cached virtPort have a thread context so it can do everything that a newly created one can.
2008-07-01 10:24:16 -04:00
Ali Saidi
9bd0bfe559
After a checkpoint (and thus a stats reset), the not_idle_fraction/notIdleFraction statistic is really wrong.
...
The notIdleFraction statistic isn't updated when the statistics reset, probably because the cpu Status information
was pulled into the atomic and timing cpus. This changeset pulls Status back into the BaseSimpleCPU object. Anyone
care to comment on the odd naming of the Status instance? It shouldn't just be status because that is confusing
with Port::Status, but _status seems a bit strage too.
2008-07-01 10:24:09 -04:00
Steve Reinhardt
96bbccc36b
Automated merge after backout.
2008-06-28 13:20:00 -04:00
Steve Reinhardt
caaac16803
Backed out changeset 94a7bb476fca: caused memory leak.
2008-06-28 13:19:38 -04:00
Ali Saidi
3205768ea5
Automated merge with http://repo.m5sim.org/m5-stable
2008-06-24 15:51:12 -04:00
Ali Saidi
57b5de6b9f
Checkpoinging/SWIG: Undo part of changeset 5464 since it broke checkpointing.
2008-06-24 15:48:45 -04:00
Gabe Black
18c83be507
SimObject: Add in missing includes of <string> and fix minor style problem.
2008-06-21 14:23:58 -04:00
Steve Reinhardt
1434b86943
Make bus address conflict error more informative
2008-06-21 01:06:27 -04:00
Steve Reinhardt
6b45238316
Generate more useful error messages for unconnected ports.
...
Force all non-default ports to provide a name and an
owner in the constructor.
2008-06-21 01:04:43 -04:00
Nathan Binkert
c1584e4227
imported patch sim_object_params.diff
2008-06-18 12:07:15 -07:00
Nathan Binkert
67a33eed40
AtomicSimpleCPU: Separate data stalls from instruction stalls.
...
Separate simulation of icache stalls and dat stalls.
2008-06-18 10:15:21 -07:00
Nathan Binkert
1099a9838a
Ethernet: share statistics between all ethernet devices and apply some
...
of those statistics to the e1000 model.
2008-06-17 22:22:44 -07:00
Nathan Binkert
87d03d00cd
inet: initialization fixes.
...
Make sure variables are properly initialized and also make sure that
truth testing works properly.
2008-06-17 22:14:12 -07:00
Nathan Binkert
8042b8f4c7
PacketFifo: Get slack out of the EthPacketData structure. This allows
...
a packet to exist in multiple FIFOs if desired.
2008-06-17 21:34:27 -07:00
Nathan Binkert
163465ac08
ThreadState: Ensure that kernelStats is properly initialized
2008-06-17 21:11:20 -07:00
Nathan Binkert
9dc4e2952c
rename MipsConsole to MipsBackdoor
...
--HG--
rename : src/dev/mips/MipsConsole.py => src/dev/mips/MipsBackdoor.py
rename : src/dev/mips/console.cc => src/dev/mips/backdoor.cc
rename : src/dev/mips/console.hh => src/dev/mips/backdoor.hh
2008-06-17 20:39:51 -07:00
Nathan Binkert
934523c3a0
rename AlphaConsole to AlphaBackdoor
...
--HG--
rename : src/dev/alpha/AlphaConsole.py => src/dev/alpha/AlphaBackdoor.py
rename : src/dev/alpha/console.cc => src/dev/alpha/backdoor.cc
rename : src/dev/alpha/console.hh => src/dev/alpha/backdoor.hh
2008-06-17 20:36:39 -07:00
Nathan Binkert
6ff4539901
Change the default output filename for the terminal so it's more obvious.
...
--HG--
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console => tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console => tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
2008-06-17 20:30:37 -07:00
Nathan Binkert
00df9016fe
Rename SimConsole to Terminal since it makes more sense
...
--HG--
rename : src/dev/SimConsole.py => src/dev/Terminal.py
rename : src/dev/simconsole.cc => src/dev/terminal.cc
rename : src/dev/simconsole.hh => src/dev/terminal.hh
2008-06-17 20:29:06 -07:00
Nathan Binkert
fa8f91fdc0
physmem: Add a null option to physical memory so it doesn't store data.
2008-06-15 21:39:29 -07:00
Nathan Binkert
e3c267a3db
port: Clean up default port setup and port switchover code.
2008-06-15 21:34:32 -07:00
Nathan Binkert
b429b1759d
params: Prevent people from setting attributes on vector params.
2008-06-15 21:26:33 -07:00
Nathan Binkert
6dedc645f7
add compile flags to m5
2008-06-15 20:56:35 -07:00
Nathan Binkert
b2036bfda8
Command line option to print out List of SimObjects and their parameters
2008-06-14 21:51:08 -07:00
Nathan Binkert
bbeb8082a5
main: add .m5/options.py processing. This file is processed before
...
arguments are parsed so that they can change the default options for
various config parameters.
2008-06-14 21:16:00 -07:00
Nathan Binkert
fc48d1dcf5
Add .m5 configuration directory
2008-06-14 21:15:59 -07:00
Nathan Binkert
779c31077c
python: Separate the options parsing stuff. Remove options parsing stuff from
...
main.py so things are a bit more obvious.
2008-06-14 21:15:58 -07:00
Nathan Binkert
4afdc40d70
params: Fix the memory bandwidth parameter
2008-06-14 20:42:45 -07:00
Nathan Binkert
3d2e7797cc
params: Fix floating point parameters
2008-06-14 20:39:31 -07:00
Nathan Binkert
f82d4e2364
python: Move various utility classes into a new m5.util package so
...
they're all in the same place. This also involves having just one
jobfile.py and moving it into the utils directory to avoid
duplication. Lots of improvements to the utility as well.
--HG--
rename : src/python/m5/attrdict.py => src/python/m5/util/attrdict.py
rename : util/pbs/jobfile.py => src/python/m5/util/jobfile.py
rename : src/python/m5/util.py => src/python/m5/util/misc.py
rename : src/python/m5/multidict.py => src/python/m5/util/multidict.py
rename : util/stats/orderdict.py => src/python/m5/util/orderdict.py
2008-06-14 20:19:49 -07:00
Nathan Binkert
fe325c7f43
MemReq: Add option to reset the time on a request.
2008-06-14 19:39:01 -07:00
Nathan Binkert
ce43e46576
Fix various SWIG warnings
2008-06-14 12:57:21 -07:00
Nathan Binkert
7a58b5a38a
Add missing dependencies on .i files
2008-06-14 12:10:50 -07:00
Nathan Binkert
2d037682ff
scons: proper fix for hg version stuff
2008-06-14 10:30:18 -07:00
Nathan Binkert
fe4fd9f414
scons: fix program_info.cc generation
2008-06-13 17:34:22 -07:00
Steve Reinhardt
dace77dc4a
Automated merge with ssh://m5sim.org//repo/m5
2008-06-13 01:59:10 -04:00
Steve Reinhardt
caccbd1edc
Get rid of bogus bus assertion.
...
It runs out that if a MemObject turns around and does a send in its
receive callback, and there are other sends already scheduled, then
it could observe a state where it's not at the head of the list but
the bus's sendEvent is not scheduled (because we're still in the
middle of processing the prior sendEvent).
2008-06-13 01:33:49 -04:00
Steve Reinhardt
024ec4c5c3
Get rid of bogus cache assertion.
...
I was asserting that the only reason you would defer targets is if
a write came in while you had an outstanding read miss, but there's
another case where you could get a read access after you've snooped
an invalidation and buffered it because it applies to a prior
outstanding miss.
2008-06-13 01:29:20 -04:00
Ali Saidi
907b28cc62
HG: Add compiled hg revision and date to the standard M5 output.
2008-06-13 01:09:04 -04:00
Gabe Black
2b4874449c
Alpha: Get rid of an old include of a non-existant file.
2008-06-12 01:54:21 -04:00
Gabe Black
7be8e671f1
Params: Allow nested namespaces in cxx_namespace
2008-06-12 01:00:29 -04:00
Gabe Black
5b5875341c
X86: Make the cpuid processor identifier return a real string.
2008-06-12 01:00:19 -04:00
Gabe Black
c625cf0ae1
X86: Make the code compile as 32 bit.
2008-06-12 01:00:05 -04:00
Gabe Black
23c04b8c66
Params: Remove an unnecessary include.
2008-06-12 00:59:58 -04:00
Gabe Black
bceaa257a3
X86: Make the e820 table manually or automatically configurable from python.
2008-06-12 00:58:36 -04:00
Gabe Black
4f4ff17578
X86: Make the disassembly for halt conform with the other microops.
2008-06-12 00:58:27 -04:00
Gabe Black
31d40ad7c2
X86: Implement and hook up STI and CLI instructions.
2008-06-12 00:58:19 -04:00
Gabe Black
da20c0ec54
X86: Make sure there's something to catch when the kernel messes with ports "behind" the pci config magic ports.
2008-06-12 00:58:13 -04:00
Gabe Black
1f5b992b58
X86: Make the platform object initialize channel 0 of the PIT.
2008-06-12 00:56:54 -04:00
Gabe Black
16e26fbf03
X86: Hook the speaker device to the pit device.
2008-06-12 00:56:17 -04:00
Gabe Black
da7f512067
Timer: Fill out the periodic modes a little.
2008-06-12 00:56:07 -04:00
Gabe Black
4f9a0402f6
Dev: Seperate the 8254 timer from tsunami and use it in that and the PC.
2008-06-12 00:54:48 -04:00
Gabe Black
0368ccdeda
BitUnion: Take out namespace declaration so bitunions can be declared inside classes.
2008-06-12 00:54:32 -04:00
Gabe Black
81936ae2ed
X86: Add an event for the apic timer timeout. It doesn't get used yet.
2008-06-12 00:54:19 -04:00
Gabe Black
6b8d0363ee
X86: Rename the divide count register to divide configuration.
2008-06-12 00:54:12 -04:00
Gabe Black
b10742ee2b
X86: Make the apic isr and irr work.
2008-06-12 00:54:05 -04:00
Gabe Black
69000baef3
X86: Make the apic task priority register work.
2008-06-12 00:54:01 -04:00
Gabe Black
e9c481ea4a
X86: Make the logical destination and destination format work.
2008-06-12 00:53:50 -04:00
Gabe Black
ed23a4970b
X86: Make the apic ID register work.
2008-06-12 00:53:43 -04:00
Gabe Black
8a6723e038
X86: Make the apic version register work.
2008-06-12 00:53:37 -04:00
Gabe Black
8d2416c6e9
X86: Implement a partial, sort of correct version of the protected mode variant of iret.
2008-06-12 00:53:01 -04:00
Gabe Black
66f54a6037
X86: Change how segment loading is performed.
2008-06-12 00:52:12 -04:00
Gabe Black
129831c116
X86: Make pushes and pops use the stack size instead of the data size.
2008-06-12 00:51:57 -04:00
Gabe Black
b05299253f
X86: In non 64bit mode, throw a fault when a NULL segment is accessed.
2008-06-12 00:51:50 -04:00
Gabe Black
a8384311d5
X86: Take advantage of the new meta register.
2008-06-12 00:51:14 -04:00
Gabe Black
d4e7c7edd3
X86: Keep handy values like the operating mode in one register.
2008-06-12 00:50:25 -04:00
Gabe Black
fa7c81c6df
X86: Change what the microop chks does.
...
Instead of computing the segment descriptor address, this now checks if a
selector value/descriptor are legal for a particular purpose.
2008-06-12 00:50:10 -04:00
Gabe Black
6bd9cf3594
X86: Add a microop to read a segments attribute register.
2008-06-12 00:50:05 -04:00
Gabe Black
e0c20386ac
X86: Add microops and supporting code to manipulate the whole rflags register.
2008-06-12 00:49:50 -04:00
Gabe Black
2bb8933f78
X86: Add microops which panic, fatal, warn, and warn_once.
2008-06-12 00:49:25 -04:00
Gabe Black
bbc1f394ff
X86: Truncate descriptors to 16 bits.
2008-06-12 00:49:16 -04:00
Gabe Black
6106b05b6e
X86: Redo BSF.
2008-06-12 00:48:58 -04:00
Gabe Black
dfc2d44ea3
X86: Flesh out 3dnow instruction decoding a bit and grab the byte immediate.
2008-06-12 00:48:46 -04:00
Gabe Black
de6eeaaa27
X86: Make string instructions work when rcx=0.
2008-06-12 00:48:15 -04:00
Gabe Black
8688ef3fe5
X86: Have all 8 machine check registers since the kernel assumes they're there.
2008-06-12 00:48:02 -04:00
Gabe Black
a8e3001df8
X86: Bypass unaligned access support for register addressed MSRs.
2008-06-12 00:47:25 -04:00
Gabe Black
b3e55339f9
X86: Remove enforcement of APIC register access alignment. Panic if more than one register is accessed at a time.
2008-06-12 00:46:22 -04:00
Gabe Black
8e2991b529
X86: Fix the implementation of BSF.
2008-06-12 00:46:04 -04:00
Gabe Black
16e189fad2
X86: Bit scan forward/reverse were accidentally transposed.
2008-06-12 00:45:52 -04:00
Gabe Black
254cc07650
X86: Fix a byte register indexing issue in the sign extending move from memory microcode.
2008-06-12 00:45:22 -04:00
Gabe Black
8501a90f59
X86: Add in some support for the tsc register.
2008-06-12 00:39:10 -04:00
Gabe Black
d093fcb079
CPU: Make the simple cpu trace data for loads/stores.
2008-06-12 00:35:50 -04:00
Ali Saidi
5797ff1016
X86: Fix building on *BSD hosts
2008-06-11 10:54:12 -04:00
Ali Saidi
fd3e661cd3
SCons: Fix more SCons version issues
2008-06-11 10:54:08 -04:00
Ali Saidi
f5e36d156d
IGbE: Implement sending packet that is contained in more than 2 descriptors.
...
--HG--
extra : convert_revision : 8fb7d5fad5cb840f69c31aa8b331dbe09e46ee9d
2008-05-20 16:06:56 -04:00
Stephen Hines
b7af65f414
SCons: Fixing SCons bug 2006 issues for non-alpha ISAs
...
--HG--
extra : convert_revision : 26e3edef06d6f82aaf162825c151d18faadd6e72
2008-05-20 14:04:53 -04:00
Ali Saidi
e71a5270a2
Make sure that output files are always checked success before they're used.
...
Make OutputDirectory::resolve() private and change the functions using
resolve() to instead use create().
--HG--
extra : convert_revision : 36d4be629764d0c4c708cec8aa712cd15f966453
2008-05-15 19:10:26 -04:00
Ali Saidi
4a4317ae18
SCons: More scons fixing for SCons bug 2006
...
--HG--
extra : convert_revision : d3656ab1e3c18251d4bcf6f5a31103d4b2dfdc43
2008-05-06 16:22:14 -04:00
Ali Saidi
8af6dc118c
SCons: add comments to SConscript documenting bug workaround
...
--HG--
extra : convert_revision : e6cdffe953d56b96c76c7ff14d2dcc3de3ccfcc3
2008-04-10 15:38:10 -04:00
Ali Saidi
fe12f38353
PhysicalMemory: Add parameter for variance in memory delay.
...
--HG--
extra : convert_revision : b931472e81dedb650b7accb9061cb426f1c32e66
2008-04-10 14:44:52 -04:00
Ali Saidi
ed27c4c521
SCons: Manually specifying header only directories with Dir() works around the problem
...
--HG--
extra : convert_revision : d9713228d934cf4a45114a972603b8bca2bd27d3
2008-04-08 11:08:26 -04:00
Ali Saidi
1605fbebc8
IGbE: Fix bug that limits wire performance a bit
...
--HG--
extra : convert_revision : 3f93c17f647a6955dab861da211174de856ee02c
2008-03-25 15:58:54 -04:00
Steve Reinhardt
ba1f7d31e0
Automated merge with ssh://daystrom.m5sim.org//repo/m5
...
--HG--
extra : convert_revision : 7922848bb1145bcb2ee07d672d21cfe2dd98fc03
2008-03-25 10:04:52 -04:00
Steve Reinhardt
29be31ce31
Fix handling of writeback-induced writebacks in atomic mode.
...
--HG--
extra : convert_revision : 4fa64f8a929f1aa36a9d5a71b8d1816b497aca4c
2008-03-25 10:01:21 -04:00
Gabe Black
93dd1978a7
X86: Put an RTC into the CMOS part of the southbridge.
...
--HG--
extra : convert_revision : a614373236fe75db6e6181fc152a02b541a131f3
2008-03-25 02:15:23 -04:00
Gabe Black
e5bdae15f3
Devices: Separate out the MC146818 RTC so both Alpha and X86 can use it.
...
--HG--
extra : convert_revision : 1e7f5185654ed0845678c2169c702d3b977159ed
2008-03-25 02:15:06 -04:00
Gabe Black
af9a57566a
X86: Turn #defines into consts.
...
--HG--
extra : convert_revision : c0416de5d88ca39f54494418768e68a93aa4f2aa
2008-03-25 02:09:18 -04:00
Gabe Black
48409ca512
X86: Start implementing the south bridge stuff.
...
--HG--
extra : convert_revision : 92918c05eb3363155d78889bdab17baa8eae9dca
2008-03-25 02:08:54 -04:00
Gabe Black
b0c52885ce
X86: Change the Opteron platform to be the PC platform.
...
--HG--
extra : convert_revision : 2c6ffebbad04a21cef6ba3fbc1803218908a6c37
2008-03-25 02:06:53 -04:00
Steve Reinhardt
623dd7ed3a
Delete the Request for a no-response Packet
...
when the Packet is deleted, since the requester
can't possibly do it.
--HG--
extra : convert_revision : 8571b144ecb3c70efc06d09faa8b3161fb58352d
2008-03-24 01:08:02 -04:00
Steve Reinhardt
93ab43288a
Don't FastAlloc MSHRs since we don't allocate them on the fly.
...
--HG--
extra : convert_revision : 02775cfb460afe6df0df0938c62cccd93a71e775
2008-03-24 01:08:02 -04:00
Steve Reinhardt
627592c2f2
Add FAST_ALLOC_DEBUG and FAST_ALLOC_STATS as SConstruct options.
...
--HG--
extra : convert_revision : 56a7f646f2ac87019c78ba7fa62c5f4bdc00ba44
2008-03-24 01:08:02 -04:00
Steve Reinhardt
407710d387
Fix cache problem with writes to tempBlock
...
getting wrong writeback address.
--HG--
extra : convert_revision : 023dfb69c227c13a69bfe2744c6af75a45828b0b
2008-03-22 22:17:15 -04:00
Gabe Black
3fe1af7952
MIPS: Check endianness of binaries in SE mode.
...
--HG--
extra : convert_revision : e6c4bda6078eb68a26f8834411f744078c6bf5a9
2008-03-20 02:10:21 -04:00
Steve Reinhardt
b051ae6acc
Fix a few Packet memory leaks.
...
--HG--
extra : convert_revision : 00db19f0698c0786f0dff561eea9217860a5a05a
2008-03-17 03:08:28 -04:00
Steve Reinhardt
131c65f429
Restructure bus timing calcs to cope with pkt being deleted by target.
...
--HG--
extra : convert_revision : db8497e73a44f2a06aab121e797e88b4c0c31330
2008-03-17 03:07:38 -04:00
Steve Reinhardt
19c367fa8f
Fix subtle cache bug where read could return stale data
...
if a prior write miss arrived while an even earlier
read miss was still outstanding.
--HG--
extra : convert_revision : 4924e145829b2ecf4610b88d33f4773510c6801a
2008-03-15 05:03:55 -07:00
Gabe Black
50946b1673
Merge
...
--HG--
extra : convert_revision : ec5f41b2007ade15f6f4c4a1533e50f9cba2798e
2008-03-06 21:09:15 -05:00
Gabe Black
a245b0eedf
X86: Refine the local APIC.
...
--HG--
extra : convert_revision : 2789c54ed555fed2f2a333fcc7dc6454f294ebf2
2008-03-06 20:37:28 -05:00
Vilas Sridharan
21fd15ad9a
O3CPU: Don't call dumpInsts if DEBUG is not defined
...
--HG--
extra : convert_revision : 3194bde4c624d118969bfbf92282539963a72245
2008-03-06 00:27:09 -05:00
Gabe Black
66aaabf4ae
X86: Don't map the local APIC into the physical address space in SE mode.
...
--HG--
extra : convert_revision : b7103974b12130bbf43583c4cb5294b808add208
2008-03-01 00:05:12 -05:00
Steve Reinhardt
19dfde2317
Automated merge with ssh://daystrom.m5sim.org//repo/m5
...
--HG--
extra : convert_revision : f4bcd342e7abb86ca83840b723e6ab0b861ecf5b
2008-02-27 18:18:56 -05:00
Korey Sewell
8fb74c238c
Add comments in code to describe bug conditions.
...
This should help if somebody gets to the bug
fix before me (or someone else)...
--HG--
extra : convert_revision : 0ae64c58ef4f7b02996f31e9e9e6bfad344719e2
2008-02-27 17:50:29 -05:00
Korey Sewell
b45cf21a8e
Fix Load/Store Queue squashing after a SMT thread is removed but ensuring
...
you are squashing from the current instruction # causing the thread exit.
--HG--
extra : convert_revision : ccbeece7dd1d5fee43f30ab19370908972113473
2008-02-27 16:53:08 -05:00
Korey Sewell
34715cc691
Fix offset in removeThread() function so that float registers start freeing up
...
from the right point (#32 usually) instead of restarting at 0 and double-freeing.
Commented out assert line in free_list.hh that will check for when double-free condition
goes bad.
--HG--
extra : convert_revision : 08d5f9b6a874736e487d101e85c22aaa67bf59ae
2008-02-27 16:48:33 -05:00
Steve Reinhardt
e6d6adc731
Revamp cache timing access mshr check to make stats sane again.
...
--HG--
extra : convert_revision : 37009b8ee536807073b5a5ca07ed1d097a496aea
2008-02-26 22:03:28 -08:00
Rick Strong
fcfc8b8c4f
Configs: Make using Simpoints easier with some config files that support them easily
...
--HG--
extra : convert_revision : 0f21829306eb68b332f03da410e6c341c8595bdd
2008-02-27 00:35:09 -05:00
Gabe Black
43ecce5fda
X86: Put in initial implementation of the local APIC.
...
--HG--
extra : convert_revision : 1708a93d96b819e64ed456c75dbb5325ac8114a8
2008-02-26 23:39:53 -05:00
Gabe Black
98d2ca403e
X86: Implement the INVLPG instruction and the TIA microop.
...
--HG--
extra : convert_revision : 31db1ee082f6c3ca5443cba1eb335e408661ead2
2008-02-26 23:39:22 -05:00
Gabe Black
8b4796a367
TLB: Make a TLB base class and put a virtual demapPage function in it.
...
--HG--
extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f
2008-02-26 23:38:51 -05:00
Gabe Black
7bde0285e5
X86: Get PCI config space to work, and adjust address space prefix numbering scheme.
...
--HG--
extra : convert_revision : 2b382f478ee8cde3a35aa4c105196f200bc7afa6
2008-02-26 23:38:01 -05:00
Steve Reinhardt
bdf3323915
Cache: better comments particularly regarding writeback situation.
...
--HG--
extra : convert_revision : 59ff9ee63ee0fec5a7dfc27b485b737455ccf362
2008-02-26 20:17:26 -08:00
Gabe Black
ec1a4cbbc7
Bus: Fix the bus timing to be more realistic.
...
--HG--
extra : convert_revision : acd70dc98ab840e55b114706fbb6afb2a95e54bc
2008-02-26 02:20:08 -05:00
Steve Reinhardt
4597a71cef
Make L2+ caches allocate new block for writeback misses
...
instead of forwarding down the line.
--HG--
extra : convert_revision : b0d6e7862c92ea7a2d21f817d30398735e7bb8ba
2008-02-16 14:58:03 -05:00
Ali Saidi
9faec83ac5
CPU: move the PC Events code to a place where the code won't be executed multiple times if an instruction faults.
...
--HG--
extra : convert_revision : 19c8e46a4eea206517be7ed4131ab9df0fe00e68
2008-02-14 16:14:35 -05:00
Ali Saidi
a33a3f7c55
Update copyright dates
...
--HG--
extra : convert_revision : 547e7ddff6b8005a9eaad60970bc51984e84fcd1
2008-02-11 12:35:28 -05:00
Steve Reinhardt
71835d42df
Automated merge with file:/home/stever/hg/m5-orig
...
--HG--
extra : convert_revision : 86a55cd98a9704f756a70aa0cbd2820cf92c821d
2008-02-11 08:31:26 -08:00
Steve Reinhardt
2f7421b12b
EXTRAS now points to src instead of needing 'src' subdir.
...
--HG--
extra : convert_revision : 8e7e4516ace8c7852eeea3c479bfd567839a8061
2008-02-11 08:04:01 -08:00
Nicolas Zea
4c7eb21119
Bus: Only update port cache when there is an item to update it with.
...
--HG--
extra : convert_revision : 84848fd48bb9e6693a0518c862364142b1969aa8
2008-02-10 19:41:03 -05:00
Ali Saidi
d167e2bb97
IGbE: Fix a couple of bugs.
...
--HG--
extra : convert_revision : a1f16bd82b6fbd5b6b5dc0f08b9e69858bea86ca
2008-02-10 19:32:12 -05:00
Steve Reinhardt
9d7a69c582
Fix #include lines for renamed cache files.
...
--HG--
extra : convert_revision : b5008115dc5b34958246608757e69a3fa43b85c5
2008-02-10 14:45:25 -08:00
Steve Reinhardt
d56e77c180
Rename cache files for brevity and consistency with rest of tree.
...
--HG--
rename : src/mem/cache/base_cache.cc => src/mem/cache/base.cc
rename : src/mem/cache/base_cache.hh => src/mem/cache/base.hh
rename : src/mem/cache/cache_blk.cc => src/mem/cache/blk.cc
rename : src/mem/cache/cache_blk.hh => src/mem/cache/blk.hh
rename : src/mem/cache/cache_builder.cc => src/mem/cache/builder.cc
rename : src/mem/cache/miss/mshr.cc => src/mem/cache/mshr.cc
rename : src/mem/cache/miss/mshr.hh => src/mem/cache/mshr.hh
rename : src/mem/cache/miss/mshr_queue.cc => src/mem/cache/mshr_queue.cc
rename : src/mem/cache/miss/mshr_queue.hh => src/mem/cache/mshr_queue.hh
rename : src/mem/cache/prefetch/base_prefetcher.cc => src/mem/cache/prefetch/base.cc
rename : src/mem/cache/prefetch/base_prefetcher.hh => src/mem/cache/prefetch/base.hh
rename : src/mem/cache/prefetch/ghb_prefetcher.cc => src/mem/cache/prefetch/ghb.cc
rename : src/mem/cache/prefetch/ghb_prefetcher.hh => src/mem/cache/prefetch/ghb.hh
rename : src/mem/cache/prefetch/stride_prefetcher.cc => src/mem/cache/prefetch/stride.cc
rename : src/mem/cache/prefetch/stride_prefetcher.hh => src/mem/cache/prefetch/stride.hh
rename : src/mem/cache/prefetch/tagged_prefetcher.cc => src/mem/cache/prefetch/tagged.cc
rename : src/mem/cache/prefetch/tagged_prefetcher.hh => src/mem/cache/prefetch/tagged.hh
rename : src/mem/cache/tags/base_tags.cc => src/mem/cache/tags/base.cc
rename : src/mem/cache/tags/base_tags.hh => src/mem/cache/tags/base.hh
rename : src/mem/cache/tags/Repl.py => src/mem/cache/tags/iic_repl/Repl.py
rename : src/mem/cache/tags/repl/gen.cc => src/mem/cache/tags/iic_repl/gen.cc
rename : src/mem/cache/tags/repl/gen.hh => src/mem/cache/tags/iic_repl/gen.hh
rename : src/mem/cache/tags/repl/repl.hh => src/mem/cache/tags/iic_repl/repl.hh
extra : convert_revision : ff7a35cc155a8d80317563c45cebe405984eac62
2008-02-10 14:15:42 -08:00
Stephen Hines
6cc1573923
Make the Event::description() a const function
...
--HG--
extra : convert_revision : c7768d54d3f78685e93920069f5485083ca989c0
2008-02-06 16:32:40 -05:00
Stephen Hines
0ccf9a2c37
Add base ARM code to M5
...
--HG--
extra : convert_revision : d811bf87d1a0bfc712942ecd3db1b48fc75257af
2008-02-05 23:44:13 -05:00
Steve Reinhardt
b96631e1a0
Cleaned up os.path imports a bit.
...
--HG--
extra : convert_revision : ee75bf9abd249ab053e804739cc50972475cd5b6
2008-02-05 17:43:45 -08:00
Steve Reinhardt
d725ff450d
Make EXTRAS work for SConsopts too.
...
Requires pushing source files down into 'src' subdir relative
to directory listed in EXTRAS.
--HG--
extra : convert_revision : ca04adc3e24c60bd3e7b63ca5770b31333d76729
2008-02-05 17:40:08 -08:00
Gabe Black
ca313e2303
X86: Put an SMBios/DMI table in memory.
...
This is basically just the header right now, but there's an untested
mechanism in place to fill out the table and make sure everything is
updated correctly.
--HG--
extra : convert_revision : c1610c0dfa211b7e0d091a04133695d84f500a1c
2008-01-23 15:28:54 -05:00
Gabe Black
423bbe6499
X86: Optomize the bit scanning instruction microassembly a little. More can be done.
...
--HG--
extra : convert_revision : 3cf6e972f0e41e3529a633ecbb31289e1bd17f0f
2008-01-23 08:18:27 -05:00
Gabe Black
60c2d98fc0
X86: Implement and attach the BSR and BSF instructions.
...
--HG--
extra : convert_revision : be7e11980092e5d1baff0e05d4ec910305966908
2008-01-22 00:10:33 -05:00
Gabe Black
f809637011
X86: Fill out group17 in the decoder.
...
--HG--
extra : convert_revision : 66ab9c0fc3086f66e3d6d82d47964ecf406c3a8a
2008-01-21 16:27:40 -05:00
Gabe Black
657b52fea1
X86: Use the existing boot_osflags instead of duplicating it.
...
--HG--
extra : convert_revision : e04e438d7d261a61c52b946c23cd126ed648814a
2008-01-21 04:32:34 -05:00
Ke Meng
0b6876a0c0
The reason is that the event is supposed to put the instructions ready to execute for next cycle. And the FUCompletion event has a lower priority than CPU tick event. It is called after the iew->tick() for current cycle has already been executed and the issueToExecuteQueue has already advanced this time. And assume the issueToExecuteLatency is 1, to catch up, the increasement should be made at access(-1) instead of access(0). Otherwise I found it could increase the actual op_latency of the instructions to execute by 1 cycle and potentially put the simulated CPU into a permanent idle state.
...
Signed-off by: Ali Saidi <saidi@eecs.umich.edu>
--HG--
extra : convert_revision : dafc16814383e8e8f8320845edf6ab2bcfed1e1d
2008-01-14 11:47:32 -05:00
Gabe Black
c08b7802a9
X86: Redo the bit test instructions.
...
--HG--
extra : convert_revision : 433c2a9f3675ed02f3be5ce759a440f2686d2ccd
2008-01-12 06:41:32 -05:00
Gabe Black
b705eba6e5
X86: Fix the wrmsr instruction.
...
--HG--
extra : convert_revision : 12bc7e71226ebafb8eedadf6a3db82929e15e722
2008-01-12 06:40:55 -05:00
Gabe Black
0ee67d4210
X86: Make the effective segment base shadow the regular one, not the selector.
...
--HG--
extra : convert_revision : 498c7c16d664c784b196885b1f35c3c6386c9cfc
2008-01-12 06:40:10 -05:00
Gabe Black
223e48e6ae
X86: Make the IO ports work using extra physical address lines. Add a serial port.
...
--HG--
extra : convert_revision : a14cb4fc9afedfc0ff58b11a7f8fb5516d462cc6
2008-01-12 06:39:15 -05:00
Gabe Black
0e394fdfa4
X86: Fix the general IO instructions dataSize.
...
--HG--
extra : convert_revision : 9774a52cb6a8e7632d1b1dc0706e5791cc18d238
2008-01-12 06:37:35 -05:00
Geoffrey Blake
f9c54d5a4b
Temporary fix for ll/sc bug see flyspray task for more info:
...
http://www.m5sim.org/flyspray/task/197
Signed-off by: Ali Saidi <saidi@eecs.umich.edu>
--HG--
extra : convert_revision : cdeece7e3163de9abf2c6c7435f1bc93570fab81
2008-01-06 00:19:45 -05:00
Steve Reinhardt
6c5a3ab8b2
Add ReadRespWithInvalidate to handle multi-level coherence situation
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where we defer a response to a read from a far-away cache A, then later
defer a ReadExcl from a cache B on the same bus as us. We'll assert
MemInhibit in both cases, but in the latter case MemInhibit will keep
the invalidation from reaching cache A. This special response tells
cache A that it gets the block to satisfy its read, but must immediately
invalidate it.
--HG--
extra : convert_revision : f85c8b47bb30232da37ac861b50a6539dc81161b
2008-01-02 15:22:38 -08:00
Steve Reinhardt
bf9b3821bd
Mark cache-to-cache MSHRs as downstreamPending when necessary.
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Don't mark upstream MSHR as pending if downstream MSHR is already in service.
--HG--
extra : convert_revision : e1c135ff00217291db58ce8a06ccde34c403d37f
2008-01-02 15:18:33 -08:00
Steve Reinhardt
538da9e24d
Don't DPRINTF in the middle of a PrintReq.
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--HG--
extra : convert_revision : 6358c014d14a19a34111c39827b05987507544bb
2008-01-02 14:42:42 -08:00
Steve Reinhardt
87e5fd1755
Bug fix: functional cache port now needs otherPort set.
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--HG--
extra : convert_revision : fb007df73a77535a5dba19341f7b0b32e8c99548
2008-01-02 14:42:24 -08:00
Steve Reinhardt
cde5a79eab
Additional comments and helper functions for PrintReq.
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--HG--
extra : convert_revision : 7eadf9b7db8c0289480f771271b6efe2400006d4
2008-01-02 13:46:22 -08:00
Steve Reinhardt
3952e41ab1
Add functional PrintReq command for memory-system debugging.
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--HG--
extra : convert_revision : 73b753e57c355b7e6873f047ddc8cb371c3136b7
2008-01-02 12:20:15 -08:00
Steve Reinhardt
659aef3eb8
Fix formatting and comments in cache_impl.hh
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--HG--
extra : convert_revision : 26d71cca5420ad03e16bf174e15dabe7f902da41
2008-01-02 12:15:48 -08:00
Gabe Black
2cb7d4f068
SPARC: Fix a bug where the TLB would match against the wrong entries.
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--HG--
extra : convert_revision : 631b3b6a1416121b54bd9717ca1cdccdd5b8a1eb
2008-01-01 18:20:08 -05:00
Ali Saidi
45ea1549c9
Checkpointing: Fix a bug in the simulation script when restoring without standard switch and change some ifs to work with the default port since every port is now connected to something.
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--HG--
extra : convert_revision : 72507cf13e58465291b0dce6322e853bee5a2b89
2007-12-18 01:52:57 -05:00
Ali Saidi
71909a50de
CPU: Update where the simple cpus read their cpu id from the thread context to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations.
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--HG--
extra : convert_revision : 4f2801967a271b43817d88e147c2f80c4480b2c3
2007-12-16 03:48:13 -05:00
Gabe Black
27cc351688
X86: Please excuse my dear Aunt Sally. (precedence bug)
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--HG--
extra : convert_revision : 9ad4f31e7a962c3177896bcbfb93e2e54720d117
2007-12-03 14:32:56 -08:00
Gabe Black
73caca57a8
X86: Make sure the memory index is calculated using the address size for bit test instructions.
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--HG--
extra : convert_revision : 9634675857dae53b5e79e49267c864a0265afde1
2007-12-02 01:46:38 -08:00
Gabe Black
b5d4018382
X86: Fix a copy/paste mistake where the bit test instructions were using an immediate where they should use a register.
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--HG--
extra : convert_revision : b0ee80e4c7fdb58a1eb85b3bcc82a0cdaa93330a
2007-12-02 01:46:29 -08:00
Gabe Black
62ad1d2872
X86: Make the page not present panic more descriptive.
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--HG--
extra : convert_revision : 9360e47adb61e164ac218f2ea231eaa60bf3229d
2007-12-02 01:46:14 -08:00
Gabe Black
82e705d713
X86: Start setting up the real mode data structure.
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--HG--
extra : convert_revision : ba6d4939d4d58da5586655c83f1617f47dc7e359
2007-12-02 00:04:31 -08:00
Gabe Black
5de71e39d8
X86: Make the 0xA0-0xA3 versions of mov use the right sized immediates.
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--HG--
extra : convert_revision : a702403de29772618abb5bd5c5555279d91bdd59
2007-12-02 00:02:51 -08:00
Gabe Black
4c37f828f1
X86: Add in a missing "break".
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--HG--
extra : convert_revision : 2e48d8b0292bc3b78e4caa27dec20113d40e7d74
2007-12-01 23:11:23 -08:00
Gabe Black
9805916cec
X86: Actually do something for the MiscRegFile clear function.
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--HG--
extra : convert_revision : 36f8abaa9d09700d8ba9e09b4a10fa4dce580f36
2007-12-01 23:10:42 -08:00
Gabe Black
42ae409746
X86: Move startup code to the system object to initialize a Linux system.
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--HG--
extra : convert_revision : a4796c79f41aa8b8f38bf2f628bee8f1b3af64be
2007-12-01 23:09:56 -08:00
Gabe Black
e7fc5c42f3
X86: Add a missing microcode file to the sconscript.
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--HG--
extra : convert_revision : 6da8a67e07bada169abf7f10aded8a90d4e63eae
2007-12-01 23:07:41 -08:00
Gabe Black
67fee01026
X86: Fix a copy paste error in the bts microcode.
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--HG--
extra : convert_revision : c4ac007d35ac13211f9816f1104c84f2b447ddba
2007-12-01 23:06:52 -08:00
Gabe Black
988c6f227a
X86: Implement mov from control register.
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--HG--
extra : convert_revision : c8280f0686a3ae6d5c405327540ad15a3a5531f9
2007-12-01 23:06:03 -08:00
Gabe Black
fe833dd2c3
X86: First crack at far returns. This is grossly approximate.
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--HG--
extra : convert_revision : 23da0338af1f7663ae5ddf2289fb45dd32f37c42
2007-12-01 23:05:01 -08:00
Gabe Black
dc6f960171
X86: Reorganize segmentation and implement segment selector movs.
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--HG--
extra : convert_revision : 553c3ffeda1f5312cf02493f602e7d4ba2fe66e8
2007-12-01 23:03:39 -08:00
Gabe Black
a548067b01
X86: Make the "fault" microop predicated.
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--HG--
extra : convert_revision : ded34133afcd6af1f55b8991b82bad45258069d3
2007-12-01 23:01:56 -08:00
Gabe Black
557bc80647
X86: Implement the LIDT instruction.
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--HG--
extra : convert_revision : 380515e985318311632e00b13000585afb052e3b
2007-12-01 23:01:31 -08:00
Gabe Black
62c79ca637
X86: Implement the lgdt instruction.
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--HG--
extra : convert_revision : d1698a82df3c57cc9bbf8d5d190f271bfc7cb2e4
2007-12-01 23:01:17 -08:00
Gabe Black
4e3ff42762
X86: Implement wrbase and wrlimit for loading pseudo descriptors.
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--HG--
extra : convert_revision : fe03c4aed95ef12773e80cdb3d9cff68a2b20f02
2007-12-01 23:00:58 -08:00
Gabe Black
bfc62d1a70
X86: Separate the effective seg base and the "hidden" seg base.
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--HG--
extra : convert_revision : 5fcb8d94dbab7a7d6fe797277a5856903c885ad4
2007-12-01 23:00:15 -08:00
Gabe Black
7433032b39
SPARC: Fixes for invalidateAll and demapAll in the SPARC TLBs.
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--HG--
extra : convert_revision : 8de6c60b0e3e725eac11047a9d9888097dd359ff
2007-11-30 16:49:27 -08:00
Gabe Black
38e804f7cd
SPARC: Fix 32 bit register window flushing endian conversion.
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--HG--
extra : convert_revision : be91d6fecb44a85e983343704a098b456948af8a
2007-11-29 20:20:18 -08:00
Gabe Black
fa5e3b47c8
SPARC: Fix the initial stack to match what the Linux kernel does.
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--HG--
extra : convert_revision : a4451710d8463e52227fd8f760ab737ea8f404b5
2007-11-29 00:00:26 -08:00
Gabe Black
16e99e4677
SPARC: Combine the 64 and 32 bit process initialization code.
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Alignment is done as it was for 32 bit processes.
--HG--
extra : convert_revision : 9368ad40dcc7911f8fc7ec1468c6a28aa92d196f
2007-11-29 00:00:02 -08:00
Ali Saidi
a84d9716d6
merge, no manual changes
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--HG--
extra : convert_revision : 6d6b744bbdfb09e7c3092368870a4f372241f9e8
2007-11-29 00:23:14 -05:00
Rick Strong
376c7285ee
Serialization: Fix serialization of file descriptors. Make sure open
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file descriptors are reopened and the file pointer is in the same
place as when the checkpoint occured.
Signed-off by: Ali Saidi
--HG--
extra : convert_revision : d9d2cd388c9c02f60e1269d6845891c35f94fc47
2007-11-29 00:22:46 -05:00
Gabe Black
8a020d40d3
Make ports that aren't connected to anything fail more gracefully.
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--HG--
extra : convert_revision : 3803b28fb2fdfd729f01f1a44df2ae02ef83a2fc
2007-11-28 14:39:19 -08:00
Gabe Black
ab598eadbf
imported patch pagewalker.patch
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--HG--
extra : convert_revision : 8ddde313f2249e1346fa51372a156f0d2ddc3b8f
2007-11-21 00:04:15 -08:00
Gabe Black
ce26c3ccec
Get rid of a file that should have never been committed.
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--HG--
extra : convert_revision : c0e678ce0ce0301bb3afff8bef4fcab7aef3c6fe
2007-11-20 22:51:03 -08:00
