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ARM: Implement the shadow registers using register flattening.

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This commit is contained in:
Gabe Black 2009-11-08 00:07:49 -08:00
parent 4a454c4f47
commit a2b76516c4
1 changed files with 41 additions and 2 deletions
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43
src/arch/arm/isa.hh
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@ -44,14 +44,44 @@ namespace ArmISA
{
protected:
MiscReg miscRegs[NumMiscRegs];
const IntRegIndex *intRegMap;
void
updateRegMap(CPSR cpsr)
{
switch (cpsr.mode) {
case MODE_USER:
case MODE_SYSTEM:
intRegMap = IntRegUsrMap;
break;
case MODE_FIQ:
intRegMap = IntRegFiqMap;
break;
case MODE_IRQ:
intRegMap = IntRegIrqMap;
break;
case MODE_SVC:
intRegMap = IntRegSvcMap;
break;
case MODE_ABORT:
intRegMap = IntRegAbtMap;
break;
case MODE_UNDEFINED:
intRegMap = IntRegUndMap;
break;
default:
panic("Unrecognized mode setting in CPSR.\n");
}
}
public:
void clear()
{
memset(miscRegs, 0, sizeof(miscRegs));
CPSR cpsr = 0;
cpsr.mode = MODE_USER;
cpsr.mode = MODE_SYSTEM;
miscRegs[MISCREG_CPSR] = cpsr;
updateRegMap(cpsr);
//XXX We need to initialize the rest of the state.
}
@ -79,6 +109,9 @@ namespace ArmISA
void
setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
{
if (misc_reg == MISCREG_CPSR) {
updateRegMap(val);
}
assert(misc_reg < NumMiscRegs);
miscRegs[misc_reg] = val;
}
@ -86,7 +119,13 @@ namespace ArmISA
int
flattenIntIndex(int reg)
{
return reg;
assert(reg >= 0);
if (reg < NUM_ARCH_INTREGS) {
return intRegMap[reg];
} else {
assert(reg < NUM_INTREGS);
return reg;
}
}
int