ruby: removed last level cache support
Removed the last level cache support and MOESI_hammer's dependency on it. Replaces the LLC support with the more generic MachineType count.
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@ -379,7 +379,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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out_msg.Requestor := machineID;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.MessageSize := MessageSizeType:Request_Control;
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TBEs[address].NumPendingMsgs := getNumberOfLastLevelCaches(); // One from each other cache (n-1) plus the memory (+1)
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TBEs[address].NumPendingMsgs := machineCount(MachineType:L1Cache); // One from each other cache (n-1) plus the memory (+1)
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}
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}
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@ -390,7 +390,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
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out_msg.Requestor := machineID;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.MessageSize := MessageSizeType:Request_Control;
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TBEs[address].NumPendingMsgs := getNumberOfLastLevelCaches(); // One from each other cache (n-1) plus the memory (+1)
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TBEs[address].NumPendingMsgs := machineCount(MachineType:L1Cache); // One from each other cache (n-1) plus the memory (+1)
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}
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}
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@ -320,7 +320,7 @@ machine(Directory, "AMD Hammer-like protocol")
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//
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// One ack for each last-level cache
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//
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TBEs[address].NumPendingMsgs := getNumberOfLastLevelCaches();
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TBEs[address].NumPendingMsgs := machineCount(MachineType:L1Cache);
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//
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// Assume initially that the caches store a clean copy and that memory
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// will provide the data
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@ -468,7 +468,7 @@ machine(Directory, "AMD Hammer-like protocol")
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}
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action(f_forwardRequest, "f", desc="Forward requests") {
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if (getNumberOfLastLevelCaches() > 1) {
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if (machineCount(MachineType:L1Cache) > 1) {
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peek(requestQueue_in, RequestMsg) {
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enqueue(forwardNetwork_out, RequestMsg, latency=memory_controller_latency) {
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out_msg.Address := address;
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@ -29,7 +29,7 @@
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// Mapping functions
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int getNumberOfLastLevelCaches();
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int machineCount(MachineType machType);
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// NodeID map_address_to_node(Address addr);
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MachineID mapAddressToRange(Address addr, MachineType type, int low, int high);
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@ -31,8 +31,4 @@
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#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
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#include "mem/ruby/system/CacheMemory.hh"
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int getNumberOfLastLevelCaches()
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{
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return CacheMemory::numberOfLastLevelCaches();
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}
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@ -42,6 +42,7 @@
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#include "mem/ruby/common/NetDest.hh"
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#include "mem/protocol/GenericMachineType.hh"
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#include "mem/ruby/system/DirectoryMemory.hh"
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#include "mem/protocol/MachineType.hh"
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#ifdef MACHINETYPE_L1Cache
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#define MACHINETYPE_L1CACHE_ENUM MachineType_L1Cache
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@ -67,9 +68,6 @@
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#define MACHINETYPE_DMA_ENUM MachineType_NUM
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#endif
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// used to determine the number of acks to wait for
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int getNumberOfLastLevelCaches();
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// used to determine the home directory
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// returns a value between 0 and total_directories_within_the_system
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inline
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@ -152,5 +150,8 @@ extern inline GenericMachineType ConvertMachToGenericMach(MachineType machType)
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}
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}
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extern inline int machineCount(MachineType machType) {
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return MachineType_base_count(machType);
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}
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#endif // COMPONENTMAPPINGFNS_H
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@ -28,9 +28,6 @@
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#include "mem/ruby/system/CacheMemory.hh"
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int CacheMemory::m_num_last_level_caches = 0;
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MachineType CacheMemory::m_last_level_machine_type = MachineType_FIRST;
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// ******************* Definitions *******************
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// Output operator definition
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@ -75,19 +72,6 @@ void CacheMemory::init()
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else
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assert(false);
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m_num_last_level_caches =
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MachineType_base_count(MachineType_FIRST);
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#if 0
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for (uint32 i=0; i<argv.size(); i+=2) {
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if (m_last_level_machine_type < m_controller->getMachineType()) {
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m_num_last_level_caches =
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MachineType_base_count(m_controller->getMachineType());
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m_last_level_machine_type =
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m_controller->getMachineType();
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}
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}
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#endif
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m_cache.setSize(m_cache_num_sets);
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m_locked.setSize(m_cache_num_sets);
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for (int i = 0; i < m_cache_num_sets; i++) {
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@ -112,13 +96,6 @@ CacheMemory::~CacheMemory()
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}
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}
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int
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CacheMemory::numberOfLastLevelCaches()
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{
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return m_num_last_level_caches;
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}
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void CacheMemory::printConfig(ostream& out)
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{
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out << "Cache config: " << m_cache_name << endl;
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@ -106,8 +106,6 @@ public:
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AccessPermission getPermission(const Address& address) const;
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void changePermission(const Address& address, AccessPermission new_perm);
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static int numberOfLastLevelCaches();
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int getLatency() const { return m_latency; }
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// Hook for checkpointing the contents of the cache
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@ -172,12 +170,6 @@ private:
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int m_cache_num_sets;
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int m_cache_num_set_bits;
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int m_cache_assoc;
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static Vector< CacheMemory* > m_all_caches;
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static int m_num_last_level_caches;
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static MachineType m_last_level_machine_type;
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};
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#endif //CACHEMEMORY_H
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