ARM: Hook the external data processing instructions into the Thumb decoder.
This commit is contained in:
Gabe Black
parent
beb759912b
commit
b66e3aec43
2 changed files with 441 additions and 221 deletions
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@ -43,98 +43,18 @@
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1: decode BIGTHUMB {
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// 16 bit thumb instructions.
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0: decode TOPCODE_15_13 {
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0x0, 0x1: decode TOPCODE_13_11 {
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0x0: WarnUnimpl::lsl(); //immediate
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0x1: WarnUnimpl::lsr(); //immediate
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0x2: WarnUnimpl::asr(); //immediate
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0x3: decode TOPCODE_10_9 {
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0x0: WarnUnimpl::add(); //register
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0x1: WarnUnimpl::sub(); //register
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0x2: WarnUnimpl::add(); //3 bit immediate
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0x3: WarnUnimpl::sub(); //3 bit immediate
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}
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0x4: WarnUnimpl::mov(); //immediate
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0x5: WarnUnimpl::cmp(); //immediate
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0x6: WarnUnimpl::add(); //8 bit immediate, thumb
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0x7: WarnUnimpl::sub(); //8 bit immediate, thumb
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}
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0x0, 0x1: Thumb16ShiftAddSubMoveCmp::thumb16ShiftAddMoveCmp();
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0x2: decode TOPCODE_12_10 {
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// Data processing
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0x0: decode TOPCODE_9_6 {
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0x0: WarnUnimpl::and(); //register
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0x1: WarnUnimpl::eor(); //register
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0x2: WarnUnimpl::lsl(); //register
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0x3: WarnUnimpl::lsr(); //register
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0x4: WarnUnimpl::asr(); //register
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0x5: WarnUnimpl::adc(); //register
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0x6: WarnUnimpl::sbc(); //register
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0x7: WarnUnimpl::ror(); //register
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0x8: WarnUnimpl::tst(); //register
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0x9: WarnUnimpl::rsb(); //immediate
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0xa: WarnUnimpl::cmp(); //register (high registers)
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0xb: WarnUnimpl::cmn(); //register
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0xc: WarnUnimpl::orr(); //register
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0xd: WarnUnimpl::mul();
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0xe: WarnUnimpl::bic(); //register
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0xf: WarnUnimpl::mvn(); //register
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}
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// Special data instructions and branch and exchange
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0x1: decode TOPCODE_9_6 {
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0x0: WarnUnimpl::add(); //register (low registers)
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0x1, 0x2, 0x3: WarnUnimpl::add(); //register (high registers)
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0x4: WarnUnimpl::unpredictable(); //?
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0x5, 0x6, 0x7: WarnUnimpl::cmp(); //register
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0x8: WarnUnimpl::mov(); //register (low registers)
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0x9, 0xa, 0xb: WarnUnimpl::mov(); //register (high registers)
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0xc, 0xd: WarnUnimpl::bx();
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0xe, 0xf: WarnUnimpl::blx(); //register
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}
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0x0: Thumb16DataProcessing::thumb16DataProcessing();
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0x1: Thumb16SpecDataAndBx::thumb16SpecDataAndBx();
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0x2, 0x3: Thumb16MemLit::thumb16MemLit();
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default: Thumb16MemReg::thumb16MemReg();
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}
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0x3, 0x4: Thumb16MemImm::thumb16MemImm();
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0x5: decode TOPCODE_12_11 {
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0x0: WarnUnimpl::adr();
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0x1: WarnUnimpl::add(); //sp, immediate
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0x2: decode TOPCODE_10_8 {
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0x0: decode TOPCODE_7 {
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0x0: WarnUnimpl::add(); //sp, immediate
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0x1: WarnUnimpl::sub(); //sp, immediate
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}
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0x1, 0x3: WarnUnimpl::cbz(); //cbnz too...
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0x2: decode TOPCODE_7_6 {
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0x0: WarnUnimpl::sxth();
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0x1: WarnUnimpl::sxtb();
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0x2: WarnUnimpl::uxth();
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0x3: WarnUnimpl::uxtb();
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}
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0x4, 0x5: WarnUnimpl::pop();
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0x6: decode TOPCODE_7_5 {
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0x2: WarnUnimpl::setend();
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0x3: WarnUnimpl::cps();
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}
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}
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0x3: decode TOPCODE_10_8 {
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0x1, 0x3: WarnUnimpl::cbz(); //cbnz too...
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0x2: decode TOPCODE_7_6 {
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0x0: WarnUnimpl::rev();
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0x1: WarnUnimpl::rev16();
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0x3: WarnUnimpl::revsh();
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}
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0x4, 0x5: WarnUnimpl::pop();
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0x6: WarnUnimpl::bkpt();
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0x7: decode TOPCODE_3_0 {
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0x0: WarnUnimpl::it();
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default: decode TOPCODE_7_4 {
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0x0: WarnUnimpl::nop();
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0x1: WarnUnimpl::yield();
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0x2: WarnUnimpl::wfe();
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0x3: WarnUnimpl::wfi();
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0x4: WarnUnimpl::sev();
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default: WarnUnimpl::unallocated_hint();
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}
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}
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}
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0x0: Thumb16Adr::thumb16Adr();
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0x1: Thumb16AddSp::thumb16AddSp(); //sp, immediate
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0x2, 0x3: Thumb16Misc::thumb16Misc();
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}
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0x6: decode TOPCODE_12_11 {
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0x0, 0x1: Thumb16MacroMem::thumb16MacroMem();
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@ -197,45 +117,7 @@
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}
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}
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}
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0x1: decode HTOPCODE_8_5 {
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0x0: decode LTRD {
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0xf: decode HTS {
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0x1: WarnUnimpl::tst(); // register
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}
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default: WarnUnimpl::and(); // register
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}
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0x1: WarnUnimpl::bic(); // register
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0x2: decode HTRN {
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0xf: WarnUnimpl::mov(); // register
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default: WarnUnimpl::orr(); // register
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}
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0x3: decode HTRN {
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0xf: WarnUnimpl::mvn(); // register
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default: WarnUnimpl::orn(); // register
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}
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0x4: decode LTRD {
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0xf: decode HTS {
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0x1: WarnUnimpl::teq(); // register
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}
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default: WarnUnimpl::eor(); // register
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}
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0x6: WarnUnimpl::pkh();
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0x8: decode LTRD {
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0xf: decode HTS {
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0x1: WarnUnimpl::cmn(); // register
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}
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default: WarnUnimpl::add(); // register
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}
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0xa: WarnUnimpl::adc(); // register
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0xb: WarnUnimpl::sbc(); // register
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0xd: decode LTRD {
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0xf: decode HTS {
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0x1: WarnUnimpl::cmp(); // register
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}
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default: WarnUnimpl::sub(); // register
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}
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0xe: WarnUnimpl::rsb(); // register
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}
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0x1: Thumb32DataProcShiftReg::thumb32DataProcShiftReg();
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default: decode HTOPCODE_9_8 {
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0x2: decode LTOPCODE_4 {
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0x0: decode LTCOPROC {
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@ -280,76 +162,7 @@
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}
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0x2: decode LTOPCODE_15 {
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0x0: decode HTOPCODE_9 {
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0x0: decode HTOPCODE_8_5 {
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0x0: decode LTRD {
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0xf: decode HTS {
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0x1: DataModImmOp::tst({{
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resTemp = Rn & rotated_imm;
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}});
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}
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default: DataModImmOp::and({{
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Rs = resTemp = Rn & rotated_imm;
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}});
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}
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0x1: DataModImmOp::bic({{
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Rs = resTemp = Rn & ~rotated_imm;
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}});
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0x2: decode HTRN {
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0xf: DataModImmOp::mov({{
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Rs = resTemp = rotated_imm;
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}});
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default: DataModImmOp::orr({{
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Rs = resTemp = Rn | rotated_imm;
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}});
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}
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0x3: decode HTRN {
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0xf: DataModImmOp::mvn({{
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Rs = resTemp = ~rotated_imm;
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}});
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default: DataModImmOp::orn({{
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Rs = resTemp = Rn | ~rotated_imm;
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}});
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}
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0x4: decode LTRD {
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0xf: decode HTS {
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0x1: DataModImmOp::teq({{
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resTemp = Rn ^ rotated_imm;
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}});
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}
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default: DataModImmOp::eor({{
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Rs = resTemp = Rn ^ rotated_imm;
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}});
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}
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0x8: decode LTRD {
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0xf: decode HTS {
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0x1: DataModImmOp::cmn({{
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resTemp = Rn + rotated_imm;
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}}, add);
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}
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default: DataModImmOp::add({{
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Rs = resTemp = Rn + rotated_imm;
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}}, add);
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}
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0xa: DataModImmOp::adc({{
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Rs = resTemp = Rn + rotated_imm + CondCodes<29:>;
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}}, add);
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0xb: DataModImmOp::sbc({{
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Rs = resTemp = Rn - rotated_imm - !CondCodes<29:>;
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}}, sub);
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0xd: decode LTRD {
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0xf: decode HTS {
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0x1: DataModImmOp::cmp({{
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resTemp = Rn - rotated_imm;
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}}, sub);
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}
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default: DataModImmOp::sub({{
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Rs = resTemp = Rn - rotated_imm;
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}}, sub);
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}
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0xe: DataModImmOp::rsb({{
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Rs = resTemp = rotated_imm - Rn;
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}}, rsb);
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}
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0x0: Thumb32DataProcModImm::thumb32DataProcModImm();
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0x1: WarnUnimpl::Data_processing_plain_binary_immediate();
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}
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0x1: WarnUnimpl::Branches_and_miscellaneous_control();
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@ -40,28 +40,30 @@ def format ArmDataProcReg() {{
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case %(opcode)#x:
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if (immShift) {
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if (setCc) {
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return new %(className)sDRegCc(machInst,
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rd, rn, rm, imm5, type);
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return new %(className)sDRegCc(machInst, %(dest)s, %(op1)s,
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rm, imm5, type);
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} else {
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return new %(className)sDReg(machInst,
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rd, rn, rm, imm5, type);
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return new %(className)sDReg(machInst, %(dest)s, %(op1)s,
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rm, imm5, type);
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}
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} else {
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if (setCc) {
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return new %(className)sDRegRegCc(machInst,
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rd, rn, rm, rs, type);
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return new %(className)sDRegRegCc(machInst, %(dest)s,
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%(op1)s, rm, rs, type);
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} else {
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return new %(className)sDRegReg(machInst,
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rd, rn, rm, rs, type);
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return new %(className)sDRegReg(machInst, %(dest)s,
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%(op1)s, rm, rs, type);
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}
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}
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break;
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'''
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def instCode(opcode, mnem):
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def instCode(opcode, mnem, dest="rd", op1="rn"):
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global instDecode
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return instDecode % { "className": mnem.capitalize(),
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"opcode": opcode }
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"opcode": opcode,
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"dest": dest,
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"op1": op1 }
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decode_block = '''
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{
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@ -83,14 +85,14 @@ def format ArmDataProcReg() {{
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decode_block += instCode(0x5, "adc")
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decode_block += instCode(0x6, "sbc")
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decode_block += instCode(0x7, "rsc")
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decode_block += instCode(0x8, "tst")
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decode_block += instCode(0x9, "teq")
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decode_block += instCode(0xa, "cmp")
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decode_block += instCode(0xb, "cmn")
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decode_block += instCode(0x8, "tst", dest="INTREG_ZERO")
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decode_block += instCode(0x9, "teq", dest="INTREG_ZERO")
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decode_block += instCode(0xa, "cmp", dest="INTREG_ZERO")
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decode_block += instCode(0xb, "cmn", dest="INTREG_ZERO")
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decode_block += instCode(0xc, "orr")
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decode_block += instCode(0xd, "mov")
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decode_block += instCode(0xd, "mov", op1="INTREG_ZERO")
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decode_block += instCode(0xe, "bic")
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decode_block += instCode(0xf, "mvn")
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decode_block += instCode(0xf, "mvn", op1="INTREG_ZERO")
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decode_block += '''
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default:
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return new Unknown(machInst);
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@ -103,17 +105,21 @@ def format ArmDataProcImm() {{
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instDecode = '''
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case %(opcode)#x:
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if (setCc) {
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return new %(className)sDImmCc(machInst, rd, rn, imm, rotC);
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return new %(className)sDImmCc(machInst, %(dest)s, %(op1)s,
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imm, rotC);
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} else {
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return new %(className)sDImm(machInst, rd, rn, imm, rotC);
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return new %(className)sDImm(machInst, %(dest)s, %(op1)s,
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imm, rotC);
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}
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break;
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'''
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def instCode(opcode, mnem):
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def instCode(opcode, mnem, dest="rd", op1="rn"):
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global instDecode
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return instDecode % { "className": mnem.capitalize(),
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"opcode": opcode }
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"opcode": opcode,
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"dest": dest,
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"op1": op1 }
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decode_block = '''
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{
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@ -134,14 +140,14 @@ def format ArmDataProcImm() {{
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decode_block += instCode(0x5, "adc")
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decode_block += instCode(0x6, "sbc")
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decode_block += instCode(0x7, "rsc")
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decode_block += instCode(0x8, "tst")
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decode_block += instCode(0x9, "teq")
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decode_block += instCode(0xa, "cmp")
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decode_block += instCode(0xb, "cmn")
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decode_block += instCode(0x8, "tst", dest="INTREG_ZERO")
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decode_block += instCode(0x9, "teq", dest="INTREG_ZERO")
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decode_block += instCode(0xa, "cmp", dest="INTREG_ZERO")
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decode_block += instCode(0xb, "cmn", dest="INTREG_ZERO")
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decode_block += instCode(0xc, "orr")
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decode_block += instCode(0xd, "mov")
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decode_block += instCode(0xd, "mov", op1="INTREG_ZERO")
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decode_block += instCode(0xe, "bic")
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decode_block += instCode(0xf, "mvn")
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decode_block += instCode(0xf, "mvn", op1="INTREG_ZERO")
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decode_block += '''
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default:
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return new Unknown(machInst);
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@ -149,3 +155,404 @@ def format ArmDataProcImm() {{
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}
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'''
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}};
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def format Thumb16ShiftAddSubMoveCmp() {{
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decode_block = '''
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{
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const uint32_t imm5 = bits(machInst, 10, 6);
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const uint32_t imm3 = bits(machInst, 8, 6);
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const uint32_t imm8 = bits(machInst, 7, 0);
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const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
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const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
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const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
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const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6);
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switch (bits(machInst, 13, 11)) {
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case 0x0: // lsl
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return new MovDReg(machInst, rd, INTREG_ZERO, rn, imm5, LSL);
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case 0x1: // lsr
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return new MovDReg(machInst, rd, INTREG_ZERO, rn, imm5, LSR);
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case 0x2: // asr
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return new MovDReg(machInst, rd, INTREG_ZERO, rn, imm5, ASR);
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case 0x3:
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switch (bits(machInst, 10, 9)) {
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case 0x0:
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return new AddDReg(machInst, rd, rn, rm, 0, LSL);
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case 0x1:
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return new SubDReg(machInst, rd, rn, rm, 0, LSL);
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case 0x2:
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return new AddDImm(machInst, rd, rn, imm3, true);
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case 0x3:
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return new SubDImm(machInst, rd, rn, imm3, true);
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}
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case 0x4:
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return new MovDImm(machInst, rd8, INTREG_ZERO, imm8, true);
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case 0x5:
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return new CmpDImmCc(machInst, INTREG_ZERO, rd8, imm8, true);
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case 0x6:
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return new AddDImm(machInst, rd8, rd8, imm8, true);
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case 0x7:
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return new SubDImm(machInst, rd8, rd8, imm8, true);
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}
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}
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'''
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}};
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def format Thumb16DataProcessing() {{
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decode_block = '''
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{
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const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
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const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
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switch (bits(machInst, 9, 6)) {
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case 0x0:
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return new AndDReg(machInst, rdn, rdn, rm, 0, LSL);
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case 0x1:
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return new EorDReg(machInst, rdn, rdn, rm, 0, LSL);
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case 0x2: //lsl
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return new MovDRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, LSL);
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case 0x3: //lsr
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return new MovDRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, LSR);
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case 0x4: //asr
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return new MovDRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, ASR);
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case 0x5:
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return new AdcDReg(machInst, rdn, rdn, rm, 0, LSL);
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case 0x6:
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return new SbcDReg(machInst, rdn, rdn, rm, 0, LSL);
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case 0x7: // ror
|
||||
return new MovDRegReg(machInst, rdn, INTREG_ZERO, rdn, rm, ROR);
|
||||
case 0x8:
|
||||
return new TstDReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
|
||||
case 0x9:
|
||||
return new RsbDImm(machInst, rdn, rm, 0, true);
|
||||
case 0xa:
|
||||
return new CmpDReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
|
||||
case 0xb:
|
||||
return new CmnDReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
|
||||
case 0xc:
|
||||
return new OrrDReg(machInst, rdn, rdn, rm, 0, LSL);
|
||||
case 0xd:
|
||||
//XXX Implement me!
|
||||
return new WarnUnimplemented("mul", machInst);
|
||||
case 0xe:
|
||||
return new BicDReg(machInst, rdn, rdn, rm, 0, LSL);
|
||||
case 0xf:
|
||||
return new MvnDReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
|
||||
}
|
||||
}
|
||||
'''
|
||||
}};
|
||||
|
||||
def format Thumb16SpecDataAndBx() {{
|
||||
decode_block = '''
|
||||
{
|
||||
const IntRegIndex rdn =
|
||||
(IntRegIndex)(uint32_t)(bits(machInst, 2, 0) |
|
||||
(bits(machInst, 7) << 3));
|
||||
const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3);
|
||||
switch (bits(machInst, 9, 8)) {
|
||||
case 0x0:
|
||||
return new AddDReg(machInst, rdn, rdn, rm, 0, LSL);
|
||||
case 0x1:
|
||||
return new CmpDReg(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
|
||||
case 0x2:
|
||||
return new MovDReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
|
||||
case 0x3:
|
||||
if (bits(machInst, 7) == 0)
|
||||
return new WarnUnimplemented("bx", machInst);
|
||||
else
|
||||
// The register version.
|
||||
return new WarnUnimplemented("blx", machInst);
|
||||
}
|
||||
}
|
||||
'''
|
||||
}};
|
||||
|
||||
def format Thumb16Adr() {{
|
||||
decode_block = '''
|
||||
{
|
||||
const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
|
||||
const uint32_t imm8 = bits(machInst, 7, 0) << 2;
|
||||
return new AddDImm(machInst, rd, INTREG_PC, imm8, true);
|
||||
}
|
||||
'''
|
||||
}};
|
||||
|
||||
def format Thumb16AddSp() {{
|
||||
decode_block = '''
|
||||
{
|
||||
const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
|
||||
const uint32_t imm8 = bits(machInst, 7, 0) << 2;
|
||||
return new AddDImm(machInst, rd, INTREG_SP, imm8, true);
|
||||
}
|
||||
'''
|
||||
}};
|
||||
|
||||
def format Thumb16Misc() {{
|
||||
decode_block = '''
|
||||
{
|
||||
switch (bits(machInst, 11, 8)) {
|
||||
case 0x0:
|
||||
if (bits(machInst, 7)) {
|
||||
return new SubDImm(machInst, INTREG_SP, INTREG_SP,
|
||||
bits(machInst, 6, 0) << 2, true);
|
||||
} else {
|
||||
return new AddDImm(machInst, INTREG_SP, INTREG_SP,
|
||||
bits(machInst, 6, 0) << 2, true);
|
||||
}
|
||||
case 0x1:
|
||||
return new WarnUnimplemented("cbz", machInst);
|
||||
case 0x2:
|
||||
switch (bits(machInst, 7, 6)) {
|
||||
case 0x0:
|
||||
return new WarnUnimplemented("sxth", machInst);
|
||||
case 0x1:
|
||||
return new WarnUnimplemented("sxtb", machInst);
|
||||
case 0x2:
|
||||
return new WarnUnimplemented("uxth", machInst);
|
||||
case 0x3:
|
||||
return new WarnUnimplemented("uxtb", machInst);
|
||||
}
|
||||
case 0x3:
|
||||
return new WarnUnimplemented("cbnz", machInst);
|
||||
case 0x4:
|
||||
case 0x5:
|
||||
return new WarnUnimplemented("push", machInst);
|
||||
case 0x6:
|
||||
{
|
||||
const uint32_t opBits = bits(machInst, 7, 5);
|
||||
if (opBits == 2) {
|
||||
return new WarnUnimplemented("setend", machInst);
|
||||
} else if (opBits == 3) {
|
||||
return new WarnUnimplemented("cps", machInst);
|
||||
}
|
||||
}
|
||||
case 0x9:
|
||||
return new WarnUnimplemented("cbz", machInst);
|
||||
case 0xa:
|
||||
switch (bits(machInst, 7, 5)) {
|
||||
case 0x0:
|
||||
return new WarnUnimplemented("rev", machInst);
|
||||
case 0x1:
|
||||
return new WarnUnimplemented("rev16", machInst);
|
||||
case 0x3:
|
||||
return new WarnUnimplemented("revsh", machInst);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 0xb:
|
||||
return new WarnUnimplemented("cbnz", machInst);
|
||||
case 0xc:
|
||||
case 0xd:
|
||||
return new WarnUnimplemented("pop", machInst);
|
||||
case 0xe:
|
||||
return new WarnUnimplemented("bkpt", machInst);
|
||||
case 0xf:
|
||||
if (bits(machInst, 3, 0) != 0)
|
||||
return new WarnUnimplemented("it", machInst);
|
||||
switch (bits(machInst, 7, 4)) {
|
||||
case 0x0:
|
||||
return new WarnUnimplemented("nop", machInst);
|
||||
case 0x1:
|
||||
return new WarnUnimplemented("yield", machInst);
|
||||
case 0x2:
|
||||
return new WarnUnimplemented("wfe", machInst);
|
||||
case 0x3:
|
||||
return new WarnUnimplemented("wfi", machInst);
|
||||
case 0x4:
|
||||
return new WarnUnimplemented("sev", machInst);
|
||||
default:
|
||||
return new WarnUnimplemented("unallocated_hint", machInst);
|
||||
}
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return new Unknown(machInst);
|
||||
}
|
||||
'''
|
||||
}};
|
||||
|
||||
def format Thumb32DataProcModImm() {{
|
||||
|
||||
def decInst(mnem, dest="rd", op1="rn"):
|
||||
return '''
|
||||
if (s) {
|
||||
return new %(mnem)sDImmCc(machInst, %(dest)s,
|
||||
%(op1)s, imm, true);
|
||||
} else {
|
||||
return new %(mnem)sDImm(machInst, %(dest)s,
|
||||
%(op1)s, imm, true);
|
||||
}
|
||||
''' % {"mnem" : mnem, "dest" : dest, "op1" : op1}
|
||||
|
||||
decode_block = '''
|
||||
{
|
||||
const uint32_t op = bits(machInst, 24, 21);
|
||||
const bool s = (bits(machInst, 20) == 1);
|
||||
const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
|
||||
const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
|
||||
const uint32_t ctrlImm = bits(machInst.instBits, 26) << 3 |
|
||||
bits(machInst, 14, 12);
|
||||
const uint32_t dataImm = bits(machInst, 7, 0);
|
||||
const uint32_t imm = modified_imm(ctrlImm, dataImm);
|
||||
switch (op) {
|
||||
case 0x0:
|
||||
if (rd == INTREG_PC) {
|
||||
%(tst)s
|
||||
} else {
|
||||
%(and)s
|
||||
}
|
||||
case 0x1:
|
||||
%(bic)s
|
||||
case 0x2:
|
||||
if (rn == INTREG_PC) {
|
||||
%(mov)s
|
||||
} else {
|
||||
%(orr)s
|
||||
}
|
||||
case 0x3:
|
||||
if (rn == INTREG_PC) {
|
||||
%(mvn)s
|
||||
} else {
|
||||
%(orn)s
|
||||
}
|
||||
case 0x4:
|
||||
if (rd == INTREG_PC) {
|
||||
%(teq)s
|
||||
} else {
|
||||
%(eor)s
|
||||
}
|
||||
case 0x8:
|
||||
if (rd == INTREG_PC) {
|
||||
%(cmn)s
|
||||
} else {
|
||||
%(add)s
|
||||
}
|
||||
case 0xa:
|
||||
%(adc)s
|
||||
case 0xb:
|
||||
%(sbc)s
|
||||
case 0xd:
|
||||
if (rd == INTREG_PC) {
|
||||
%(cmp)s
|
||||
} else {
|
||||
%(sub)s
|
||||
}
|
||||
case 0xe:
|
||||
%(rsb)s
|
||||
default:
|
||||
return new Unknown(machInst);
|
||||
}
|
||||
}
|
||||
''' % {
|
||||
"tst" : decInst("Tst", "INTREG_ZERO"),
|
||||
"and" : decInst("And"),
|
||||
"bic" : decInst("Bic"),
|
||||
"mov" : decInst("Mov", op1="INTREG_ZERO"),
|
||||
"orr" : decInst("Orr"),
|
||||
"mvn" : decInst("Mvn", op1="INTREG_ZERO"),
|
||||
"orn" : decInst("Orn"),
|
||||
"teq" : decInst("Teq", dest="INTREG_ZERO"),
|
||||
"eor" : decInst("Eor"),
|
||||
"cmn" : decInst("Cmn", dest="INTREG_ZERO"),
|
||||
"add" : decInst("Add"),
|
||||
"adc" : decInst("Adc"),
|
||||
"sbc" : decInst("Sbc"),
|
||||
"cmp" : decInst("Cmp", dest="INTREG_ZERO"),
|
||||
"sub" : decInst("Sub"),
|
||||
"rsb" : decInst("Rsb")
|
||||
}
|
||||
}};
|
||||
|
||||
def format Thumb32DataProcShiftReg() {{
|
||||
|
||||
def decInst(mnem, dest="rd", op1="rn"):
|
||||
return '''
|
||||
if (s) {
|
||||
return new %(mnem)sDRegCc(machInst, %(dest)s,
|
||||
%(op1)s, rm, amt, type);
|
||||
} else {
|
||||
return new %(mnem)sDReg(machInst, %(dest)s,
|
||||
%(op1)s, rm, amt, type);
|
||||
}
|
||||
''' % {"mnem" : mnem, "dest" : dest, "op1" : op1}
|
||||
|
||||
decode_block = '''
|
||||
{
|
||||
const uint32_t op = bits(machInst, 24, 21);
|
||||
const bool s = (bits(machInst, 20) == 1);
|
||||
const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
|
||||
const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
|
||||
const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
|
||||
const uint32_t amt = (bits(machInst, 14, 12) << 2) |
|
||||
bits(machInst, 7, 6);
|
||||
const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 5, 4);
|
||||
switch (op) {
|
||||
case 0x0:
|
||||
if (rd == INTREG_PC) {
|
||||
%(tst)s
|
||||
} else {
|
||||
%(and)s
|
||||
}
|
||||
case 0x1:
|
||||
%(bic)s
|
||||
case 0x2:
|
||||
if (rn == INTREG_PC) {
|
||||
%(mov)s
|
||||
} else {
|
||||
%(orr)s
|
||||
}
|
||||
case 0x3:
|
||||
if (rn == INTREG_PC) {
|
||||
%(mvn)s
|
||||
} else {
|
||||
%(orn)s
|
||||
}
|
||||
case 0x4:
|
||||
if (rd == INTREG_PC) {
|
||||
%(teq)s
|
||||
} else {
|
||||
%(eor)s
|
||||
}
|
||||
case 0x6:
|
||||
return new WarnUnimplemented("pkh", machInst);
|
||||
case 0x8:
|
||||
if (rd == INTREG_PC) {
|
||||
%(cmn)s
|
||||
} else {
|
||||
%(add)s
|
||||
}
|
||||
case 0xa:
|
||||
%(adc)s
|
||||
case 0xb:
|
||||
%(sbc)s
|
||||
case 0xd:
|
||||
if (rd == INTREG_PC) {
|
||||
%(cmp)s
|
||||
} else {
|
||||
%(sub)s
|
||||
}
|
||||
case 0xe:
|
||||
%(rsb)s
|
||||
default:
|
||||
return new Unknown(machInst);
|
||||
}
|
||||
}
|
||||
''' % {
|
||||
"tst" : decInst("Tst", "INTREG_ZERO"),
|
||||
"and" : decInst("And"),
|
||||
"bic" : decInst("Bic"),
|
||||
"mov" : decInst("Mov", op1="INTREG_ZERO"),
|
||||
"orr" : decInst("Orr"),
|
||||
"mvn" : decInst("Mvn", op1="INTREG_ZERO"),
|
||||
"orn" : decInst("Orn"),
|
||||
"teq" : decInst("Teq", "INTREG_ZERO"),
|
||||
"eor" : decInst("Eor"),
|
||||
"cmn" : decInst("Cmn", "INTREG_ZERO"),
|
||||
"add" : decInst("Add"),
|
||||
"adc" : decInst("Adc"),
|
||||
"sbc" : decInst("Sbc"),
|
||||
"cmp" : decInst("Cmp", "INTREG_ZERO"),
|
||||
"sub" : decInst("Sub"),
|
||||
"rsb" : decInst("Rsb")
|
||||
}
|
||||
}};
|
||||
|
|
|
|||
Loading…
Reference in a new issue