m5: Regression Tester Update
This patch includes the necessary regression updates to test the new ruby configuration system. The patch includes support for multiple ruby protocols and adds the ruby random tester. The patch removes atomic mode test for ruby since ruby does not support atomic mode acceses. These tests can be added back in when ruby supports atomic mode for real. --HG-- rename : tests/quick/50.memtest/test.py => tests/quick/60.rubytest/test.py
This commit is contained in:
Brad Beckmann
parent
ceae8383ff
commit
ab2f864af2
4
build_opts/ALPHA_SE_MESI_CMP_directory
Normal file
4
build_opts/ALPHA_SE_MESI_CMP_directory
Normal file
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@ -0,0 +1,4 @@
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FULL_SYSTEM = 0
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SS_COMPATIBLE_FP = 1
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
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PROTOCOL = 'MESI_CMP_directory'
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4
build_opts/ALPHA_SE_MOESI_CMP_directory
Normal file
4
build_opts/ALPHA_SE_MOESI_CMP_directory
Normal file
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@ -0,0 +1,4 @@
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FULL_SYSTEM = 0
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SS_COMPATIBLE_FP = 1
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
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PROTOCOL = 'MOESI_CMP_directory'
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4
build_opts/ALPHA_SE_MOESI_CMP_token
Normal file
4
build_opts/ALPHA_SE_MOESI_CMP_token
Normal file
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@ -0,0 +1,4 @@
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FULL_SYSTEM = 0
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SS_COMPATIBLE_FP = 1
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
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PROTOCOL = 'MOESI_CMP_token'
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4
build_opts/ALPHA_SE_MOESI_hammer
Normal file
4
build_opts/ALPHA_SE_MOESI_hammer
Normal file
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@ -0,0 +1,4 @@
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FULL_SYSTEM = 0
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SS_COMPATIBLE_FP = 1
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CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
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PROTOCOL = 'MOESI_hammer'
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@ -4,4 +4,3 @@ MESI_CMP_directory-L2cache.sm
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MESI_CMP_directory-dir.sm
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MESI_CMP_directory-dma.sm
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standard_CMP-protocol.sm
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@ -264,11 +264,23 @@ if env['FULL_SYSTEM']:
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else:
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configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest',
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'simple-atomic-mp', 'simple-timing-mp', 'o3-timing-mp',
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'inorder-timing']
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'inorder-timing', 'rubytest']
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if env['RUBY']:
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# Hack for Ruby
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configs += [c + '-ruby' for c in configs]
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# With Ruby, A protocol must be specified in the environment
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assert(env['PROTOCOL'])
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#
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# Is there a way to determine what is Protocol EnumVariable
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# default and eliminate the need to hard code the default protocol below?
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#
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# If the binary includes the default ruby protocol, run both ruby and
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# non-ruby versions of the tests. Otherwise just run the ruby versions.
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#
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if env['PROTOCOL'] == 'MI_example':
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configs += [c + "-ruby" for c in configs]
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else:
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configs = [c + "-ruby-" + env['PROTOCOL'] for c in configs]
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cwd = os.getcwd()
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os.chdir(str(Dir('.').srcdir))
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@ -1,4 +1,5 @@
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2010 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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@ -63,7 +64,11 @@ execfile(os.path.join(config_root, "configs/common", "Options.py"))
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#MAX CORES IS 8 with the fals sharing method
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nb_cores = 8
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cpus = [ MemTest() for i in xrange(nb_cores) ]
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# ruby does not support atomic, functional, or uncacheable accesses
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cpus = [ MemTest(atomic=False, percent_functional=0, \
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percent_uncacheable=0) \
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for i in xrange(nb_cores) ]
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# overwrite options.num_cpus with the nb_cores value
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options.num_cpus = nb_cores
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@ -91,3 +96,6 @@ for (i, ruby_port) in enumerate(system.ruby.cpu_ruby_ports):
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root = Root(system = system)
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root.system.mem_mode = 'timing'
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# Not much point in this being higher than the L1 latency
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m5.ticks.setGlobalFrequency('1ns')
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@ -1,30 +0,0 @@
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import os
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import subprocess
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from os.path import dirname, join as joinpath
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import m5
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from m5.params import *
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def generate(config_file, cores=1, memories=1, memory_size=1024, \
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cache_size=32768, cache_assoc=8, dmas=1,
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ruby_tick='1t', ports_per_cpu=2, protocol='MOESI_CMP_directory'):
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default = joinpath(dirname(__file__), '../../src/mem/ruby/config')
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ruby_config = os.environ.get('RUBY_CONFIG', default)
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args = [ "ruby", "-I", ruby_config, joinpath(ruby_config, "print_cfg.rb"),
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"-c", str(protocol),
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"-r", joinpath(ruby_config, config_file), "-p", str(cores),
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"-m", str(memories), "-s", str(memory_size), "-C", str(cache_size),
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"-A", str(cache_assoc), "-D", str(dmas)]
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temp_config = joinpath(m5.options.outdir, "ruby.config")
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ret = subprocess.call(args, stdout=file(temp_config, "w"))
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if ret != 0:
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raise RuntimeError, "subprocess failed!"
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return m5.objects.RubyMemory(clock = ruby_tick,
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config_file = temp_config,
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num_cpus = cores,
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range = AddrRange(str(memory_size)+"MB"),
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num_dmas = dmas,
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ports_per_core = ports_per_cpu)
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103
tests/configs/rubytest-ruby.py
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103
tests/configs/rubytest-ruby.py
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@ -0,0 +1,103 @@
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ron Dreslinski
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# Brad Beckmann
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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import os, optparse, sys
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if buildEnv['FULL_SYSTEM']:
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panic("This script requires system-emulation mode (*_SE).")
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# Get paths we might need. It's expected this file is in m5/configs/example.
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config_path = os.path.dirname(os.path.abspath(__file__))
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config_root = os.path.dirname(config_path)
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m5_root = os.path.dirname(config_root)
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addToPath(config_root+'/configs/common')
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addToPath(config_root+'/configs/ruby')
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import Ruby
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parser = optparse.OptionParser()
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#
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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#
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parser.add_option("--l1d_size", type="string", default="256B")
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parser.add_option("--l1i_size", type="string", default="256B")
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parser.add_option("--l2_size", type="string", default="512B")
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parser.add_option("--l1d_assoc", type="int", default=2)
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parser.add_option("--l1i_assoc", type="int", default=2)
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parser.add_option("--l2_assoc", type="int", default=2)
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execfile(os.path.join(config_root, "configs/common", "Options.py"))
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(options, args) = parser.parse_args()
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#
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# create the tester and system, including ruby
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#
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tester = RubyTester(checks_to_complete = 100, wakeup_frequency = 10)
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system = System(physmem = PhysicalMemory())
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system.ruby = Ruby.create_system(options, system.physmem)
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assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
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#
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# The tester is most effective when randomization is turned on and
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# artifical delay is randomly inserted on messages
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#
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system.ruby.randomization = True
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for ruby_port in system.ruby.cpu_ruby_ports:
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#
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# Tie the ruby tester ports to the ruby cpu ports
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#
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tester.cpuPort = ruby_port.port
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#
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# Tell the sequencer this is the ruby tester so that it
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# copies the subblock back to the checker
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#
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ruby_port.using_ruby_tester = True
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# -----------------------
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# run simulation
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# -----------------------
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root = Root( system = system )
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root.system.mem_mode = 'timing'
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# Not much point in this being higher than the L1 latency
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m5.ticks.setGlobalFrequency('1ns')
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@ -28,24 +28,59 @@
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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import os, optparse, sys
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if buildEnv['FULL_SYSTEM']:
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panic("This script requires system-emulation mode (*_SE).")
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# Get paths we might need
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config_path = os.path.dirname(os.path.abspath(__file__))
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config_root = os.path.dirname(config_path)
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m5_root = os.path.dirname(config_root)
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addToPath(config_root+'/configs/common')
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addToPath(config_root+'/configs/ruby')
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import Ruby
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parser = optparse.OptionParser()
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#
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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#
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parser.add_option("--l1d_size", type="string", default="256B")
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parser.add_option("--l1i_size", type="string", default="256B")
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parser.add_option("--l2_size", type="string", default="512B")
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parser.add_option("--l1d_assoc", type="int", default=2)
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parser.add_option("--l1i_assoc", type="int", default=2)
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parser.add_option("--l2_assoc", type="int", default=2)
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execfile(os.path.join(config_root, "configs/common", "Options.py"))
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(options, args) = parser.parse_args()
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nb_cores = 4
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cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
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import ruby_config
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ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
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# overwrite the num_cpus to equal nb_cores
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options.num_cpus = nb_cores
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# system simulated
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system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
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system = System(cpu = cpus,
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physmem = PhysicalMemory())
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# add L1 caches
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for cpu in cpus:
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cpu.connectMemPorts(system.membus)
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cpu.clock = '2GHz'
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system.ruby = Ruby.create_system(options, system.physmem)
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# connect memory to membus
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system.physmem.port = system.membus.port
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assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
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for (i, cpu) in enumerate(system.cpu):
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#
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# Tie the cpu ports to the ruby cpu ports
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#
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cpu.icache_port = system.ruby.cpu_ruby_ports[i].port
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cpu.dcache_port = system.ruby.cpu_ruby_ports[i].port
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# -----------------------
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# run simulation
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@ -53,3 +88,6 @@ system.physmem.port = system.membus.port
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root = Root( system = system )
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root.system.mem_mode = 'timing'
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# Not much point in this being higher than the L1 latency
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m5.ticks.setGlobalFrequency('1ns')
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@ -28,16 +28,63 @@
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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import os, optparse, sys
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import ruby_config
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ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1)
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if buildEnv['FULL_SYSTEM']:
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panic("This script requires system-emulation mode (*_SE).")
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# Get paths we might need
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config_path = os.path.dirname(os.path.abspath(__file__))
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config_root = os.path.dirname(config_path)
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m5_root = os.path.dirname(config_root)
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addToPath(config_root+'/configs/common')
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addToPath(config_root+'/configs/ruby')
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import Ruby
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parser = optparse.OptionParser()
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#
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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#
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parser.add_option("--l1d_size", type="string", default="256B")
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parser.add_option("--l1i_size", type="string", default="256B")
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parser.add_option("--l2_size", type="string", default="512B")
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parser.add_option("--l1d_assoc", type="int", default=2)
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parser.add_option("--l1i_assoc", type="int", default=2)
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parser.add_option("--l2_assoc", type="int", default=2)
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execfile(os.path.join(config_root, "configs/common", "Options.py"))
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(options, args) = parser.parse_args()
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# this is a uniprocessor only test
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options.num_cpus = 1
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cpu = TimingSimpleCPU(cpu_id=0)
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system = System(cpu = cpu,
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physmem = ruby_memory,
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membus = Bus())
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system.physmem.port = system.membus.port
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cpu.connectMemPorts(system.membus)
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cpu.clock = '2GHz'
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physmem = PhysicalMemory())
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system.ruby = Ruby.create_system(options, system.physmem)
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assert(len(system.ruby.cpu_ruby_ports) == 1)
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#
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# Tie the cpu cache ports to the ruby cpu ports and
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# physmem, respectively
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#
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cpu.icache_port = system.ruby.cpu_ruby_ports[0].port
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cpu.dcache_port = system.ruby.cpu_ruby_ports[0].port
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# -----------------------
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# run simulation
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# -----------------------
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root = Root(system = system)
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root.system.mem_mode = 'timing'
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# Not much point in this being higher than the L1 latency
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m5.ticks.setGlobalFrequency('1ns')
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@ -1,97 +0,0 @@
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[root]
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type=Root
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children=system
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dummy=0
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[system]
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type=System
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children=cpu membus physmem
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mem_mode=atomic
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physmem=system.physmem
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[system.cpu]
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type=AtomicSimpleCPU
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children=dtb itb tracer workload
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checker=Null
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clock=500
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cpu_id=0
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defer_registration=false
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do_checkpoint_insts=true
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do_statistics_insts=true
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dtb=system.cpu.dtb
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function_trace=false
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function_trace_start=0
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itb=system.cpu.itb
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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numThreads=1
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phase=0
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progress_interval=0
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simulate_data_stalls=false
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simulate_inst_stalls=false
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system=system
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tracer=system.cpu.tracer
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width=1
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workload=system.cpu.workload
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dcache_port=system.membus.port[2]
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icache_port=system.membus.port[1]
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[system.cpu.dtb]
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type=AlphaTLB
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size=64
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[system.cpu.itb]
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type=AlphaTLB
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size=48
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[system.cpu.tracer]
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type=ExeTracer
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[system.cpu.workload]
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type=LiveProcess
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cmd=hello
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cwd=
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egid=100
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env=
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errout=cerr
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euid=100
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executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
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gid=100
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input=cin
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max_stack_size=67108864
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output=cout
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pid=100
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ppid=99
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simpoint=0
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system=system
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uid=100
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[system.membus]
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type=Bus
|
||||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=RubyMemory
|
||||
clock=1
|
||||
config_file=build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic-ruby/ruby.config
|
||||
debug=false
|
||||
debug_file=ruby.debug
|
||||
file=
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
num_cpus=1
|
||||
phase=0
|
||||
range=0:134217727
|
||||
stats_file=ruby.stats
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
|
|
@ -1,382 +0,0 @@
|
|||
|
||||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
RubySystem config:
|
||||
random_seed: 952703
|
||||
randomization: 0
|
||||
tech_nm: 45
|
||||
freq_mhz: 3000
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 1073741824
|
||||
memory_size_bits: 30
|
||||
DMA_Controller config: DMAController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
dma_sequencer: DMASequencer_0
|
||||
number_of_TBEs: 128
|
||||
transitions_per_cycle: 32
|
||||
Directory_Controller config: DirectoryController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
directory_latency: 6
|
||||
directory_name: DirectoryMemory_0
|
||||
memory_controller_name: MemoryControl_0
|
||||
memory_latency: 158
|
||||
number_of_TBEs: 128
|
||||
recycle_latency: 10
|
||||
to_mem_ctrl_latency: 1
|
||||
transitions_per_cycle: 32
|
||||
L1Cache_Controller config: L1CacheController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
cache: l1u_0
|
||||
cache_response_latency: 12
|
||||
issue_latency: 2
|
||||
number_of_TBEs: 128
|
||||
sequencer: Sequencer_0
|
||||
transitions_per_cycle: 32
|
||||
Cache config: l1u_0
|
||||
controller: L1CacheController_0
|
||||
cache_associativity: 8
|
||||
num_cache_sets_bits: 2
|
||||
num_cache_sets: 4
|
||||
cache_set_size_bytes: 256
|
||||
cache_set_size_Kbytes: 0.25
|
||||
cache_set_size_Mbytes: 0.000244141
|
||||
cache_size_bytes: 2048
|
||||
cache_size_Kbytes: 2
|
||||
cache_size_Mbytes: 0.00195312
|
||||
DirectoryMemory Global Config:
|
||||
number of directory memories: 1
|
||||
total memory size bytes: 1073741824
|
||||
total memory size bits: 30
|
||||
DirectoryMemory module config: DirectoryMemory_0
|
||||
controller: DirectoryController_0
|
||||
version: 0
|
||||
memory_bits: 30
|
||||
memory_size_bytes: 1073741824
|
||||
memory_size_Kbytes: 1.04858e+06
|
||||
memory_size_Mbytes: 1024
|
||||
memory_size_Gbytes: 1
|
||||
Seqeuncer config: Sequencer_0
|
||||
controller: L1CacheController_0
|
||||
version: 0
|
||||
max_outstanding_requests: 16
|
||||
deadlock_threshold: 500000
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology: theTopology
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
virtual_net_2: active, ordered
|
||||
virtual_net_3: inactive
|
||||
virtual_net_4: active, ordered
|
||||
virtual_net_5: active, ordered
|
||||
|
||||
--- Begin Topology Print ---
|
||||
|
||||
Topology print ONLY indicates the _NETWORK_ latency between two machines
|
||||
It does NOT include the latency within the machines
|
||||
|
||||
L1Cache-0 Network Latencies
|
||||
L1Cache-0 -> Directory-0 net_lat: 7
|
||||
L1Cache-0 -> DMA-0 net_lat: 7
|
||||
|
||||
Directory-0 Network Latencies
|
||||
Directory-0 -> L1Cache-0 net_lat: 7
|
||||
Directory-0 -> DMA-0 net_lat: 7
|
||||
|
||||
DMA-0 Network Latencies
|
||||
DMA-0 -> L1Cache-0 net_lat: 7
|
||||
DMA-0 -> Directory-0 net_lat: 7
|
||||
|
||||
--- End Topology Print ---
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
periodic_stats_period: 1000000
|
||||
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jul/06/2009 11:11:07
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 0.2
|
||||
Virtual_time_in_minutes: 0.00333333
|
||||
Virtual_time_in_hours: 5.55556e-05
|
||||
Virtual_time_in_days: 5.55556e-05
|
||||
|
||||
Ruby_current_time: 3215001
|
||||
Ruby_start_time: 1
|
||||
Ruby_cycles: 3215000
|
||||
|
||||
mbytes_resident: 144.742
|
||||
mbytes_total: 1329.5
|
||||
resident_ratio: 0.108872
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
instruction_executed: 1 [ 1 ]
|
||||
ruby_cycles_executed: 3215001 [ 3215001 ]
|
||||
cycles_per_instruction: 3.215e+06 [ 3.215e+06 ]
|
||||
misses_per_thousand_instructions: 0 [ 0 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
instructions_per_transaction: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
|
||||
L1D_cache cache stats:
|
||||
L1D_cache_total_misses: 0
|
||||
L1D_cache_total_demand_misses: 0
|
||||
L1D_cache_total_prefetches: 0
|
||||
L1D_cache_total_sw_prefetches: 0
|
||||
L1D_cache_total_hw_prefetches: 0
|
||||
L1D_cache_misses_per_transaction: 0
|
||||
L1D_cache_misses_per_instruction: 0
|
||||
L1D_cache_instructions_per_misses: NaN
|
||||
|
||||
L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
L1I_cache cache stats:
|
||||
L1I_cache_total_misses: 0
|
||||
L1I_cache_total_demand_misses: 0
|
||||
L1I_cache_total_prefetches: 0
|
||||
L1I_cache_total_sw_prefetches: 0
|
||||
L1I_cache_total_hw_prefetches: 0
|
||||
L1I_cache_misses_per_transaction: 0
|
||||
L1I_cache_misses_per_instruction: 0
|
||||
L1I_cache_instructions_per_misses: NaN
|
||||
|
||||
L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
L2_cache cache stats:
|
||||
L2_cache_total_misses: 0
|
||||
L2_cache_total_demand_misses: 0
|
||||
L2_cache_total_prefetches: 0
|
||||
L2_cache_total_sw_prefetches: 0
|
||||
L2_cache_total_hw_prefetches: 0
|
||||
L2_cache_misses_per_transaction: 0
|
||||
L2_cache_misses_per_instruction: 0
|
||||
L2_cache_instructions_per_misses: NaN
|
||||
|
||||
L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
Directory-0:0
|
||||
DMA-0:0
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 37817
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 40
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0
|
||||
links_utilized_percent_switch_0_link_0: 0 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0 bw: 160000 base_latency: 1
|
||||
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0
|
||||
links_utilized_percent_switch_1_link_0: 0 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0 bw: 160000 base_latency: 1
|
||||
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0
|
||||
links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
|
||||
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 0
|
||||
links_utilized_percent_switch_3_link_0: 0 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
|
||||
|
||||
|
||||
--- DMA ---
|
||||
- Event Counts -
|
||||
ReadRequest 0
|
||||
WriteRequest 0
|
||||
Data 0
|
||||
Ack 0
|
||||
|
||||
- Transitions -
|
||||
READY ReadRequest 0 <--
|
||||
READY WriteRequest 0 <--
|
||||
|
||||
BUSY_RD Data 0 <--
|
||||
|
||||
BUSY_WR Ack 0 <--
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX 0
|
||||
GETS 0
|
||||
PUTX 0
|
||||
PUTX_NotOwner 0
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
Memory_Data 0
|
||||
Memory_Ack 0
|
||||
|
||||
- Transitions -
|
||||
I GETX 0 <--
|
||||
I PUTX_NotOwner 0 <--
|
||||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
|
||||
M GETX 0 <--
|
||||
M PUTX 0 <--
|
||||
M PUTX_NotOwner 0 <--
|
||||
M DMA_READ 0 <--
|
||||
M DMA_WRITE 0 <--
|
||||
|
||||
M_DRD GETX 0 <--
|
||||
M_DRD PUTX 0 <--
|
||||
|
||||
M_DWR GETX 0 <--
|
||||
M_DWR PUTX 0 <--
|
||||
|
||||
M_DWRI Memory_Ack 0 <--
|
||||
|
||||
IM GETX 0 <--
|
||||
IM GETS 0 <--
|
||||
IM PUTX 0 <--
|
||||
IM PUTX_NotOwner 0 <--
|
||||
IM DMA_READ 0 <--
|
||||
IM DMA_WRITE 0 <--
|
||||
IM Memory_Data 0 <--
|
||||
|
||||
MI GETX 0 <--
|
||||
MI GETS 0 <--
|
||||
MI PUTX 0 <--
|
||||
MI PUTX_NotOwner 0 <--
|
||||
MI DMA_READ 0 <--
|
||||
MI DMA_WRITE 0 <--
|
||||
MI Memory_Ack 0 <--
|
||||
|
||||
ID GETX 0 <--
|
||||
ID GETS 0 <--
|
||||
ID PUTX 0 <--
|
||||
ID PUTX_NotOwner 0 <--
|
||||
ID DMA_READ 0 <--
|
||||
ID DMA_WRITE 0 <--
|
||||
ID Memory_Data 0 <--
|
||||
|
||||
ID_W GETX 0 <--
|
||||
ID_W GETS 0 <--
|
||||
ID_W PUTX 0 <--
|
||||
ID_W PUTX_NotOwner 0 <--
|
||||
ID_W DMA_READ 0 <--
|
||||
ID_W DMA_WRITE 0 <--
|
||||
ID_W Memory_Ack 0 <--
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load 0
|
||||
Ifetch 0
|
||||
Store 0
|
||||
Data 0
|
||||
Fwd_GETX 0
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 0 <--
|
||||
I Ifetch 0 <--
|
||||
I Store 0 <--
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M Fwd_GETX 0 <--
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
|
||||
IS Data 0 <--
|
||||
|
||||
IM Data 0 <--
|
||||
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
|
||||
print config: 1
|
||||
Creating new MessageBuffer for 0 0
|
||||
Creating new MessageBuffer for 0 1
|
||||
Creating new MessageBuffer for 0 2
|
||||
Creating new MessageBuffer for 0 3
|
||||
Creating new MessageBuffer for 0 4
|
||||
Creating new MessageBuffer for 0 5
|
||||
Creating new MessageBuffer for 1 0
|
||||
Creating new MessageBuffer for 1 1
|
||||
Creating new MessageBuffer for 1 2
|
||||
Creating new MessageBuffer for 1 3
|
||||
Creating new MessageBuffer for 1 4
|
||||
Creating new MessageBuffer for 1 5
|
||||
Creating new MessageBuffer for 2 0
|
||||
Creating new MessageBuffer for 2 1
|
||||
Creating new MessageBuffer for 2 2
|
||||
Creating new MessageBuffer for 2 3
|
||||
Creating new MessageBuffer for 2 4
|
||||
Creating new MessageBuffer for 2 5
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 6 2009 11:03:45
|
||||
M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
|
||||
M5 started Jul 6 2009 11:11:06
|
||||
M5 executing on maize
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic-ruby
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Debug: Adding to filter: 'q' (Queue)
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 3215000 because target called exit()
|
||||
|
|
@ -0,0 +1,281 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
checker=Null
|
||||
clock=1
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
l2_request_latency=2
|
||||
l2_response_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
to_l1_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links2.ext_node
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links2.ext_node.directory
|
||||
directory_latency=6
|
||||
memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
to_mem_ctrl_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
size=134217728
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=0
|
||||
node_b=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=1
|
||||
node_b=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links2]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=2
|
||||
node_b=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
|
||||
[system.ruby.tracer]
|
||||
type=RubyTracer
|
||||
warmup_length=100000
|
||||
|
||||
|
|
@ -0,0 +1,617 @@
|
|||
|
||||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
RubySystem config:
|
||||
random_seed: 1234
|
||||
randomization: 0
|
||||
cycle_period: 1
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 134217728
|
||||
memory_size_bits: 27
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, unordered
|
||||
virtual_net_1: active, unordered
|
||||
virtual_net_2: active, unordered
|
||||
virtual_net_3: inactive
|
||||
virtual_net_4: inactive
|
||||
virtual_net_5: inactive
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
virtual_net_9: inactive
|
||||
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
periodic_stats_period: 1000000
|
||||
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/28/2010 13:57:44
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 0.95
|
||||
Virtual_time_in_minutes: 0.0158333
|
||||
Virtual_time_in_hours: 0.000263889
|
||||
Virtual_time_in_days: 1.09954e-05
|
||||
|
||||
Ruby_current_time: 275313
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 275313
|
||||
|
||||
mbytes_resident: 34.4609
|
||||
mbytes_total: 34.4688
|
||||
resident_ratio: 1
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
ruby_cycles_executed: 275314 [ 275314 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
L2Cache-0:0
|
||||
Directory-0:0
|
||||
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 281 count: 8464 average: 31.5275 | standard deviation: 62.4195 | 0 6974 0 0 0 0 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156 439 246 330 220 8 7 9 11 3 2 9 4 5 1 0 0 1 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_1: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 2 max: 281 count: 1185 average: 82.5848 | standard deviation: 82.5677 | 0 602 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 191 73 123 92 4 2 3 3 1 1 7 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 2 max: 215 count: 865 average: 42.0289 | standard deviation: 69.8546 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 45 78 16 22 0 0 2 2 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 30 count: 9645 average: 0.0134785 | standard deviation: 0.509043 | 9637 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 6920 average: 0 | standard deviation: 0 | 6920 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 30 count: 2725 average: 0.0477064 | standard deviation: 0.956852 | 2717 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1041 average: 0 | standard deviation: 0 | 1041 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 5879 average: 0 | standard deviation: 0 | 5879 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 7392
|
||||
page_faults: 2212
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.0889147
|
||||
links_utilized_percent_switch_0_link_0: 0.0675913 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.110238 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 1490 107280 [ 0 1490 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Control: 1699 13592 [ 0 900 799 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.228653
|
||||
links_utilized_percent_switch_1_link_0: 0.0938114 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.363495 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Control: 3151 25208 [ 0 2352 799 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1767 127224 [ 0 1767 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 1611 12888 [ 0 1611 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.144145
|
||||
links_utilized_percent_switch_2_link_0: 0.0232826 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.265007 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 1452 11616 [ 0 1452 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 0.246247
|
||||
links_utilized_percent_switch_3_link_0: 0.270365 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.375246 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.0931304 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Request_Control: 1041 8328 [ 1041 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 1490 107280 [ 0 1490 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 1490 11920 [ 1490 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 1460 105120 [ 0 1460 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Control: 3151 25208 [ 0 2352 799 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 288 20736 [ 147 141 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 289 2312 [ 289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Control: 1460 11680 [ 1460 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
--- L1Cache 0 ---
|
||||
- Event Counts -
|
||||
Load 1185
|
||||
Ifetch 6414
|
||||
Store 865
|
||||
Inv 1041
|
||||
L1_Replacement 1354
|
||||
Fwd_GETX 0
|
||||
Fwd_GETS 0
|
||||
Fwd_GET_INSTR 0
|
||||
Data 0
|
||||
Data_Exclusive 583
|
||||
DataS_fromL1 0
|
||||
Data_all_Acks 907
|
||||
Ack 0
|
||||
Ack_all 0
|
||||
WB_Ack 436
|
||||
|
||||
- Transitions -
|
||||
NP Load 525
|
||||
NP Ifetch 646
|
||||
NP Store 191
|
||||
NP Inv 356
|
||||
NP L1_Replacement 0 <--
|
||||
|
||||
I Load 58
|
||||
I Ifetch 45
|
||||
I Store 25
|
||||
I Inv 0 <--
|
||||
I L1_Replacement 556
|
||||
|
||||
S Load 0 <--
|
||||
S Ifetch 5723
|
||||
S Store 0 <--
|
||||
S Inv 325
|
||||
S L1_Replacement 362
|
||||
|
||||
E Load 454
|
||||
E Ifetch 0 <--
|
||||
E Store 71
|
||||
E Inv 219
|
||||
E L1_Replacement 291
|
||||
E Fwd_GETX 0 <--
|
||||
E Fwd_GETS 0 <--
|
||||
E Fwd_GET_INSTR 0 <--
|
||||
|
||||
M Load 148
|
||||
M Ifetch 0 <--
|
||||
M Store 578
|
||||
M Inv 141
|
||||
M L1_Replacement 145
|
||||
M Fwd_GETX 0 <--
|
||||
M Fwd_GETS 0 <--
|
||||
M Fwd_GET_INSTR 0 <--
|
||||
|
||||
IS Load 0 <--
|
||||
IS Ifetch 0 <--
|
||||
IS Store 0 <--
|
||||
IS Inv 0 <--
|
||||
IS L1_Replacement 0 <--
|
||||
IS Data_Exclusive 583
|
||||
IS DataS_fromL1 0 <--
|
||||
IS Data_all_Acks 691
|
||||
|
||||
IM Load 0 <--
|
||||
IM Ifetch 0 <--
|
||||
IM Store 0 <--
|
||||
IM Inv 0 <--
|
||||
IM L1_Replacement 0 <--
|
||||
IM Data 0 <--
|
||||
IM Data_all_Acks 216
|
||||
IM Ack 0 <--
|
||||
|
||||
SM Load 0 <--
|
||||
SM Ifetch 0 <--
|
||||
SM Store 0 <--
|
||||
SM Inv 0 <--
|
||||
SM L1_Replacement 0 <--
|
||||
SM Ack 0 <--
|
||||
SM Ack_all 0 <--
|
||||
|
||||
IS_I Load 0 <--
|
||||
IS_I Ifetch 0 <--
|
||||
IS_I Store 0 <--
|
||||
IS_I Inv 0 <--
|
||||
IS_I L1_Replacement 0 <--
|
||||
IS_I Data_Exclusive 0 <--
|
||||
IS_I DataS_fromL1 0 <--
|
||||
IS_I Data_all_Acks 0 <--
|
||||
|
||||
M_I Load 0 <--
|
||||
M_I Ifetch 0 <--
|
||||
M_I Store 0 <--
|
||||
M_I Inv 0 <--
|
||||
M_I L1_Replacement 0 <--
|
||||
M_I Fwd_GETX 0 <--
|
||||
M_I Fwd_GETS 0 <--
|
||||
M_I Fwd_GET_INSTR 0 <--
|
||||
M_I WB_Ack 436
|
||||
|
||||
E_I Load 0 <--
|
||||
E_I Ifetch 0 <--
|
||||
E_I Store 0 <--
|
||||
E_I L1_Replacement 0 <--
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
--- L2Cache 0 ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR 691
|
||||
L1_GETS 592
|
||||
L1_GETX 220
|
||||
L1_UPGRADE 0
|
||||
L1_PUTX 436
|
||||
L1_PUTX_old 0
|
||||
Fwd_L1_GETX 0
|
||||
Fwd_L1_GETS 0
|
||||
Fwd_L1_GET_INSTR 0
|
||||
L2_Replacement 142
|
||||
L2_Replacement_clean 1310
|
||||
Mem_Data 1460
|
||||
Mem_Ack 1452
|
||||
WB_Data 141
|
||||
WB_Data_clean 0
|
||||
Ack 0
|
||||
Ack_all 900
|
||||
Unblock 0
|
||||
Unblock_Cancel 0
|
||||
Exclusive_Unblock 799
|
||||
MEM_Inv 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GET_INSTR 686
|
||||
NP L1_GETS 570
|
||||
NP L1_GETX 204
|
||||
NP L1_PUTX 0 <--
|
||||
NP L1_PUTX_old 0 <--
|
||||
|
||||
SS L1_GET_INSTR 5
|
||||
SS L1_GETS 0 <--
|
||||
SS L1_GETX 0 <--
|
||||
SS L1_UPGRADE 0 <--
|
||||
SS L1_PUTX 0 <--
|
||||
SS L1_PUTX_old 0 <--
|
||||
SS L2_Replacement 0 <--
|
||||
SS L2_Replacement_clean 681
|
||||
SS MEM_Inv 0 <--
|
||||
|
||||
M L1_GET_INSTR 0 <--
|
||||
M L1_GETS 13
|
||||
M L1_GETX 12
|
||||
M L1_PUTX 0 <--
|
||||
M L1_PUTX_old 0 <--
|
||||
M L2_Replacement 134
|
||||
M L2_Replacement_clean 277
|
||||
M MEM_Inv 0 <--
|
||||
|
||||
MT L1_GET_INSTR 0 <--
|
||||
MT L1_GETS 0 <--
|
||||
MT L1_GETX 0 <--
|
||||
MT L1_PUTX 436
|
||||
MT L1_PUTX_old 0 <--
|
||||
MT L2_Replacement 8
|
||||
MT L2_Replacement_clean 352
|
||||
MT MEM_Inv 0 <--
|
||||
|
||||
M_I L1_GET_INSTR 0 <--
|
||||
M_I L1_GETS 9
|
||||
M_I L1_GETX 4
|
||||
M_I L1_UPGRADE 0 <--
|
||||
M_I L1_PUTX 0 <--
|
||||
M_I L1_PUTX_old 0 <--
|
||||
M_I Mem_Ack 1452
|
||||
M_I MEM_Inv 0 <--
|
||||
|
||||
MT_I L1_GET_INSTR 0 <--
|
||||
MT_I L1_GETS 0 <--
|
||||
MT_I L1_GETX 0 <--
|
||||
MT_I L1_UPGRADE 0 <--
|
||||
MT_I L1_PUTX 0 <--
|
||||
MT_I L1_PUTX_old 0 <--
|
||||
MT_I WB_Data 6
|
||||
MT_I WB_Data_clean 0 <--
|
||||
MT_I Ack_all 2
|
||||
MT_I MEM_Inv 0 <--
|
||||
|
||||
MCT_I L1_GET_INSTR 0 <--
|
||||
MCT_I L1_GETS 0 <--
|
||||
MCT_I L1_GETX 0 <--
|
||||
MCT_I L1_UPGRADE 0 <--
|
||||
MCT_I L1_PUTX 0 <--
|
||||
MCT_I L1_PUTX_old 0 <--
|
||||
MCT_I WB_Data 135
|
||||
MCT_I WB_Data_clean 0 <--
|
||||
MCT_I Ack_all 217
|
||||
|
||||
I_I L1_GET_INSTR 0 <--
|
||||
I_I L1_GETS 0 <--
|
||||
I_I L1_GETX 0 <--
|
||||
I_I L1_UPGRADE 0 <--
|
||||
I_I L1_PUTX 0 <--
|
||||
I_I L1_PUTX_old 0 <--
|
||||
I_I Ack 0 <--
|
||||
I_I Ack_all 681
|
||||
|
||||
S_I L1_GET_INSTR 0 <--
|
||||
S_I L1_GETS 0 <--
|
||||
S_I L1_GETX 0 <--
|
||||
S_I L1_UPGRADE 0 <--
|
||||
S_I L1_PUTX 0 <--
|
||||
S_I L1_PUTX_old 0 <--
|
||||
S_I Ack 0 <--
|
||||
S_I Ack_all 0 <--
|
||||
S_I MEM_Inv 0 <--
|
||||
|
||||
ISS L1_GET_INSTR 0 <--
|
||||
ISS L1_GETS 0 <--
|
||||
ISS L1_GETX 0 <--
|
||||
ISS L1_PUTX 0 <--
|
||||
ISS L1_PUTX_old 0 <--
|
||||
ISS L2_Replacement 0 <--
|
||||
ISS L2_Replacement_clean 0 <--
|
||||
ISS Mem_Data 570
|
||||
ISS MEM_Inv 0 <--
|
||||
|
||||
IS L1_GET_INSTR 0 <--
|
||||
IS L1_GETS 0 <--
|
||||
IS L1_GETX 0 <--
|
||||
IS L1_PUTX 0 <--
|
||||
IS L1_PUTX_old 0 <--
|
||||
IS L2_Replacement 0 <--
|
||||
IS L2_Replacement_clean 0 <--
|
||||
IS Mem_Data 686
|
||||
IS MEM_Inv 0 <--
|
||||
|
||||
IM L1_GET_INSTR 0 <--
|
||||
IM L1_GETS 0 <--
|
||||
IM L1_GETX 0 <--
|
||||
IM L1_PUTX 0 <--
|
||||
IM L1_PUTX_old 0 <--
|
||||
IM L2_Replacement 0 <--
|
||||
IM L2_Replacement_clean 0 <--
|
||||
IM Mem_Data 204
|
||||
IM MEM_Inv 0 <--
|
||||
|
||||
SS_MB L1_GET_INSTR 0 <--
|
||||
SS_MB L1_GETS 0 <--
|
||||
SS_MB L1_GETX 0 <--
|
||||
SS_MB L1_UPGRADE 0 <--
|
||||
SS_MB L1_PUTX 0 <--
|
||||
SS_MB L1_PUTX_old 0 <--
|
||||
SS_MB L2_Replacement 0 <--
|
||||
SS_MB L2_Replacement_clean 0 <--
|
||||
SS_MB Unblock_Cancel 0 <--
|
||||
SS_MB Exclusive_Unblock 0 <--
|
||||
SS_MB MEM_Inv 0 <--
|
||||
|
||||
MT_MB L1_GET_INSTR 0 <--
|
||||
MT_MB L1_GETS 0 <--
|
||||
MT_MB L1_GETX 0 <--
|
||||
MT_MB L1_UPGRADE 0 <--
|
||||
MT_MB L1_PUTX 0 <--
|
||||
MT_MB L1_PUTX_old 0 <--
|
||||
MT_MB L2_Replacement 0 <--
|
||||
MT_MB L2_Replacement_clean 0 <--
|
||||
MT_MB Unblock_Cancel 0 <--
|
||||
MT_MB Exclusive_Unblock 799
|
||||
MT_MB MEM_Inv 0 <--
|
||||
|
||||
M_MB L1_GET_INSTR 0 <--
|
||||
M_MB L1_GETS 0 <--
|
||||
M_MB L1_GETX 0 <--
|
||||
M_MB L1_UPGRADE 0 <--
|
||||
M_MB L1_PUTX 0 <--
|
||||
M_MB L1_PUTX_old 0 <--
|
||||
M_MB L2_Replacement 0 <--
|
||||
M_MB L2_Replacement_clean 0 <--
|
||||
M_MB Exclusive_Unblock 0 <--
|
||||
M_MB MEM_Inv 0 <--
|
||||
|
||||
MT_IIB L1_GET_INSTR 0 <--
|
||||
MT_IIB L1_GETS 0 <--
|
||||
MT_IIB L1_GETX 0 <--
|
||||
MT_IIB L1_UPGRADE 0 <--
|
||||
MT_IIB L1_PUTX 0 <--
|
||||
MT_IIB L1_PUTX_old 0 <--
|
||||
MT_IIB L2_Replacement 0 <--
|
||||
MT_IIB L2_Replacement_clean 0 <--
|
||||
MT_IIB WB_Data 0 <--
|
||||
MT_IIB WB_Data_clean 0 <--
|
||||
MT_IIB Unblock 0 <--
|
||||
MT_IIB MEM_Inv 0 <--
|
||||
|
||||
MT_IB L1_GET_INSTR 0 <--
|
||||
MT_IB L1_GETS 0 <--
|
||||
MT_IB L1_GETX 0 <--
|
||||
MT_IB L1_UPGRADE 0 <--
|
||||
MT_IB L1_PUTX 0 <--
|
||||
MT_IB L1_PUTX_old 0 <--
|
||||
MT_IB L2_Replacement 0 <--
|
||||
MT_IB L2_Replacement_clean 0 <--
|
||||
MT_IB WB_Data 0 <--
|
||||
MT_IB WB_Data_clean 0 <--
|
||||
MT_IB Unblock_Cancel 0 <--
|
||||
MT_IB MEM_Inv 0 <--
|
||||
|
||||
MT_SB L1_GET_INSTR 0 <--
|
||||
MT_SB L1_GETS 0 <--
|
||||
MT_SB L1_GETX 0 <--
|
||||
MT_SB L1_UPGRADE 0 <--
|
||||
MT_SB L1_PUTX 0 <--
|
||||
MT_SB L1_PUTX_old 0 <--
|
||||
MT_SB L2_Replacement 0 <--
|
||||
MT_SB L2_Replacement_clean 0 <--
|
||||
MT_SB Unblock 0 <--
|
||||
MT_SB MEM_Inv 0 <--
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
|
||||
memory_total_requests: 1737
|
||||
memory_reads: 1460
|
||||
memory_writes: 277
|
||||
memory_refreshes: 574
|
||||
memory_total_request_delays: 1092
|
||||
memory_delays_per_request: 0.62867
|
||||
memory_delays_in_input_queue: 133
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 959
|
||||
memory_stalls_for_bank_busy: 199
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 32
|
||||
memory_stalls_for_bus: 236
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 492
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 92 21 45 54 57 174 48 18 19 22 35 37 56 59 44 36 41 24 22 28 32 48 122 36 32 25 35 96 114 185 19 61
|
||||
|
||||
--- Directory 0 ---
|
||||
- Event Counts -
|
||||
Fetch 1460
|
||||
Data 277
|
||||
Memory_Data 1460
|
||||
Memory_Ack 277
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
CleanReplacement 1175
|
||||
|
||||
- Transitions -
|
||||
I Fetch 1460
|
||||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
|
||||
ID Fetch 0 <--
|
||||
ID Data 0 <--
|
||||
ID Memory_Data 0 <--
|
||||
ID DMA_READ 0 <--
|
||||
ID DMA_WRITE 0 <--
|
||||
|
||||
ID_W Fetch 0 <--
|
||||
ID_W Data 0 <--
|
||||
ID_W Memory_Ack 0 <--
|
||||
ID_W DMA_READ 0 <--
|
||||
ID_W DMA_WRITE 0 <--
|
||||
|
||||
M Data 277
|
||||
M DMA_READ 0 <--
|
||||
M DMA_WRITE 0 <--
|
||||
M CleanReplacement 1175
|
||||
|
||||
IM Fetch 0 <--
|
||||
IM Data 0 <--
|
||||
IM Memory_Data 1460
|
||||
IM DMA_READ 0 <--
|
||||
IM DMA_WRITE 0 <--
|
||||
|
||||
MI Fetch 0 <--
|
||||
MI Data 0 <--
|
||||
MI Memory_Ack 277
|
||||
MI DMA_READ 0 <--
|
||||
MI DMA_WRITE 0 <--
|
||||
|
||||
M_DRD Data 0 <--
|
||||
M_DRD DMA_READ 0 <--
|
||||
M_DRD DMA_WRITE 0 <--
|
||||
|
||||
M_DRDI Fetch 0 <--
|
||||
M_DRDI Data 0 <--
|
||||
M_DRDI Memory_Ack 0 <--
|
||||
M_DRDI DMA_READ 0 <--
|
||||
M_DRDI DMA_WRITE 0 <--
|
||||
|
||||
M_DWR Data 0 <--
|
||||
M_DWR DMA_READ 0 <--
|
||||
M_DWR DMA_WRITE 0 <--
|
||||
|
||||
M_DWRI Fetch 0 <--
|
||||
M_DWRI Data 0 <--
|
||||
M_DWRI Memory_Ack 0 <--
|
||||
M_DWRI DMA_READ 0 <--
|
||||
M_DWRI DMA_WRITE 0 <--
|
||||
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 28 2010 13:54:58
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 13:57:42
|
||||
M5 executing on svvint03
|
||||
command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 275313 because target called exit()
|
||||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 105206 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 1361416 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_tick_rate 52654853 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 8106 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215916 # Number of bytes of host memory used
|
||||
host_seconds 0.79 # Real time elapsed on the host
|
||||
host_tick_rate 348501 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_seconds 0.000003 # Number of seconds simulated
|
||||
sim_ticks 3215000 # Number of ticks simulated
|
||||
sim_seconds 0.000275 # Number of seconds simulated
|
||||
sim_ticks 275313 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
||||
|
|
@ -29,9 +29,9 @@ system.cpu.itb.data_accesses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 6431 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 6432 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 6414 # ITB hits
|
||||
system.cpu.itb.fetch_hits 6415 # ITB hits
|
||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -42,7 +42,7 @@ system.cpu.itb.write_acv 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 6431 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 275313 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 6404 # Number of instructions executed
|
||||
system.cpu.num_refs 2060 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
|
@ -0,0 +1,277 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
checker=Null
|
||||
clock=1
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
response_latency=2
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links2.ext_node
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links2.ext_node.directory
|
||||
directory_latency=6
|
||||
memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
size=134217728
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=0
|
||||
node_b=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=1
|
||||
node_b=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links2]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=2
|
||||
node_b=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
|
||||
[system.ruby.tracer]
|
||||
type=RubyTracer
|
||||
warmup_length=100000
|
||||
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,3 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 28 2010 14:49:51
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 15:08:13
|
||||
M5 executing on svvint05
|
||||
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 223854 because target called exit()
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 11859 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 216064 # Number of bytes of host memory used
|
||||
host_seconds 0.55 # Real time elapsed on the host
|
||||
host_tick_rate 407003 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_seconds 0.000224 # Number of seconds simulated
|
||||
sim_ticks 223854 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
||||
system.cpu.dtb.data_misses 10 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 1192 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 1185 # DTB read hits
|
||||
system.cpu.dtb.read_misses 7 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 865 # DTB write hits
|
||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 6432 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 6415 # ITB hits
|
||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 223854 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 6404 # Number of instructions executed
|
||||
system.cpu.num_refs 2060 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -0,0 +1,287 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
checker=Null
|
||||
clock=1
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
filtering_enabled=true
|
||||
l2_request_latency=10
|
||||
l2_response_latency=10
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links2.ext_node
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links2.ext_node.directory
|
||||
directory_latency=6
|
||||
distributed_persistent=true
|
||||
fixed_timeout_latency=300
|
||||
l2_select_num_bits=0
|
||||
memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
size=134217728
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=0
|
||||
node_b=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=1
|
||||
node_b=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links2]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=2
|
||||
node_b=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
|
||||
[system.ruby.tracer]
|
||||
type=RubyTracer
|
||||
warmup_length=100000
|
||||
|
||||
|
|
@ -0,0 +1,912 @@
|
|||
|
||||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
RubySystem config:
|
||||
random_seed: 1234
|
||||
randomization: 0
|
||||
cycle_period: 1
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 134217728
|
||||
memory_size_bits: 27
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, unordered
|
||||
virtual_net_2: active, ordered
|
||||
virtual_net_3: active, unordered
|
||||
virtual_net_4: active, unordered
|
||||
virtual_net_5: active, ordered
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
virtual_net_9: inactive
|
||||
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
periodic_stats_period: 1000000
|
||||
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/28/2010 15:55:45
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.43
|
||||
Virtual_time_in_minutes: 0.00716667
|
||||
Virtual_time_in_hours: 0.000119444
|
||||
Virtual_time_in_days: 4.97685e-06
|
||||
|
||||
Ruby_current_time: 236654
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 236654
|
||||
|
||||
mbytes_resident: 34.4141
|
||||
mbytes_total: 34.4219
|
||||
resident_ratio: 1
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
ruby_cycles_executed: 236655 [ 236655 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
L2Cache-0:0
|
||||
Directory-0:0
|
||||
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 279 count: 8464 average: 26.9601 | standard deviation: 58.5578 | 0 7082 0 0 0 0 0 0 0 0 0 0 0 220 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 268 180 200 165 117 12 3 8 3 4 46 30 32 33 37 0 1 1 1 2 1 4 1 3 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_1: [binsize: 2 max: 279 count: 6414 average: 18.8457 | standard deviation: 49.2277 | 0 5768 0 0 0 0 0 0 0 0 0 0 0 55 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 125 84 121 94 59 8 2 4 1 3 20 12 18 22 8 0 1 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 2 max: 279 count: 1185 average: 66.1527 | standard deviation: 80.7635 | 0 660 0 0 0 0 0 0 0 0 0 0 0 99 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 56 67 56 46 4 0 3 2 0 24 12 14 10 10 0 0 0 1 1 1 2 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 2 max: 213 count: 865 average: 33.437 | standard deviation: 63.4371 | 0 654 0 0 0 0 0 0 0 0 0 0 0 66 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 40 12 15 12 0 1 1 0 1 2 6 0 1 19 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 7348
|
||||
page_faults: 2239
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.164956
|
||||
links_utilized_percent_switch_0_link_0: 0.0658979 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.264014 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 1162 83664 [ 0 1162 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 220 15840 [ 0 220 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 38 304 [ 0 38 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 1382 11056 [ 0 0 0 0 1382 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 1220 87840 [ 0 1220 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 134 1072 [ 0 134 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.0968503
|
||||
links_utilized_percent_switch_1_link_0: 0.0660035 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.127697 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 1382 11056 [ 0 0 0 0 1382 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 1220 87840 [ 0 1220 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 134 1072 [ 0 134 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 1180 9440 [ 0 0 0 1180 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 220 15840 [ 0 220 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 38 304 [ 0 38 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 207 14904 [ 0 207 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 983 7864 [ 0 983 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.12111
|
||||
links_utilized_percent_switch_2_link_0: 0.0212652 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.220955 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 1180 9440 [ 0 0 0 1180 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 207 14904 [ 0 207 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 983 7864 [ 0 983 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 1162 83664 [ 0 1162 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 0.204222
|
||||
links_utilized_percent_switch_3_link_0: 0.263592 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.264014 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.0850609 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 1162 83664 [ 0 1162 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 220 15840 [ 0 220 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 38 304 [ 0 38 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Request_Control: 1382 11056 [ 0 0 0 0 1382 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 1220 87840 [ 0 1220 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 134 1072 [ 0 134 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 1180 9440 [ 0 0 0 1180 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 207 14904 [ 0 207 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 983 7864 [ 0 983 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
--- L1Cache 0 ---
|
||||
- Event Counts -
|
||||
Load 1185
|
||||
Ifetch 6414
|
||||
Store 865
|
||||
L1_Replacement 1375
|
||||
Data_Shared 154
|
||||
Data_Owner 0
|
||||
Data_All_Tokens 1228
|
||||
Ack 38
|
||||
Ack_All_Tokens 0
|
||||
Transient_GETX 0
|
||||
Transient_Local_GETX 0
|
||||
Transient_GETS 0
|
||||
Transient_Local_GETS 0
|
||||
Transient_GETS_Last_Token 0
|
||||
Transient_Local_GETS_Last_Token 0
|
||||
Persistent_GETX 0
|
||||
Persistent_GETS 0
|
||||
Own_Lock_or_Unlock 0
|
||||
Request_Timeout 0
|
||||
Use_TimeoutStarverX 0
|
||||
Use_TimeoutStarverS 0
|
||||
Use_TimeoutNoStarvers 1227
|
||||
|
||||
- Transitions -
|
||||
NP Load 525
|
||||
NP Ifetch 646
|
||||
NP Store 191
|
||||
NP Data_Shared 0 <--
|
||||
NP Data_Owner 0 <--
|
||||
NP Data_All_Tokens 0 <--
|
||||
NP Ack 0 <--
|
||||
NP Transient_GETX 0 <--
|
||||
NP Transient_Local_GETX 0 <--
|
||||
NP Transient_GETS 0 <--
|
||||
NP Transient_Local_GETS 0 <--
|
||||
NP Persistent_GETX 0 <--
|
||||
NP Persistent_GETS 0 <--
|
||||
NP Own_Lock_or_Unlock 0 <--
|
||||
|
||||
I Load 0 <--
|
||||
I Ifetch 0 <--
|
||||
I Store 0 <--
|
||||
I L1_Replacement 0 <--
|
||||
I Data_Shared 0 <--
|
||||
I Data_Owner 0 <--
|
||||
I Data_All_Tokens 0 <--
|
||||
I Ack 0 <--
|
||||
I Transient_GETX 0 <--
|
||||
I Transient_Local_GETX 0 <--
|
||||
I Transient_GETS 0 <--
|
||||
I Transient_Local_GETS 0 <--
|
||||
I Transient_GETS_Last_Token 0 <--
|
||||
I Transient_Local_GETS_Last_Token 0 <--
|
||||
I Persistent_GETX 0 <--
|
||||
I Persistent_GETS 0 <--
|
||||
I Own_Lock_or_Unlock 0 <--
|
||||
|
||||
S Load 166
|
||||
S Ifetch 314
|
||||
S Store 20
|
||||
S L1_Replacement 134
|
||||
S Data_Shared 0 <--
|
||||
S Data_Owner 0 <--
|
||||
S Data_All_Tokens 0 <--
|
||||
S Ack 0 <--
|
||||
S Transient_GETX 0 <--
|
||||
S Transient_Local_GETX 0 <--
|
||||
S Transient_GETS 0 <--
|
||||
S Transient_Local_GETS 0 <--
|
||||
S Transient_GETS_Last_Token 0 <--
|
||||
S Transient_Local_GETS_Last_Token 0 <--
|
||||
S Persistent_GETX 0 <--
|
||||
S Persistent_GETS 0 <--
|
||||
S Own_Lock_or_Unlock 0 <--
|
||||
|
||||
O Load 0 <--
|
||||
O Ifetch 0 <--
|
||||
O Store 0 <--
|
||||
O L1_Replacement 0 <--
|
||||
O Data_Shared 0 <--
|
||||
O Data_All_Tokens 0 <--
|
||||
O Ack 0 <--
|
||||
O Ack_All_Tokens 0 <--
|
||||
O Transient_GETX 0 <--
|
||||
O Transient_Local_GETX 0 <--
|
||||
O Transient_GETS 0 <--
|
||||
O Transient_Local_GETS 0 <--
|
||||
O Transient_GETS_Last_Token 0 <--
|
||||
O Transient_Local_GETS_Last_Token 0 <--
|
||||
O Persistent_GETX 0 <--
|
||||
O Persistent_GETS 0 <--
|
||||
O Own_Lock_or_Unlock 0 <--
|
||||
|
||||
M Load 184
|
||||
M Ifetch 3447
|
||||
M Store 33
|
||||
M L1_Replacement 952
|
||||
M Transient_GETX 0 <--
|
||||
M Transient_Local_GETX 0 <--
|
||||
M Transient_GETS 0 <--
|
||||
M Transient_Local_GETS 0 <--
|
||||
M Persistent_GETX 0 <--
|
||||
M Persistent_GETS 0 <--
|
||||
M Own_Lock_or_Unlock 0 <--
|
||||
|
||||
MM Load 221
|
||||
MM Ifetch 0 <--
|
||||
MM Store 333
|
||||
MM L1_Replacement 268
|
||||
MM Transient_GETX 0 <--
|
||||
MM Transient_Local_GETX 0 <--
|
||||
MM Transient_GETS 0 <--
|
||||
MM Transient_Local_GETS 0 <--
|
||||
MM Persistent_GETX 0 <--
|
||||
MM Persistent_GETS 0 <--
|
||||
MM Own_Lock_or_Unlock 0 <--
|
||||
|
||||
M_W Load 69
|
||||
M_W Ifetch 2007
|
||||
M_W Store 25
|
||||
M_W L1_Replacement 14
|
||||
M_W Transient_GETX 0 <--
|
||||
M_W Transient_Local_GETX 0 <--
|
||||
M_W Transient_GETS 0 <--
|
||||
M_W Transient_Local_GETS 0 <--
|
||||
M_W Persistent_GETX 0 <--
|
||||
M_W Persistent_GETS 0 <--
|
||||
M_W Own_Lock_or_Unlock 0 <--
|
||||
M_W Use_TimeoutStarverX 0 <--
|
||||
M_W Use_TimeoutStarverS 0 <--
|
||||
M_W Use_TimeoutNoStarvers 991
|
||||
|
||||
MM_W Load 20
|
||||
MM_W Ifetch 0 <--
|
||||
MM_W Store 263
|
||||
MM_W L1_Replacement 7
|
||||
MM_W Transient_GETX 0 <--
|
||||
MM_W Transient_Local_GETX 0 <--
|
||||
MM_W Transient_GETS 0 <--
|
||||
MM_W Transient_Local_GETS 0 <--
|
||||
MM_W Persistent_GETX 0 <--
|
||||
MM_W Persistent_GETS 0 <--
|
||||
MM_W Own_Lock_or_Unlock 0 <--
|
||||
MM_W Use_TimeoutStarverX 0 <--
|
||||
MM_W Use_TimeoutStarverS 0 <--
|
||||
MM_W Use_TimeoutNoStarvers 236
|
||||
|
||||
IM Load 0 <--
|
||||
IM Ifetch 0 <--
|
||||
IM Store 0 <--
|
||||
IM L1_Replacement 0 <--
|
||||
IM Data_Shared 0 <--
|
||||
IM Data_Owner 0 <--
|
||||
IM Data_All_Tokens 191
|
||||
IM Ack 7
|
||||
IM Transient_GETX 0 <--
|
||||
IM Transient_Local_GETX 0 <--
|
||||
IM Transient_GETS 0 <--
|
||||
IM Transient_Local_GETS 0 <--
|
||||
IM Transient_GETS_Last_Token 0 <--
|
||||
IM Transient_Local_GETS_Last_Token 0 <--
|
||||
IM Persistent_GETX 0 <--
|
||||
IM Persistent_GETS 0 <--
|
||||
IM Own_Lock_or_Unlock 0 <--
|
||||
IM Request_Timeout 0 <--
|
||||
|
||||
SM Load 0 <--
|
||||
SM Ifetch 0 <--
|
||||
SM Store 0 <--
|
||||
SM L1_Replacement 0 <--
|
||||
SM Data_Shared 0 <--
|
||||
SM Data_Owner 0 <--
|
||||
SM Data_All_Tokens 20
|
||||
SM Ack 0 <--
|
||||
SM Transient_GETX 0 <--
|
||||
SM Transient_Local_GETX 0 <--
|
||||
SM Transient_GETS 0 <--
|
||||
SM Transient_Local_GETS 0 <--
|
||||
SM Transient_GETS_Last_Token 0 <--
|
||||
SM Transient_Local_GETS_Last_Token 0 <--
|
||||
SM Persistent_GETX 0 <--
|
||||
SM Persistent_GETS 0 <--
|
||||
SM Own_Lock_or_Unlock 0 <--
|
||||
SM Request_Timeout 0 <--
|
||||
|
||||
OM Load 0 <--
|
||||
OM Ifetch 0 <--
|
||||
OM Store 0 <--
|
||||
OM L1_Replacement 0 <--
|
||||
OM Data_Shared 0 <--
|
||||
OM Data_All_Tokens 0 <--
|
||||
OM Ack 0 <--
|
||||
OM Ack_All_Tokens 0 <--
|
||||
OM Transient_GETX 0 <--
|
||||
OM Transient_Local_GETX 0 <--
|
||||
OM Transient_GETS 0 <--
|
||||
OM Transient_Local_GETS 0 <--
|
||||
OM Transient_GETS_Last_Token 0 <--
|
||||
OM Transient_Local_GETS_Last_Token 0 <--
|
||||
OM Persistent_GETX 0 <--
|
||||
OM Persistent_GETS 0 <--
|
||||
OM Own_Lock_or_Unlock 0 <--
|
||||
OM Request_Timeout 0 <--
|
||||
|
||||
IS Load 0 <--
|
||||
IS Ifetch 0 <--
|
||||
IS Store 0 <--
|
||||
IS L1_Replacement 0 <--
|
||||
IS Data_Shared 154
|
||||
IS Data_Owner 0 <--
|
||||
IS Data_All_Tokens 1017
|
||||
IS Ack 31
|
||||
IS Transient_GETX 0 <--
|
||||
IS Transient_Local_GETX 0 <--
|
||||
IS Transient_GETS 0 <--
|
||||
IS Transient_Local_GETS 0 <--
|
||||
IS Transient_GETS_Last_Token 0 <--
|
||||
IS Transient_Local_GETS_Last_Token 0 <--
|
||||
IS Persistent_GETX 0 <--
|
||||
IS Persistent_GETS 0 <--
|
||||
IS Own_Lock_or_Unlock 0 <--
|
||||
IS Request_Timeout 0 <--
|
||||
|
||||
I_L Load 0 <--
|
||||
I_L Ifetch 0 <--
|
||||
I_L Store 0 <--
|
||||
I_L L1_Replacement 0 <--
|
||||
I_L Data_Shared 0 <--
|
||||
I_L Data_Owner 0 <--
|
||||
I_L Data_All_Tokens 0 <--
|
||||
I_L Ack 0 <--
|
||||
I_L Transient_GETX 0 <--
|
||||
I_L Transient_Local_GETX 0 <--
|
||||
I_L Transient_GETS 0 <--
|
||||
I_L Transient_Local_GETS 0 <--
|
||||
I_L Transient_GETS_Last_Token 0 <--
|
||||
I_L Transient_Local_GETS_Last_Token 0 <--
|
||||
I_L Persistent_GETX 0 <--
|
||||
I_L Persistent_GETS 0 <--
|
||||
I_L Own_Lock_or_Unlock 0 <--
|
||||
|
||||
S_L Load 0 <--
|
||||
S_L Ifetch 0 <--
|
||||
S_L Store 0 <--
|
||||
S_L L1_Replacement 0 <--
|
||||
S_L Data_Shared 0 <--
|
||||
S_L Data_Owner 0 <--
|
||||
S_L Data_All_Tokens 0 <--
|
||||
S_L Ack 0 <--
|
||||
S_L Transient_GETX 0 <--
|
||||
S_L Transient_Local_GETX 0 <--
|
||||
S_L Transient_GETS 0 <--
|
||||
S_L Transient_Local_GETS 0 <--
|
||||
S_L Transient_GETS_Last_Token 0 <--
|
||||
S_L Transient_Local_GETS_Last_Token 0 <--
|
||||
S_L Persistent_GETX 0 <--
|
||||
S_L Persistent_GETS 0 <--
|
||||
S_L Own_Lock_or_Unlock 0 <--
|
||||
|
||||
IM_L Load 0 <--
|
||||
IM_L Ifetch 0 <--
|
||||
IM_L Store 0 <--
|
||||
IM_L L1_Replacement 0 <--
|
||||
IM_L Data_Shared 0 <--
|
||||
IM_L Data_Owner 0 <--
|
||||
IM_L Data_All_Tokens 0 <--
|
||||
IM_L Ack 0 <--
|
||||
IM_L Transient_GETX 0 <--
|
||||
IM_L Transient_Local_GETX 0 <--
|
||||
IM_L Transient_GETS 0 <--
|
||||
IM_L Transient_Local_GETS 0 <--
|
||||
IM_L Transient_GETS_Last_Token 0 <--
|
||||
IM_L Transient_Local_GETS_Last_Token 0 <--
|
||||
IM_L Persistent_GETX 0 <--
|
||||
IM_L Persistent_GETS 0 <--
|
||||
IM_L Own_Lock_or_Unlock 0 <--
|
||||
IM_L Request_Timeout 0 <--
|
||||
|
||||
SM_L Load 0 <--
|
||||
SM_L Ifetch 0 <--
|
||||
SM_L Store 0 <--
|
||||
SM_L L1_Replacement 0 <--
|
||||
SM_L Data_Shared 0 <--
|
||||
SM_L Data_Owner 0 <--
|
||||
SM_L Data_All_Tokens 0 <--
|
||||
SM_L Ack 0 <--
|
||||
SM_L Transient_GETX 0 <--
|
||||
SM_L Transient_Local_GETX 0 <--
|
||||
SM_L Transient_GETS 0 <--
|
||||
SM_L Transient_Local_GETS 0 <--
|
||||
SM_L Transient_GETS_Last_Token 0 <--
|
||||
SM_L Transient_Local_GETS_Last_Token 0 <--
|
||||
SM_L Persistent_GETX 0 <--
|
||||
SM_L Persistent_GETS 0 <--
|
||||
SM_L Own_Lock_or_Unlock 0 <--
|
||||
SM_L Request_Timeout 0 <--
|
||||
|
||||
IS_L Load 0 <--
|
||||
IS_L Ifetch 0 <--
|
||||
IS_L Store 0 <--
|
||||
IS_L L1_Replacement 0 <--
|
||||
IS_L Data_Shared 0 <--
|
||||
IS_L Data_Owner 0 <--
|
||||
IS_L Data_All_Tokens 0 <--
|
||||
IS_L Ack 0 <--
|
||||
IS_L Transient_GETX 0 <--
|
||||
IS_L Transient_Local_GETX 0 <--
|
||||
IS_L Transient_GETS 0 <--
|
||||
IS_L Transient_Local_GETS 0 <--
|
||||
IS_L Transient_GETS_Last_Token 0 <--
|
||||
IS_L Transient_Local_GETS_Last_Token 0 <--
|
||||
IS_L Persistent_GETX 0 <--
|
||||
IS_L Persistent_GETS 0 <--
|
||||
IS_L Own_Lock_or_Unlock 0 <--
|
||||
IS_L Request_Timeout 0 <--
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
--- L2Cache 0 ---
|
||||
- Event Counts -
|
||||
L1_GETS 1140
|
||||
L1_GETS_Last_Token 31
|
||||
L1_GETX 211
|
||||
L1_INV 0
|
||||
Transient_GETX 0
|
||||
Transient_GETS 0
|
||||
Transient_GETS_Last_Token 0
|
||||
L2_Replacement 1276
|
||||
Writeback_Tokens 82
|
||||
Writeback_Shared_Data 0
|
||||
Writeback_All_Tokens 1272
|
||||
Writeback_Owned 0
|
||||
Data_Shared 0
|
||||
Data_Owner 0
|
||||
Data_All_Tokens 0
|
||||
Ack 0
|
||||
Ack_All_Tokens 0
|
||||
Persistent_GETX 0
|
||||
Persistent_GETS 0
|
||||
Own_Lock_or_Unlock 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GETS 986
|
||||
NP L1_GETX 138
|
||||
NP L1_INV 0 <--
|
||||
NP Transient_GETX 0 <--
|
||||
NP Transient_GETS 0 <--
|
||||
NP Writeback_Tokens 82
|
||||
NP Writeback_Shared_Data 0 <--
|
||||
NP Writeback_All_Tokens 1202
|
||||
NP Writeback_Owned 0 <--
|
||||
NP Data_Shared 0 <--
|
||||
NP Data_Owner 0 <--
|
||||
NP Data_All_Tokens 0 <--
|
||||
NP Ack 0 <--
|
||||
NP Persistent_GETX 0 <--
|
||||
NP Persistent_GETS 0 <--
|
||||
NP Own_Lock_or_Unlock 0 <--
|
||||
|
||||
I L1_GETS 0 <--
|
||||
I L1_GETS_Last_Token 31
|
||||
I L1_GETX 7
|
||||
I L1_INV 0 <--
|
||||
I Transient_GETX 0 <--
|
||||
I Transient_GETS 0 <--
|
||||
I Transient_GETS_Last_Token 0 <--
|
||||
I L2_Replacement 130
|
||||
I Writeback_Tokens 0 <--
|
||||
I Writeback_Shared_Data 0 <--
|
||||
I Writeback_All_Tokens 18
|
||||
I Writeback_Owned 0 <--
|
||||
I Data_Shared 0 <--
|
||||
I Data_Owner 0 <--
|
||||
I Data_All_Tokens 0 <--
|
||||
I Ack 0 <--
|
||||
I Persistent_GETX 0 <--
|
||||
I Persistent_GETS 0 <--
|
||||
I Own_Lock_or_Unlock 0 <--
|
||||
|
||||
S L1_GETS 0 <--
|
||||
S L1_GETS_Last_Token 0 <--
|
||||
S L1_GETX 0 <--
|
||||
S L1_INV 0 <--
|
||||
S Transient_GETX 0 <--
|
||||
S Transient_GETS 0 <--
|
||||
S Transient_GETS_Last_Token 0 <--
|
||||
S L2_Replacement 0 <--
|
||||
S Writeback_Tokens 0 <--
|
||||
S Writeback_Shared_Data 0 <--
|
||||
S Writeback_All_Tokens 0 <--
|
||||
S Writeback_Owned 0 <--
|
||||
S Data_Shared 0 <--
|
||||
S Data_Owner 0 <--
|
||||
S Data_All_Tokens 0 <--
|
||||
S Ack 0 <--
|
||||
S Persistent_GETX 0 <--
|
||||
S Persistent_GETS 0 <--
|
||||
S Own_Lock_or_Unlock 0 <--
|
||||
|
||||
O L1_GETS 0 <--
|
||||
O L1_GETS_Last_Token 0 <--
|
||||
O L1_GETX 18
|
||||
O L1_INV 0 <--
|
||||
O Transient_GETX 0 <--
|
||||
O Transient_GETS 0 <--
|
||||
O Transient_GETS_Last_Token 0 <--
|
||||
O L2_Replacement 84
|
||||
O Writeback_Tokens 0 <--
|
||||
O Writeback_Shared_Data 0 <--
|
||||
O Writeback_All_Tokens 52
|
||||
O Data_Shared 0 <--
|
||||
O Data_All_Tokens 0 <--
|
||||
O Ack 0 <--
|
||||
O Ack_All_Tokens 0 <--
|
||||
O Persistent_GETX 0 <--
|
||||
O Persistent_GETS 0 <--
|
||||
O Own_Lock_or_Unlock 0 <--
|
||||
|
||||
M L1_GETS 154
|
||||
M L1_GETX 48
|
||||
M L1_INV 0 <--
|
||||
M Transient_GETX 0 <--
|
||||
M Transient_GETS 0 <--
|
||||
M L2_Replacement 1062
|
||||
M Persistent_GETX 0 <--
|
||||
M Persistent_GETS 0 <--
|
||||
M Own_Lock_or_Unlock 0 <--
|
||||
|
||||
I_L L1_GETS 0 <--
|
||||
I_L L1_GETX 0 <--
|
||||
I_L L1_INV 0 <--
|
||||
I_L Transient_GETX 0 <--
|
||||
I_L Transient_GETS 0 <--
|
||||
I_L Transient_GETS_Last_Token 0 <--
|
||||
I_L L2_Replacement 0 <--
|
||||
I_L Writeback_Tokens 0 <--
|
||||
I_L Writeback_Shared_Data 0 <--
|
||||
I_L Writeback_All_Tokens 0 <--
|
||||
I_L Writeback_Owned 0 <--
|
||||
I_L Data_Shared 0 <--
|
||||
I_L Data_Owner 0 <--
|
||||
I_L Data_All_Tokens 0 <--
|
||||
I_L Ack 0 <--
|
||||
I_L Persistent_GETX 0 <--
|
||||
I_L Persistent_GETS 0 <--
|
||||
I_L Own_Lock_or_Unlock 0 <--
|
||||
|
||||
S_L L1_GETS 0 <--
|
||||
S_L L1_GETS_Last_Token 0 <--
|
||||
S_L L1_GETX 0 <--
|
||||
S_L L1_INV 0 <--
|
||||
S_L Transient_GETX 0 <--
|
||||
S_L Transient_GETS 0 <--
|
||||
S_L Transient_GETS_Last_Token 0 <--
|
||||
S_L L2_Replacement 0 <--
|
||||
S_L Writeback_Tokens 0 <--
|
||||
S_L Writeback_Shared_Data 0 <--
|
||||
S_L Writeback_All_Tokens 0 <--
|
||||
S_L Writeback_Owned 0 <--
|
||||
S_L Data_Shared 0 <--
|
||||
S_L Data_Owner 0 <--
|
||||
S_L Data_All_Tokens 0 <--
|
||||
S_L Ack 0 <--
|
||||
S_L Persistent_GETX 0 <--
|
||||
S_L Persistent_GETS 0 <--
|
||||
S_L Own_Lock_or_Unlock 0 <--
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
|
||||
memory_total_requests: 1369
|
||||
memory_reads: 1162
|
||||
memory_writes: 207
|
||||
memory_refreshes: 493
|
||||
memory_total_request_delays: 529
|
||||
memory_delays_per_request: 0.386413
|
||||
memory_delays_in_input_queue: 185
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 344
|
||||
memory_stalls_for_bank_busy: 101
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 19
|
||||
memory_stalls_for_bus: 222
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 2
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 75 17 45 46 54 108 37 16 19 22 32 34 52 49 39 31 39 21 21 21 28 38 61 27 30 22 32 72 90 124 14 53
|
||||
|
||||
--- Directory 0 ---
|
||||
- Event Counts -
|
||||
GETX 163
|
||||
GETS 1017
|
||||
Lockdown 0
|
||||
Unlockdown 0
|
||||
Own_Lock_or_Unlock 0
|
||||
Data_Owner 19
|
||||
Data_All_Tokens 188
|
||||
Ack_Owner 65
|
||||
Ack_Owner_All_Tokens 874
|
||||
Tokens 0
|
||||
Ack_All_Tokens 44
|
||||
Request_Timeout 0
|
||||
Memory_Data 1162
|
||||
Memory_Ack 207
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
DMA_WRITE_All_Tokens 0
|
||||
|
||||
- Transitions -
|
||||
O GETX 145
|
||||
O GETS 1017
|
||||
O Lockdown 0 <--
|
||||
O Own_Lock_or_Unlock 0 <--
|
||||
O Data_Owner 0 <--
|
||||
O Data_All_Tokens 0 <--
|
||||
O Tokens 0 <--
|
||||
O Ack_All_Tokens 44
|
||||
O DMA_READ 0 <--
|
||||
O DMA_WRITE 0 <--
|
||||
O DMA_WRITE_All_Tokens 0 <--
|
||||
|
||||
NO GETX 18
|
||||
NO GETS 0 <--
|
||||
NO Lockdown 0 <--
|
||||
NO Own_Lock_or_Unlock 0 <--
|
||||
NO Data_Owner 19
|
||||
NO Data_All_Tokens 188
|
||||
NO Ack_Owner 65
|
||||
NO Ack_Owner_All_Tokens 874
|
||||
NO Tokens 0 <--
|
||||
NO DMA_READ 0 <--
|
||||
NO DMA_WRITE 0 <--
|
||||
|
||||
L GETX 0 <--
|
||||
L GETS 0 <--
|
||||
L Lockdown 0 <--
|
||||
L Unlockdown 0 <--
|
||||
L Own_Lock_or_Unlock 0 <--
|
||||
L Data_Owner 0 <--
|
||||
L Data_All_Tokens 0 <--
|
||||
L Ack_Owner 0 <--
|
||||
L Ack_Owner_All_Tokens 0 <--
|
||||
L Tokens 0 <--
|
||||
L DMA_READ 0 <--
|
||||
L DMA_WRITE 0 <--
|
||||
|
||||
O_W GETX 0 <--
|
||||
O_W GETS 0 <--
|
||||
O_W Lockdown 0 <--
|
||||
O_W Unlockdown 0 <--
|
||||
O_W Own_Lock_or_Unlock 0 <--
|
||||
O_W Data_Owner 0 <--
|
||||
O_W Ack_Owner 0 <--
|
||||
O_W Tokens 0 <--
|
||||
O_W Ack_All_Tokens 0 <--
|
||||
O_W Memory_Data 0 <--
|
||||
O_W Memory_Ack 207
|
||||
O_W DMA_READ 0 <--
|
||||
O_W DMA_WRITE 0 <--
|
||||
|
||||
L_O_W GETX 0 <--
|
||||
L_O_W GETS 0 <--
|
||||
L_O_W Lockdown 0 <--
|
||||
L_O_W Unlockdown 0 <--
|
||||
L_O_W Own_Lock_or_Unlock 0 <--
|
||||
L_O_W Data_Owner 0 <--
|
||||
L_O_W Ack_Owner 0 <--
|
||||
L_O_W Tokens 0 <--
|
||||
L_O_W Ack_All_Tokens 0 <--
|
||||
L_O_W Memory_Data 0 <--
|
||||
L_O_W Memory_Ack 0 <--
|
||||
L_O_W DMA_READ 0 <--
|
||||
L_O_W DMA_WRITE 0 <--
|
||||
|
||||
L_NO_W GETX 0 <--
|
||||
L_NO_W GETS 0 <--
|
||||
L_NO_W Lockdown 0 <--
|
||||
L_NO_W Unlockdown 0 <--
|
||||
L_NO_W Own_Lock_or_Unlock 0 <--
|
||||
L_NO_W Data_Owner 0 <--
|
||||
L_NO_W Ack_Owner 0 <--
|
||||
L_NO_W Tokens 0 <--
|
||||
L_NO_W Ack_All_Tokens 0 <--
|
||||
L_NO_W Memory_Data 0 <--
|
||||
L_NO_W DMA_READ 0 <--
|
||||
L_NO_W DMA_WRITE 0 <--
|
||||
|
||||
DR_L_W GETX 0 <--
|
||||
DR_L_W GETS 0 <--
|
||||
DR_L_W Lockdown 0 <--
|
||||
DR_L_W Unlockdown 0 <--
|
||||
DR_L_W Own_Lock_or_Unlock 0 <--
|
||||
DR_L_W Data_Owner 0 <--
|
||||
DR_L_W Ack_Owner 0 <--
|
||||
DR_L_W Tokens 0 <--
|
||||
DR_L_W Ack_All_Tokens 0 <--
|
||||
DR_L_W Request_Timeout 0 <--
|
||||
DR_L_W Memory_Data 0 <--
|
||||
DR_L_W DMA_READ 0 <--
|
||||
DR_L_W DMA_WRITE 0 <--
|
||||
|
||||
NO_W GETX 0 <--
|
||||
NO_W GETS 0 <--
|
||||
NO_W Lockdown 0 <--
|
||||
NO_W Unlockdown 0 <--
|
||||
NO_W Own_Lock_or_Unlock 0 <--
|
||||
NO_W Data_Owner 0 <--
|
||||
NO_W Ack_Owner 0 <--
|
||||
NO_W Tokens 0 <--
|
||||
NO_W Ack_All_Tokens 0 <--
|
||||
NO_W Memory_Data 1162
|
||||
NO_W DMA_READ 0 <--
|
||||
NO_W DMA_WRITE 0 <--
|
||||
|
||||
O_DW_W GETX 0 <--
|
||||
O_DW_W GETS 0 <--
|
||||
O_DW_W Data_Owner 0 <--
|
||||
O_DW_W Ack_Owner 0 <--
|
||||
O_DW_W Tokens 0 <--
|
||||
O_DW_W Ack_All_Tokens 0 <--
|
||||
O_DW_W Memory_Ack 0 <--
|
||||
O_DW_W DMA_READ 0 <--
|
||||
O_DW_W DMA_WRITE 0 <--
|
||||
|
||||
O_DR_W GETX 0 <--
|
||||
O_DR_W GETS 0 <--
|
||||
O_DR_W Lockdown 0 <--
|
||||
O_DR_W Unlockdown 0 <--
|
||||
O_DR_W Own_Lock_or_Unlock 0 <--
|
||||
O_DR_W Data_Owner 0 <--
|
||||
O_DR_W Ack_Owner 0 <--
|
||||
O_DR_W Tokens 0 <--
|
||||
O_DR_W Ack_All_Tokens 0 <--
|
||||
O_DR_W Memory_Data 0 <--
|
||||
O_DR_W DMA_READ 0 <--
|
||||
O_DR_W DMA_WRITE 0 <--
|
||||
|
||||
O_DW GETX 0 <--
|
||||
O_DW GETS 0 <--
|
||||
O_DW Lockdown 0 <--
|
||||
O_DW Own_Lock_or_Unlock 0 <--
|
||||
O_DW Data_Owner 0 <--
|
||||
O_DW Data_All_Tokens 0 <--
|
||||
O_DW Ack_Owner 0 <--
|
||||
O_DW Ack_Owner_All_Tokens 0 <--
|
||||
O_DW Tokens 0 <--
|
||||
O_DW Ack_All_Tokens 0 <--
|
||||
O_DW DMA_READ 0 <--
|
||||
O_DW DMA_WRITE 0 <--
|
||||
|
||||
NO_DW GETX 0 <--
|
||||
NO_DW GETS 0 <--
|
||||
NO_DW Lockdown 0 <--
|
||||
NO_DW Own_Lock_or_Unlock 0 <--
|
||||
NO_DW Data_Owner 0 <--
|
||||
NO_DW Data_All_Tokens 0 <--
|
||||
NO_DW Tokens 0 <--
|
||||
NO_DW Request_Timeout 0 <--
|
||||
NO_DW DMA_READ 0 <--
|
||||
NO_DW DMA_WRITE 0 <--
|
||||
|
||||
NO_DR GETX 0 <--
|
||||
NO_DR GETS 0 <--
|
||||
NO_DR Lockdown 0 <--
|
||||
NO_DR Own_Lock_or_Unlock 0 <--
|
||||
NO_DR Data_Owner 0 <--
|
||||
NO_DR Data_All_Tokens 0 <--
|
||||
NO_DR Tokens 0 <--
|
||||
NO_DR Request_Timeout 0 <--
|
||||
NO_DR DMA_READ 0 <--
|
||||
NO_DR DMA_WRITE 0 <--
|
||||
|
||||
DW_L GETX 0 <--
|
||||
DW_L GETS 0 <--
|
||||
DW_L Lockdown 0 <--
|
||||
DW_L Unlockdown 0 <--
|
||||
DW_L Own_Lock_or_Unlock 0 <--
|
||||
DW_L Data_Owner 0 <--
|
||||
DW_L Data_All_Tokens 0 <--
|
||||
DW_L Ack_Owner 0 <--
|
||||
DW_L Ack_Owner_All_Tokens 0 <--
|
||||
DW_L Tokens 0 <--
|
||||
DW_L Request_Timeout 0 <--
|
||||
DW_L DMA_READ 0 <--
|
||||
DW_L DMA_WRITE 0 <--
|
||||
|
||||
DR_L GETX 0 <--
|
||||
DR_L GETS 0 <--
|
||||
DR_L Lockdown 0 <--
|
||||
DR_L Unlockdown 0 <--
|
||||
DR_L Own_Lock_or_Unlock 0 <--
|
||||
DR_L Data_Owner 0 <--
|
||||
DR_L Data_All_Tokens 0 <--
|
||||
DR_L Ack_Owner 0 <--
|
||||
DR_L Ack_Owner_All_Tokens 0 <--
|
||||
DR_L Tokens 0 <--
|
||||
DR_L Request_Timeout 0 <--
|
||||
DR_L DMA_READ 0 <--
|
||||
DR_L DMA_WRITE 0 <--
|
||||
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 28 2010 15:54:34
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 15:55:45
|
||||
M5 executing on svvint04
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 236654 because target called exit()
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 35577 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215884 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
host_tick_rate 1314701 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_seconds 0.000237 # Number of seconds simulated
|
||||
sim_ticks 236654 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
||||
system.cpu.dtb.data_misses 10 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 1192 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 1185 # DTB read hits
|
||||
system.cpu.dtb.read_misses 7 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 865 # DTB write hits
|
||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 6432 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 6415 # ITB hits
|
||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 236654 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 6404 # Number of instructions executed
|
||||
system.cpu.num_refs 2060 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -0,0 +1,249 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
checker=Null
|
||||
clock=1
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links1.ext_node.directory
|
||||
memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
|
||||
memory_controller_latency=12
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
size=134217728
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=0
|
||||
node_b=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=1
|
||||
node_b=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
|
||||
[system.ruby.tracer]
|
||||
type=RubyTracer
|
||||
warmup_length=100000
|
||||
|
||||
|
|
@ -0,0 +1,576 @@
|
|||
|
||||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
RubySystem config:
|
||||
random_seed: 1234
|
||||
randomization: 0
|
||||
cycle_period: 1
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 134217728
|
||||
memory_size_bits: 27
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, unordered
|
||||
virtual_net_1: active, unordered
|
||||
virtual_net_2: active, unordered
|
||||
virtual_net_3: active, unordered
|
||||
virtual_net_4: active, ordered
|
||||
virtual_net_5: active, ordered
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
virtual_net_9: inactive
|
||||
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
periodic_stats_period: 1000000
|
||||
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/28/2010 11:55:11
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.39
|
||||
Virtual_time_in_minutes: 0.0065
|
||||
Virtual_time_in_hours: 0.000108333
|
||||
Virtual_time_in_days: 4.51389e-06
|
||||
|
||||
Ruby_current_time: 215528
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 215528
|
||||
|
||||
mbytes_resident: 33.1406
|
||||
mbytes_total: 33.1484
|
||||
resident_ratio: 1
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
ruby_cycles_executed: 215529 [ 215529 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
Directory-0:0
|
||||
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 377 count: 8464 average: 24.4641 | standard deviation: 54.9689 | 0 7305 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 199 174 167 309 200 14 3 4 1 4 0 15 1 5 2 1 0 0 0 1 3 4 4 7 1 1 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 1 0 1 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 15 4 1 1 0 2 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
|
||||
miss_latency_1: [binsize: 2 max: 261 count: 6414 average: 16.7424 | standard deviation: 43.645 | 0 5833 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111 113 72 159 92 10 2 2 1 2 0 0 0 1 0 0 0 0 0 1 3 1 4 3 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 2 max: 333 count: 1185 average: 57.908 | standard deviation: 75.2483 | 0 765 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 52 60 116 72 4 1 0 0 1 0 12 1 2 2 1 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 2 max: 377 count: 865 average: 35.904 | standard deviation: 74.7708 | 0 707 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 9 35 34 36 0 0 2 0 1 0 3 0 2 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 14 3 1 0 0 2 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 7120
|
||||
page_faults: 2128
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.107382
|
||||
links_utilized_percent_switch_0_link_0: 0.0671258 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.147637 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 1159 83448 [ 0 1159 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 1143 9144 [ 0 0 1143 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 1159 9272 [ 0 0 0 1159 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 220 15840 [ 220 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 2066 16528 [ 923 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 1159 9272 [ 1159 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.152706
|
||||
links_utilized_percent_switch_1_link_0: 0.0369094 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.268503 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 1159 9272 [ 0 0 0 1159 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 220 15840 [ 220 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 2066 16528 [ 923 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Unblock_Control: 1159 9272 [ 1159 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1159 83448 [ 0 1159 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 1143 9144 [ 0 0 1143 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.20807
|
||||
links_utilized_percent_switch_2_link_0: 0.268503 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.147637 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 1159 83448 [ 0 1159 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 1143 9144 [ 0 0 1143 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 1159 9272 [ 0 0 0 1159 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 220 15840 [ 220 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 923 0 0 1143 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 1159 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 581
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 581
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 100%
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 581 100%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 4 count: 581 average: 4 | standard deviation: 0 | 0 0 0 0 581 ]
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 578
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 578
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: inf
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_LD: 72.6644%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_ST: 27.3356%
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 578 100%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 8 count: 578 average: 7.5917 | standard deviation: 1.2123 | 0 0 0 0 59 0 0 0 519 ]
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
--- L1Cache 0 ---
|
||||
- Event Counts -
|
||||
Load 1209
|
||||
Ifetch 6447
|
||||
Store 946
|
||||
L2_Replacement 1143
|
||||
L1_to_L2 1354
|
||||
L2_to_L1D 138
|
||||
L2_to_L1I 65
|
||||
Other_GETX 0
|
||||
Other_GETS 0
|
||||
Ack 0
|
||||
Shared_Ack 0
|
||||
Data 0
|
||||
Shared_Data 0
|
||||
Exclusive_Data 1159
|
||||
Writeback_Ack 1143
|
||||
Writeback_Nack 0
|
||||
All_acks 0
|
||||
All_acks_no_sharers 1159
|
||||
|
||||
- Transitions -
|
||||
I Load 420
|
||||
I Ifetch 581
|
||||
I Store 158
|
||||
I L2_Replacement 0 <--
|
||||
I L1_to_L2 0 <--
|
||||
I L2_to_L1D 0 <--
|
||||
I L2_to_L1I 0 <--
|
||||
I Other_GETX 0 <--
|
||||
I Other_GETS 0 <--
|
||||
|
||||
S Load 0 <--
|
||||
S Ifetch 0 <--
|
||||
S Store 0 <--
|
||||
S L2_Replacement 0 <--
|
||||
S L1_to_L2 0 <--
|
||||
S L2_to_L1D 0 <--
|
||||
S L2_to_L1I 0 <--
|
||||
S Other_GETX 0 <--
|
||||
S Other_GETS 0 <--
|
||||
|
||||
O Load 0 <--
|
||||
O Ifetch 0 <--
|
||||
O Store 0 <--
|
||||
O L2_Replacement 0 <--
|
||||
O L1_to_L2 0 <--
|
||||
O L2_to_L1D 0 <--
|
||||
O L2_to_L1I 0 <--
|
||||
O Other_GETX 0 <--
|
||||
O Other_GETS 0 <--
|
||||
|
||||
M Load 368
|
||||
M Ifetch 5833
|
||||
M Store 66
|
||||
M L2_Replacement 923
|
||||
M L1_to_L2 1061
|
||||
M L2_to_L1D 68
|
||||
M L2_to_L1I 65
|
||||
M Other_GETX 0 <--
|
||||
M Other_GETS 0 <--
|
||||
|
||||
MM Load 397
|
||||
MM Ifetch 0 <--
|
||||
MM Store 641
|
||||
MM L2_Replacement 220
|
||||
MM L1_to_L2 293
|
||||
MM L2_to_L1D 70
|
||||
MM L2_to_L1I 0 <--
|
||||
MM Other_GETX 0 <--
|
||||
MM Other_GETS 0 <--
|
||||
|
||||
IM Load 0 <--
|
||||
IM Ifetch 0 <--
|
||||
IM Store 0 <--
|
||||
IM L2_Replacement 0 <--
|
||||
IM L1_to_L2 0 <--
|
||||
IM Other_GETX 0 <--
|
||||
IM Other_GETS 0 <--
|
||||
IM Ack 0 <--
|
||||
IM Data 0 <--
|
||||
IM Exclusive_Data 158
|
||||
|
||||
SM Load 0 <--
|
||||
SM Ifetch 0 <--
|
||||
SM Store 0 <--
|
||||
SM L2_Replacement 0 <--
|
||||
SM L1_to_L2 0 <--
|
||||
SM Other_GETX 0 <--
|
||||
SM Other_GETS 0 <--
|
||||
SM Ack 0 <--
|
||||
SM Data 0 <--
|
||||
|
||||
OM Load 0 <--
|
||||
OM Ifetch 0 <--
|
||||
OM Store 0 <--
|
||||
OM L2_Replacement 0 <--
|
||||
OM L1_to_L2 0 <--
|
||||
OM Other_GETX 0 <--
|
||||
OM Other_GETS 0 <--
|
||||
OM Ack 0 <--
|
||||
OM All_acks 0 <--
|
||||
OM All_acks_no_sharers 0 <--
|
||||
|
||||
ISM Load 0 <--
|
||||
ISM Ifetch 0 <--
|
||||
ISM Store 0 <--
|
||||
ISM L2_Replacement 0 <--
|
||||
ISM L1_to_L2 0 <--
|
||||
ISM Ack 0 <--
|
||||
ISM All_acks_no_sharers 0 <--
|
||||
|
||||
M_W Load 0 <--
|
||||
M_W Ifetch 0 <--
|
||||
M_W Store 0 <--
|
||||
M_W L2_Replacement 0 <--
|
||||
M_W L1_to_L2 0 <--
|
||||
M_W Ack 0 <--
|
||||
M_W All_acks_no_sharers 1001
|
||||
|
||||
MM_W Load 0 <--
|
||||
MM_W Ifetch 0 <--
|
||||
MM_W Store 0 <--
|
||||
MM_W L2_Replacement 0 <--
|
||||
MM_W L1_to_L2 0 <--
|
||||
MM_W Ack 0 <--
|
||||
MM_W All_acks_no_sharers 158
|
||||
|
||||
IS Load 0 <--
|
||||
IS Ifetch 0 <--
|
||||
IS Store 0 <--
|
||||
IS L2_Replacement 0 <--
|
||||
IS L1_to_L2 0 <--
|
||||
IS Other_GETX 0 <--
|
||||
IS Other_GETS 0 <--
|
||||
IS Ack 0 <--
|
||||
IS Shared_Ack 0 <--
|
||||
IS Data 0 <--
|
||||
IS Shared_Data 0 <--
|
||||
IS Exclusive_Data 1001
|
||||
|
||||
SS Load 0 <--
|
||||
SS Ifetch 0 <--
|
||||
SS Store 0 <--
|
||||
SS L2_Replacement 0 <--
|
||||
SS L1_to_L2 0 <--
|
||||
SS Ack 0 <--
|
||||
SS Shared_Ack 0 <--
|
||||
SS All_acks 0 <--
|
||||
SS All_acks_no_sharers 0 <--
|
||||
|
||||
OI Load 0 <--
|
||||
OI Ifetch 0 <--
|
||||
OI Store 0 <--
|
||||
OI L2_Replacement 0 <--
|
||||
OI L1_to_L2 0 <--
|
||||
OI Other_GETX 0 <--
|
||||
OI Other_GETS 0 <--
|
||||
OI Writeback_Ack 0 <--
|
||||
|
||||
MI Load 24
|
||||
MI Ifetch 33
|
||||
MI Store 81
|
||||
MI L2_Replacement 0 <--
|
||||
MI L1_to_L2 0 <--
|
||||
MI Other_GETX 0 <--
|
||||
MI Other_GETS 0 <--
|
||||
MI Writeback_Ack 1143
|
||||
|
||||
II Load 0 <--
|
||||
II Ifetch 0 <--
|
||||
II Store 0 <--
|
||||
II L2_Replacement 0 <--
|
||||
II L1_to_L2 0 <--
|
||||
II Other_GETX 0 <--
|
||||
II Other_GETS 0 <--
|
||||
II Writeback_Ack 0 <--
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
|
||||
memory_total_requests: 1379
|
||||
memory_reads: 1159
|
||||
memory_writes: 220
|
||||
memory_refreshes: 449
|
||||
memory_total_request_delays: 342
|
||||
memory_delays_per_request: 0.248006
|
||||
memory_delays_in_input_queue: 1
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 341
|
||||
memory_stalls_for_bank_busy: 167
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 19
|
||||
memory_stalls_for_bus: 57
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 98
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 75 17 45 40 54 101 33 16 20 22 32 34 53 50 39 31 39 22 21 27 28 38 81 22 31 23 32 72 89 126 14 52
|
||||
|
||||
--- Directory 0 ---
|
||||
- Event Counts -
|
||||
GETX 519
|
||||
GETS 1114
|
||||
PUT 1143
|
||||
Unblock 1159
|
||||
Writeback_Clean 0
|
||||
Writeback_Dirty 0
|
||||
Writeback_Exclusive_Clean 923
|
||||
Writeback_Exclusive_Dirty 220
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
Memory_Data 1159
|
||||
Memory_Ack 220
|
||||
Ack 0
|
||||
Shared_Ack 0
|
||||
Shared_Data 0
|
||||
Exclusive_Data 0
|
||||
All_acks_and_data 0
|
||||
All_acks_and_data_no_sharers 0
|
||||
|
||||
- Transitions -
|
||||
NO GETX 0 <--
|
||||
NO GETS 0 <--
|
||||
NO PUT 1143
|
||||
NO DMA_READ 0 <--
|
||||
NO DMA_WRITE 0 <--
|
||||
|
||||
O GETX 0 <--
|
||||
O GETS 0 <--
|
||||
O PUT 0 <--
|
||||
O DMA_READ 0 <--
|
||||
O DMA_WRITE 0 <--
|
||||
|
||||
E GETX 158
|
||||
E GETS 1001
|
||||
E PUT 0 <--
|
||||
E DMA_READ 0 <--
|
||||
E DMA_WRITE 0 <--
|
||||
|
||||
NO_B GETX 0 <--
|
||||
NO_B GETS 0 <--
|
||||
NO_B PUT 0 <--
|
||||
NO_B Unblock 1159
|
||||
NO_B DMA_READ 0 <--
|
||||
NO_B DMA_WRITE 0 <--
|
||||
|
||||
O_B GETX 0 <--
|
||||
O_B GETS 0 <--
|
||||
O_B PUT 0 <--
|
||||
O_B Unblock 0 <--
|
||||
O_B DMA_READ 0 <--
|
||||
O_B DMA_WRITE 0 <--
|
||||
|
||||
NO_B_W GETX 0 <--
|
||||
NO_B_W GETS 0 <--
|
||||
NO_B_W PUT 0 <--
|
||||
NO_B_W Unblock 0 <--
|
||||
NO_B_W DMA_READ 0 <--
|
||||
NO_B_W DMA_WRITE 0 <--
|
||||
NO_B_W Memory_Data 1159
|
||||
|
||||
O_B_W GETX 0 <--
|
||||
O_B_W GETS 0 <--
|
||||
O_B_W PUT 0 <--
|
||||
O_B_W Unblock 0 <--
|
||||
O_B_W DMA_READ 0 <--
|
||||
O_B_W DMA_WRITE 0 <--
|
||||
O_B_W Memory_Data 0 <--
|
||||
|
||||
NO_W GETX 0 <--
|
||||
NO_W GETS 0 <--
|
||||
NO_W PUT 0 <--
|
||||
NO_W DMA_READ 0 <--
|
||||
NO_W DMA_WRITE 0 <--
|
||||
NO_W Memory_Data 0 <--
|
||||
|
||||
O_W GETX 0 <--
|
||||
O_W GETS 0 <--
|
||||
O_W PUT 0 <--
|
||||
O_W DMA_READ 0 <--
|
||||
O_W DMA_WRITE 0 <--
|
||||
O_W Memory_Data 0 <--
|
||||
|
||||
NO_DW_B_W GETX 0 <--
|
||||
NO_DW_B_W GETS 0 <--
|
||||
NO_DW_B_W PUT 0 <--
|
||||
NO_DW_B_W DMA_READ 0 <--
|
||||
NO_DW_B_W DMA_WRITE 0 <--
|
||||
NO_DW_B_W Ack 0 <--
|
||||
NO_DW_B_W Exclusive_Data 0 <--
|
||||
NO_DW_B_W All_acks_and_data_no_sharers 0 <--
|
||||
|
||||
NO_DR_B_W GETX 0 <--
|
||||
NO_DR_B_W GETS 0 <--
|
||||
NO_DR_B_W PUT 0 <--
|
||||
NO_DR_B_W DMA_READ 0 <--
|
||||
NO_DR_B_W DMA_WRITE 0 <--
|
||||
NO_DR_B_W Memory_Data 0 <--
|
||||
NO_DR_B_W Ack 0 <--
|
||||
NO_DR_B_W Shared_Ack 0 <--
|
||||
NO_DR_B_W Shared_Data 0 <--
|
||||
NO_DR_B_W Exclusive_Data 0 <--
|
||||
|
||||
NO_DR_B_D GETX 0 <--
|
||||
NO_DR_B_D GETS 0 <--
|
||||
NO_DR_B_D PUT 0 <--
|
||||
NO_DR_B_D DMA_READ 0 <--
|
||||
NO_DR_B_D DMA_WRITE 0 <--
|
||||
NO_DR_B_D Ack 0 <--
|
||||
NO_DR_B_D Shared_Ack 0 <--
|
||||
NO_DR_B_D Shared_Data 0 <--
|
||||
NO_DR_B_D Exclusive_Data 0 <--
|
||||
NO_DR_B_D All_acks_and_data 0 <--
|
||||
NO_DR_B_D All_acks_and_data_no_sharers 0 <--
|
||||
|
||||
NO_DR_B GETX 0 <--
|
||||
NO_DR_B GETS 0 <--
|
||||
NO_DR_B PUT 0 <--
|
||||
NO_DR_B DMA_READ 0 <--
|
||||
NO_DR_B DMA_WRITE 0 <--
|
||||
NO_DR_B Ack 0 <--
|
||||
NO_DR_B Shared_Ack 0 <--
|
||||
NO_DR_B Shared_Data 0 <--
|
||||
NO_DR_B Exclusive_Data 0 <--
|
||||
NO_DR_B All_acks_and_data 0 <--
|
||||
NO_DR_B All_acks_and_data_no_sharers 0 <--
|
||||
|
||||
NO_DW_W GETX 0 <--
|
||||
NO_DW_W GETS 0 <--
|
||||
NO_DW_W PUT 0 <--
|
||||
NO_DW_W DMA_READ 0 <--
|
||||
NO_DW_W DMA_WRITE 0 <--
|
||||
NO_DW_W Memory_Ack 0 <--
|
||||
|
||||
O_DR_B_W GETX 0 <--
|
||||
O_DR_B_W GETS 0 <--
|
||||
O_DR_B_W PUT 0 <--
|
||||
O_DR_B_W DMA_READ 0 <--
|
||||
O_DR_B_W DMA_WRITE 0 <--
|
||||
O_DR_B_W Memory_Data 0 <--
|
||||
|
||||
O_DR_B GETX 0 <--
|
||||
O_DR_B GETS 0 <--
|
||||
O_DR_B PUT 0 <--
|
||||
O_DR_B DMA_READ 0 <--
|
||||
O_DR_B DMA_WRITE 0 <--
|
||||
O_DR_B Ack 0 <--
|
||||
O_DR_B All_acks_and_data_no_sharers 0 <--
|
||||
|
||||
WB GETX 27
|
||||
WB GETS 20
|
||||
WB PUT 0 <--
|
||||
WB Unblock 0 <--
|
||||
WB Writeback_Clean 0 <--
|
||||
WB Writeback_Dirty 0 <--
|
||||
WB Writeback_Exclusive_Clean 923
|
||||
WB Writeback_Exclusive_Dirty 220
|
||||
WB DMA_READ 0 <--
|
||||
WB DMA_WRITE 0 <--
|
||||
|
||||
WB_O_W GETX 0 <--
|
||||
WB_O_W GETS 0 <--
|
||||
WB_O_W PUT 0 <--
|
||||
WB_O_W DMA_READ 0 <--
|
||||
WB_O_W DMA_WRITE 0 <--
|
||||
WB_O_W Memory_Ack 0 <--
|
||||
|
||||
WB_E_W GETX 334
|
||||
WB_E_W GETS 93
|
||||
WB_E_W PUT 0 <--
|
||||
WB_E_W DMA_READ 0 <--
|
||||
WB_E_W DMA_WRITE 0 <--
|
||||
WB_E_W Memory_Ack 220
|
||||
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
hack: be nice to actually delete the event here
|
||||
17
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
Executable file
17
tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
Executable file
|
|
@ -0,0 +1,17 @@
|
|||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 28 2010 11:30:01
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 11:55:11
|
||||
M5 executing on svvint06
|
||||
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 215528 because target called exit()
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 45742 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 213100 # Number of bytes of host memory used
|
||||
host_seconds 0.14 # Real time elapsed on the host
|
||||
host_tick_rate 1539442 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_seconds 0.000216 # Number of seconds simulated
|
||||
sim_ticks 215528 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
||||
system.cpu.dtb.data_misses 10 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 1192 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 1185 # DTB read hits
|
||||
system.cpu.dtb.read_misses 7 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 868 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 865 # DTB write hits
|
||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 6432 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 6415 # ITB hits
|
||||
system.cpu.itb.fetch_misses 17 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 215528 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 6404 # Number of instructions executed
|
||||
system.cpu.num_refs 2060 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -5,15 +5,15 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
children=cpu physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
clock=1
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
|
|
@ -32,8 +32,8 @@ progress_interval=0
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -54,7 +54,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
|
||||
executable=tests/test-progs/hello/bin/alpha/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -65,30 +65,169 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=RubyMemory
|
||||
clock=1
|
||||
config_file=build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby/ruby.config
|
||||
debug=false
|
||||
debug_file=ruby.debug
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30000
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
num_cpus=1
|
||||
phase=0
|
||||
range=0:134217727
|
||||
stats_file=ruby.stats
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links1.ext_node.directory
|
||||
directory_latency=12
|
||||
memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
size=134217728
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=0
|
||||
node_b=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=1
|
||||
node_b=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
|
||||
[system.ruby.tracer]
|
||||
type=RubyTracer
|
||||
warmup_length=100000
|
||||
|
||||
|
|
|
|||
|
|
@ -2,73 +2,18 @@
|
|||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
RubySystem config:
|
||||
random_seed: 380268
|
||||
random_seed: 1234
|
||||
randomization: 0
|
||||
tech_nm: 45
|
||||
freq_mhz: 3000
|
||||
cycle_period: 1
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 1073741824
|
||||
memory_size_bits: 30
|
||||
DMA_Controller config: DMAController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
dma_sequencer: DMASequencer_0
|
||||
number_of_TBEs: 128
|
||||
transitions_per_cycle: 32
|
||||
Directory_Controller config: DirectoryController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
directory_latency: 6
|
||||
directory_name: DirectoryMemory_0
|
||||
memory_controller_name: MemoryControl_0
|
||||
memory_latency: 158
|
||||
number_of_TBEs: 128
|
||||
recycle_latency: 10
|
||||
to_mem_ctrl_latency: 1
|
||||
transitions_per_cycle: 32
|
||||
L1Cache_Controller config: L1CacheController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
cache: l1u_0
|
||||
cache_response_latency: 12
|
||||
issue_latency: 2
|
||||
number_of_TBEs: 128
|
||||
sequencer: Sequencer_0
|
||||
transitions_per_cycle: 32
|
||||
Cache config: l1u_0
|
||||
controller: L1CacheController_0
|
||||
cache_associativity: 8
|
||||
num_cache_sets_bits: 2
|
||||
num_cache_sets: 4
|
||||
cache_set_size_bytes: 256
|
||||
cache_set_size_Kbytes: 0.25
|
||||
cache_set_size_Mbytes: 0.000244141
|
||||
cache_size_bytes: 2048
|
||||
cache_size_Kbytes: 2
|
||||
cache_size_Mbytes: 0.00195312
|
||||
DirectoryMemory Global Config:
|
||||
number of directory memories: 1
|
||||
total memory size bytes: 1073741824
|
||||
total memory size bits: 30
|
||||
DirectoryMemory module config: DirectoryMemory_0
|
||||
controller: DirectoryController_0
|
||||
version: 0
|
||||
memory_bits: 30
|
||||
memory_size_bytes: 1073741824
|
||||
memory_size_Kbytes: 1.04858e+06
|
||||
memory_size_Mbytes: 1024
|
||||
memory_size_Gbytes: 1
|
||||
Seqeuncer config: Sequencer_0
|
||||
controller: L1CacheController_0
|
||||
version: 0
|
||||
max_outstanding_requests: 16
|
||||
deadlock_threshold: 500000
|
||||
memory_size_bytes: 134217728
|
||||
memory_size_bits: 27
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology: theTopology
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
|
|
@ -76,25 +21,11 @@ virtual_net_2: active, ordered
|
|||
virtual_net_3: inactive
|
||||
virtual_net_4: active, ordered
|
||||
virtual_net_5: active, ordered
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
virtual_net_9: inactive
|
||||
|
||||
--- Begin Topology Print ---
|
||||
|
||||
Topology print ONLY indicates the _NETWORK_ latency between two machines
|
||||
It does NOT include the latency within the machines
|
||||
|
||||
L1Cache-0 Network Latencies
|
||||
L1Cache-0 -> Directory-0 net_lat: 7
|
||||
L1Cache-0 -> DMA-0 net_lat: 7
|
||||
|
||||
Directory-0 Network Latencies
|
||||
Directory-0 -> L1Cache-0 net_lat: 7
|
||||
Directory-0 -> DMA-0 net_lat: 7
|
||||
|
||||
DMA-0 Network Latencies
|
||||
DMA-0 -> L1Cache-0 net_lat: 7
|
||||
DMA-0 -> Directory-0 net_lat: 7
|
||||
|
||||
--- End Topology Print ---
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
|
|
@ -103,7 +34,7 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jul/06/2009 11:11:08
|
||||
Real time: Jan/28/2010 10:15:29
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -112,123 +43,52 @@ Elapsed_time_in_minutes: 0.0166667
|
|||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 0.84
|
||||
Virtual_time_in_minutes: 0.014
|
||||
Virtual_time_in_hours: 0.000233333
|
||||
Virtual_time_in_days: 0.000233333
|
||||
Virtual_time_in_seconds: 0.5
|
||||
Virtual_time_in_minutes: 0.00833333
|
||||
Virtual_time_in_hours: 0.000138889
|
||||
Virtual_time_in_days: 5.78704e-06
|
||||
|
||||
Ruby_current_time: 25390001
|
||||
Ruby_start_time: 1
|
||||
Ruby_cycles: 25390000
|
||||
Ruby_current_time: 342698
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 342698
|
||||
|
||||
mbytes_resident: 145.145
|
||||
mbytes_total: 1329.68
|
||||
resident_ratio: 0.109161
|
||||
mbytes_resident: 34.2148
|
||||
mbytes_total: 34.2227
|
||||
resident_ratio: 1
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
instruction_executed: 1 [ 1 ]
|
||||
ruby_cycles_executed: 25390001 [ 25390001 ]
|
||||
cycles_per_instruction: 2.539e+07 [ 2.539e+07 ]
|
||||
misses_per_thousand_instructions: 0 [ 0 ]
|
||||
ruby_cycles_executed: 342699 [ 342699 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
instructions_per_transaction: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
|
||||
L1D_cache cache stats:
|
||||
L1D_cache_total_misses: 0
|
||||
L1D_cache_total_demand_misses: 0
|
||||
L1D_cache_total_prefetches: 0
|
||||
L1D_cache_total_sw_prefetches: 0
|
||||
L1D_cache_total_hw_prefetches: 0
|
||||
L1D_cache_misses_per_transaction: 0
|
||||
L1D_cache_misses_per_instruction: 0
|
||||
L1D_cache_instructions_per_misses: NaN
|
||||
|
||||
L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
L1I_cache cache stats:
|
||||
L1I_cache_total_misses: 0
|
||||
L1I_cache_total_demand_misses: 0
|
||||
L1I_cache_total_prefetches: 0
|
||||
L1I_cache_total_sw_prefetches: 0
|
||||
L1I_cache_total_hw_prefetches: 0
|
||||
L1I_cache_misses_per_transaction: 0
|
||||
L1I_cache_misses_per_instruction: 0
|
||||
L1I_cache_instructions_per_misses: NaN
|
||||
|
||||
L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
L2_cache cache stats:
|
||||
L2_cache_total_misses: 0
|
||||
L2_cache_total_demand_misses: 0
|
||||
L2_cache_total_prefetches: 0
|
||||
L2_cache_total_sw_prefetches: 0
|
||||
L2_cache_total_hw_prefetches: 0
|
||||
L2_cache_misses_per_transaction: 0
|
||||
L2_cache_misses_per_instruction: 0
|
||||
L2_cache_instructions_per_misses: NaN
|
||||
|
||||
L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
|
||||
Memory control:
|
||||
memory_total_requests: 1554
|
||||
memory_reads: 793
|
||||
memory_writes: 761
|
||||
memory_refreshes: 14035
|
||||
memory_total_request_delays: 1878
|
||||
memory_delays_per_request: 1.20849
|
||||
memory_delays_in_input_queue: 761
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 1117
|
||||
memory_stalls_for_bank_busy: 223
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 62
|
||||
memory_stalls_for_bus: 804
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 28
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 58 26 38 28 28 95 36 22 26 30 48 48 82 65 56 48 61 37 36 30 52 58 52 34 45 35 40 98 78 83 22 59
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
Directory-0:0
|
||||
DMA-0:0
|
||||
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
L2TBE_usage: [binsize: 1 max: 1 count: 1554 average: 0.489704 | standard deviation: 0.500483 | 793 761 ]
|
||||
StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8464 average: 1 | standard deviation: 0 | 0 8464 ]
|
||||
store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8465 average: 1 | standard deviation: 0 | 0 8465 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 279 count: 8464 average: 17.852 | standard deviation: 49.5344 | 0 7671 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 0 0 0 15 0 0 0 0 687 0 0 0 0 16 0 0 0 0 24 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 0 0 0 0 1 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_1: [binsize: 2 max: 269 count: 6414 average: 12.6723 | standard deviation: 41.1839 | 0 6008 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 11 0 0 0 0 362 0 0 0 0 8 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 2 max: 279 count: 1185 average: 42.865 | standard deviation: 73.1137 | 0 900 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 0 0 0 0 1 0 0 0 0 241 0 0 0 0 7 0 0 0 0 12 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 2 max: 279 count: 865 average: 21.9931 | standard deviation: 55.1781 | 0 763 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 3 0 0 0 0 84 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency: [binsize: 2 max: 377 count: 8464 average: 39.4889 | standard deviation: 72.9776 | 0 6734 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 6 1 3 6 0 334 211 182 529 243 4 4 0 5 2 15 9 4 14 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 30 18 15 24 37 2 3 0 0 2 2 1 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ]
|
||||
miss_latency_1: [binsize: 2 max: 285 count: 6414 average: 23.2806 | standard deviation: 57.2661 | 0 5684 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 4 0 155 91 77 220 92 2 3 0 1 2 2 6 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 20 9 5 10 12 2 1 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 2 max: 375 count: 1185 average: 110.608 | standard deviation: 87.0282 | 0 458 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 0 1 2 0 147 90 74 255 81 2 1 0 3 0 12 3 1 9 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 4 2 11 4 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 2 max: 377 count: 865 average: 62.2439 | standard deviation: 89.6671 | 0 592 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 30 31 54 70 0 0 0 1 0 1 0 2 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 8 3 21 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
|
@ -237,104 +97,159 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
|
|||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 1554 average: 0 | standard deviation: 0 | 1554 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1554 average: 0 | standard deviation: 0 | 1554 ]
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 3456 average: 0 | standard deviation: 0 | 3456 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 3456 average: 0 | standard deviation: 0 | 3456 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 793 average: 0 | standard deviation: 0 | 793 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 761 average: 0 | standard deviation: 0 | 761 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1730 average: 0 | standard deviation: 0 | 1730 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1726 average: 0 | standard deviation: 0 | 1726 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 37916
|
||||
page_faults: 0
|
||||
page_reclaims: 7357
|
||||
page_faults: 2195
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 48
|
||||
block_outputs: 0
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.000191266
|
||||
links_utilized_percent_switch_0_link_0: 7.65065e-05 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.000306026 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.157486
|
||||
links_utilized_percent_switch_0_link_0: 0.0630876 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.251884 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 793 6344 [ 0 793 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 761 6088 [ 0 0 761 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 793 6344 [ 793 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 761 6088 [ 761 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.000191266
|
||||
links_utilized_percent_switch_1_link_0: 7.65065e-05 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.000306026 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 0.157661
|
||||
links_utilized_percent_switch_1_link_0: 0.0629709 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.25235 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 793 6344 [ 793 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 761 6088 [ 761 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 793 6344 [ 0 793 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 761 6088 [ 0 0 761 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0
|
||||
links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.252117
|
||||
links_utilized_percent_switch_2_link_0: 0.25235 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.251884 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 1730 124560 [ 0 1730 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 1726 13808 [ 0 0 1726 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 1730 13840 [ 1730 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 1726 124272 [ 1726 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 0.000204017
|
||||
links_utilized_percent_switch_3_link_0: 0.000306026 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.000306026 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1730
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1730
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
|
||||
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 793 6344 [ 0 793 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 761 6088 [ 0 0 761 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 793 6344 [ 793 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Data: 761 6088 [ 761 0 0 0 0 0 ] base_latency: 1
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 42.0231%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 15.7803%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 42.1965%
|
||||
|
||||
--- DMA ---
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 1730 100%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1730 average: 6.00925 | standard deviation: 2.00058 | 0 0 0 0 861 0 0 0 869 ]
|
||||
|
||||
--- L1Cache 0 ---
|
||||
- Event Counts -
|
||||
ReadRequest 0
|
||||
WriteRequest 0
|
||||
Data 0
|
||||
Ack 0
|
||||
Load 1185
|
||||
Ifetch 6414
|
||||
Store 865
|
||||
Data 1730
|
||||
Fwd_GETX 0
|
||||
Inv 0
|
||||
Replacement 1726
|
||||
Writeback_Ack 1726
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
READY ReadRequest 0 <--
|
||||
READY WriteRequest 0 <--
|
||||
I Load 727
|
||||
I Ifetch 730
|
||||
I Store 273
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
BUSY_RD Data 0 <--
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
BUSY_WR Ack 0 <--
|
||||
M Load 458
|
||||
M Ifetch 5684
|
||||
M Store 592
|
||||
M Fwd_GETX 0 <--
|
||||
M Inv 0 <--
|
||||
M Replacement 1726
|
||||
|
||||
--- Directory ---
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 1726
|
||||
MI Writeback_Nack 0 <--
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
|
||||
IS Data 1457
|
||||
|
||||
IM Data 273
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
|
||||
memory_total_requests: 3456
|
||||
memory_reads: 1730
|
||||
memory_writes: 1726
|
||||
memory_refreshes: 714
|
||||
memory_total_request_delays: 5050
|
||||
memory_delays_per_request: 1.46123
|
||||
memory_delays_in_input_queue: 1722
|
||||
memory_delays_behind_head_of_bank_queue: 8
|
||||
memory_delays_stalled_at_head_of_bank_queue: 3320
|
||||
memory_stalls_for_bank_busy: 1509
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 99
|
||||
memory_stalls_for_bus: 1677
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 35
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 162 36 92 110 106 362 98 36 32 34 83 92 110 104 84 86 83 53 50 58 64 124 212 72 66 50 122 190 220 325 42 98
|
||||
|
||||
--- Directory 0 ---
|
||||
- Event Counts -
|
||||
GETX 793
|
||||
GETX 1730
|
||||
GETS 0
|
||||
PUTX 761
|
||||
PUTX 1726
|
||||
PUTX_NotOwner 0
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
Memory_Data 793
|
||||
Memory_Ack 761
|
||||
Memory_Data 1730
|
||||
Memory_Ack 1726
|
||||
|
||||
- Transitions -
|
||||
I GETX 793
|
||||
I GETX 1730
|
||||
I PUTX_NotOwner 0 <--
|
||||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
|
||||
M GETX 0 <--
|
||||
M PUTX 761
|
||||
M PUTX 1726
|
||||
M PUTX_NotOwner 0 <--
|
||||
M DMA_READ 0 <--
|
||||
M DMA_WRITE 0 <--
|
||||
|
|
@ -345,15 +260,19 @@ M_DRD PUTX 0 <--
|
|||
M_DWR GETX 0 <--
|
||||
M_DWR PUTX 0 <--
|
||||
|
||||
M_DWRI GETX 0 <--
|
||||
M_DWRI Memory_Ack 0 <--
|
||||
|
||||
M_DRDI GETX 0 <--
|
||||
M_DRDI Memory_Ack 0 <--
|
||||
|
||||
IM GETX 0 <--
|
||||
IM GETS 0 <--
|
||||
IM PUTX 0 <--
|
||||
IM PUTX_NotOwner 0 <--
|
||||
IM DMA_READ 0 <--
|
||||
IM DMA_WRITE 0 <--
|
||||
IM Memory_Data 793
|
||||
IM Memory_Data 1730
|
||||
|
||||
MI GETX 0 <--
|
||||
MI GETS 0 <--
|
||||
|
|
@ -361,7 +280,7 @@ MI PUTX 0 <--
|
|||
MI PUTX_NotOwner 0 <--
|
||||
MI DMA_READ 0 <--
|
||||
MI DMA_WRITE 0 <--
|
||||
MI Memory_Ack 761
|
||||
MI Memory_Ack 1726
|
||||
|
||||
ID GETX 0 <--
|
||||
ID GETS 0 <--
|
||||
|
|
@ -379,39 +298,3 @@ ID_W DMA_READ 0 <--
|
|||
ID_W DMA_WRITE 0 <--
|
||||
ID_W Memory_Ack 0 <--
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load 1185
|
||||
Ifetch 6414
|
||||
Store 865
|
||||
Data 793
|
||||
Fwd_GETX 0
|
||||
Inv 0
|
||||
Replacement 761
|
||||
Writeback_Ack 761
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 285
|
||||
I Ifetch 406
|
||||
I Store 102
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 900
|
||||
M Ifetch 6008
|
||||
M Store 763
|
||||
M Fwd_GETX 0 <--
|
||||
M Inv 0 <--
|
||||
M Replacement 761
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 761
|
||||
|
||||
IS Data 691
|
||||
|
||||
IM Data 102
|
||||
|
||||
|
|
|
|||
|
|
@ -1,23 +1,3 @@
|
|||
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
|
||||
print config: 1
|
||||
Creating new MessageBuffer for 0 0
|
||||
Creating new MessageBuffer for 0 1
|
||||
Creating new MessageBuffer for 0 2
|
||||
Creating new MessageBuffer for 0 3
|
||||
Creating new MessageBuffer for 0 4
|
||||
Creating new MessageBuffer for 0 5
|
||||
Creating new MessageBuffer for 1 0
|
||||
Creating new MessageBuffer for 1 1
|
||||
Creating new MessageBuffer for 1 2
|
||||
Creating new MessageBuffer for 1 3
|
||||
Creating new MessageBuffer for 1 4
|
||||
Creating new MessageBuffer for 1 5
|
||||
Creating new MessageBuffer for 2 0
|
||||
Creating new MessageBuffer for 2 1
|
||||
Creating new MessageBuffer for 2 2
|
||||
Creating new MessageBuffer for 2 3
|
||||
Creating new MessageBuffer for 2 4
|
||||
Creating new MessageBuffer for 2 5
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,14 +5,13 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 6 2009 11:03:45
|
||||
M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
|
||||
M5 started Jul 6 2009 11:11:07
|
||||
M5 executing on maize
|
||||
M5 compiled Jan 27 2010 22:23:20
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 10:15:28
|
||||
M5 executing on svvint07
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Debug: Adding to filter: 'q' (Queue)
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 25390000 because target called exit()
|
||||
Exiting @ tick 342698 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 8064 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 1361592 # Number of bytes of host memory used
|
||||
host_seconds 0.79 # Real time elapsed on the host
|
||||
host_tick_rate 31966299 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 19405 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215700 # Number of bytes of host memory used
|
||||
host_seconds 0.33 # Real time elapsed on the host
|
||||
host_tick_rate 1038428 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 6404 # Number of instructions simulated
|
||||
sim_seconds 0.000025 # Number of seconds simulated
|
||||
sim_ticks 25390000 # Number of ticks simulated
|
||||
sim_seconds 0.000343 # Number of seconds simulated
|
||||
sim_ticks 342698 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 2060 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 2050 # DTB hits
|
||||
|
|
@ -42,7 +42,7 @@ system.cpu.itb.write_acv 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 50780 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 342698 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 6404 # Number of instructions executed
|
||||
system.cpu.num_refs 2060 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,97 +0,0 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=RubyMemory
|
||||
clock=1
|
||||
config_file=build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic-ruby/ruby.config
|
||||
debug=false
|
||||
debug_file=ruby.debug
|
||||
file=
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
num_cpus=1
|
||||
phase=0
|
||||
range=0:134217727
|
||||
stats_file=ruby.stats
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
|
|
@ -1,382 +0,0 @@
|
|||
|
||||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
RubySystem config:
|
||||
random_seed: 613394
|
||||
randomization: 0
|
||||
tech_nm: 45
|
||||
freq_mhz: 3000
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 1073741824
|
||||
memory_size_bits: 30
|
||||
DMA_Controller config: DMAController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
dma_sequencer: DMASequencer_0
|
||||
number_of_TBEs: 128
|
||||
transitions_per_cycle: 32
|
||||
Directory_Controller config: DirectoryController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
directory_latency: 6
|
||||
directory_name: DirectoryMemory_0
|
||||
memory_controller_name: MemoryControl_0
|
||||
memory_latency: 158
|
||||
number_of_TBEs: 128
|
||||
recycle_latency: 10
|
||||
to_mem_ctrl_latency: 1
|
||||
transitions_per_cycle: 32
|
||||
L1Cache_Controller config: L1CacheController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
cache: l1u_0
|
||||
cache_response_latency: 12
|
||||
issue_latency: 2
|
||||
number_of_TBEs: 128
|
||||
sequencer: Sequencer_0
|
||||
transitions_per_cycle: 32
|
||||
Cache config: l1u_0
|
||||
controller: L1CacheController_0
|
||||
cache_associativity: 8
|
||||
num_cache_sets_bits: 2
|
||||
num_cache_sets: 4
|
||||
cache_set_size_bytes: 256
|
||||
cache_set_size_Kbytes: 0.25
|
||||
cache_set_size_Mbytes: 0.000244141
|
||||
cache_size_bytes: 2048
|
||||
cache_size_Kbytes: 2
|
||||
cache_size_Mbytes: 0.00195312
|
||||
DirectoryMemory Global Config:
|
||||
number of directory memories: 1
|
||||
total memory size bytes: 1073741824
|
||||
total memory size bits: 30
|
||||
DirectoryMemory module config: DirectoryMemory_0
|
||||
controller: DirectoryController_0
|
||||
version: 0
|
||||
memory_bits: 30
|
||||
memory_size_bytes: 1073741824
|
||||
memory_size_Kbytes: 1.04858e+06
|
||||
memory_size_Mbytes: 1024
|
||||
memory_size_Gbytes: 1
|
||||
Seqeuncer config: Sequencer_0
|
||||
controller: L1CacheController_0
|
||||
version: 0
|
||||
max_outstanding_requests: 16
|
||||
deadlock_threshold: 500000
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology: theTopology
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
virtual_net_2: active, ordered
|
||||
virtual_net_3: inactive
|
||||
virtual_net_4: active, ordered
|
||||
virtual_net_5: active, ordered
|
||||
|
||||
--- Begin Topology Print ---
|
||||
|
||||
Topology print ONLY indicates the _NETWORK_ latency between two machines
|
||||
It does NOT include the latency within the machines
|
||||
|
||||
L1Cache-0 Network Latencies
|
||||
L1Cache-0 -> Directory-0 net_lat: 7
|
||||
L1Cache-0 -> DMA-0 net_lat: 7
|
||||
|
||||
Directory-0 Network Latencies
|
||||
Directory-0 -> L1Cache-0 net_lat: 7
|
||||
Directory-0 -> DMA-0 net_lat: 7
|
||||
|
||||
DMA-0 Network Latencies
|
||||
DMA-0 -> L1Cache-0 net_lat: 7
|
||||
DMA-0 -> Directory-0 net_lat: 7
|
||||
|
||||
--- End Topology Print ---
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
periodic_stats_period: 1000000
|
||||
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jul/06/2009 11:11:05
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.21
|
||||
Virtual_time_in_minutes: 0.0035
|
||||
Virtual_time_in_hours: 5.83333e-05
|
||||
Virtual_time_in_days: 5.83333e-05
|
||||
|
||||
Ruby_current_time: 1297501
|
||||
Ruby_start_time: 1
|
||||
Ruby_cycles: 1297500
|
||||
|
||||
mbytes_resident: 143.516
|
||||
mbytes_total: 1328.64
|
||||
resident_ratio: 0.10802
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
instruction_executed: 1 [ 1 ]
|
||||
ruby_cycles_executed: 1297501 [ 1297501 ]
|
||||
cycles_per_instruction: 1.2975e+06 [ 1.2975e+06 ]
|
||||
misses_per_thousand_instructions: 0 [ 0 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
instructions_per_transaction: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
|
||||
L1D_cache cache stats:
|
||||
L1D_cache_total_misses: 0
|
||||
L1D_cache_total_demand_misses: 0
|
||||
L1D_cache_total_prefetches: 0
|
||||
L1D_cache_total_sw_prefetches: 0
|
||||
L1D_cache_total_hw_prefetches: 0
|
||||
L1D_cache_misses_per_transaction: 0
|
||||
L1D_cache_misses_per_instruction: 0
|
||||
L1D_cache_instructions_per_misses: NaN
|
||||
|
||||
L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
L1I_cache cache stats:
|
||||
L1I_cache_total_misses: 0
|
||||
L1I_cache_total_demand_misses: 0
|
||||
L1I_cache_total_prefetches: 0
|
||||
L1I_cache_total_sw_prefetches: 0
|
||||
L1I_cache_total_hw_prefetches: 0
|
||||
L1I_cache_misses_per_transaction: 0
|
||||
L1I_cache_misses_per_instruction: 0
|
||||
L1I_cache_instructions_per_misses: NaN
|
||||
|
||||
L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
L2_cache cache stats:
|
||||
L2_cache_total_misses: 0
|
||||
L2_cache_total_demand_misses: 0
|
||||
L2_cache_total_prefetches: 0
|
||||
L2_cache_total_sw_prefetches: 0
|
||||
L2_cache_total_hw_prefetches: 0
|
||||
L2_cache_misses_per_transaction: 0
|
||||
L2_cache_misses_per_instruction: 0
|
||||
L2_cache_instructions_per_misses: NaN
|
||||
|
||||
L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
Directory-0:0
|
||||
DMA-0:0
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 37503
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 24
|
||||
block_outputs: 48
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0
|
||||
links_utilized_percent_switch_0_link_0: 0 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0 bw: 160000 base_latency: 1
|
||||
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0
|
||||
links_utilized_percent_switch_1_link_0: 0 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0 bw: 160000 base_latency: 1
|
||||
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0
|
||||
links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
|
||||
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 0
|
||||
links_utilized_percent_switch_3_link_0: 0 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
|
||||
|
||||
|
||||
--- DMA ---
|
||||
- Event Counts -
|
||||
ReadRequest 0
|
||||
WriteRequest 0
|
||||
Data 0
|
||||
Ack 0
|
||||
|
||||
- Transitions -
|
||||
READY ReadRequest 0 <--
|
||||
READY WriteRequest 0 <--
|
||||
|
||||
BUSY_RD Data 0 <--
|
||||
|
||||
BUSY_WR Ack 0 <--
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX 0
|
||||
GETS 0
|
||||
PUTX 0
|
||||
PUTX_NotOwner 0
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
Memory_Data 0
|
||||
Memory_Ack 0
|
||||
|
||||
- Transitions -
|
||||
I GETX 0 <--
|
||||
I PUTX_NotOwner 0 <--
|
||||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
|
||||
M GETX 0 <--
|
||||
M PUTX 0 <--
|
||||
M PUTX_NotOwner 0 <--
|
||||
M DMA_READ 0 <--
|
||||
M DMA_WRITE 0 <--
|
||||
|
||||
M_DRD GETX 0 <--
|
||||
M_DRD PUTX 0 <--
|
||||
|
||||
M_DWR GETX 0 <--
|
||||
M_DWR PUTX 0 <--
|
||||
|
||||
M_DWRI Memory_Ack 0 <--
|
||||
|
||||
IM GETX 0 <--
|
||||
IM GETS 0 <--
|
||||
IM PUTX 0 <--
|
||||
IM PUTX_NotOwner 0 <--
|
||||
IM DMA_READ 0 <--
|
||||
IM DMA_WRITE 0 <--
|
||||
IM Memory_Data 0 <--
|
||||
|
||||
MI GETX 0 <--
|
||||
MI GETS 0 <--
|
||||
MI PUTX 0 <--
|
||||
MI PUTX_NotOwner 0 <--
|
||||
MI DMA_READ 0 <--
|
||||
MI DMA_WRITE 0 <--
|
||||
MI Memory_Ack 0 <--
|
||||
|
||||
ID GETX 0 <--
|
||||
ID GETS 0 <--
|
||||
ID PUTX 0 <--
|
||||
ID PUTX_NotOwner 0 <--
|
||||
ID DMA_READ 0 <--
|
||||
ID DMA_WRITE 0 <--
|
||||
ID Memory_Data 0 <--
|
||||
|
||||
ID_W GETX 0 <--
|
||||
ID_W GETS 0 <--
|
||||
ID_W PUTX 0 <--
|
||||
ID_W PUTX_NotOwner 0 <--
|
||||
ID_W DMA_READ 0 <--
|
||||
ID_W DMA_WRITE 0 <--
|
||||
ID_W Memory_Ack 0 <--
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load 0
|
||||
Ifetch 0
|
||||
Store 0
|
||||
Data 0
|
||||
Fwd_GETX 0
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 0 <--
|
||||
I Ifetch 0 <--
|
||||
I Store 0 <--
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M Fwd_GETX 0 <--
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
|
||||
IS Data 0 <--
|
||||
|
||||
IM Data 0 <--
|
||||
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
|
||||
print config: 1
|
||||
Creating new MessageBuffer for 0 0
|
||||
Creating new MessageBuffer for 0 1
|
||||
Creating new MessageBuffer for 0 2
|
||||
Creating new MessageBuffer for 0 3
|
||||
Creating new MessageBuffer for 0 4
|
||||
Creating new MessageBuffer for 0 5
|
||||
Creating new MessageBuffer for 1 0
|
||||
Creating new MessageBuffer for 1 1
|
||||
Creating new MessageBuffer for 1 2
|
||||
Creating new MessageBuffer for 1 3
|
||||
Creating new MessageBuffer for 1 4
|
||||
Creating new MessageBuffer for 1 5
|
||||
Creating new MessageBuffer for 2 0
|
||||
Creating new MessageBuffer for 2 1
|
||||
Creating new MessageBuffer for 2 2
|
||||
Creating new MessageBuffer for 2 3
|
||||
Creating new MessageBuffer for 2 4
|
||||
Creating new MessageBuffer for 2 5
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 6 2009 11:03:45
|
||||
M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
|
||||
M5 started Jul 6 2009 11:11:05
|
||||
M5 executing on maize
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic-ruby
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Debug: Adding to filter: 'q' (Queue)
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 1297500 because target called exit()
|
||||
|
|
@ -0,0 +1,281 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
checker=Null
|
||||
clock=1
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
buffer_size=0
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
to_l2_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
l2_request_latency=2
|
||||
l2_response_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
to_l1_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links2.ext_node
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links2.ext_node.directory
|
||||
directory_latency=6
|
||||
memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
to_mem_ctrl_latency=1
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
size=134217728
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=0
|
||||
node_b=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=1
|
||||
node_b=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links2]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=2
|
||||
node_b=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
|
||||
[system.ruby.tracer]
|
||||
type=RubyTracer
|
||||
warmup_length=100000
|
||||
|
||||
|
|
@ -0,0 +1,617 @@
|
|||
|
||||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
RubySystem config:
|
||||
random_seed: 1234
|
||||
randomization: 0
|
||||
cycle_period: 1
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 134217728
|
||||
memory_size_bits: 27
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, unordered
|
||||
virtual_net_1: active, unordered
|
||||
virtual_net_2: active, unordered
|
||||
virtual_net_3: inactive
|
||||
virtual_net_4: inactive
|
||||
virtual_net_5: inactive
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
virtual_net_9: inactive
|
||||
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
periodic_stats_period: 1000000
|
||||
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/28/2010 13:57:45
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.45
|
||||
Virtual_time_in_minutes: 0.0075
|
||||
Virtual_time_in_hours: 0.000125
|
||||
Virtual_time_in_days: 5.20833e-06
|
||||
|
||||
Ruby_current_time: 103637
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 103637
|
||||
|
||||
mbytes_resident: 33.0938
|
||||
mbytes_total: 33.1016
|
||||
resident_ratio: 1
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
ruby_cycles_executed: 103638 [ 103638 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
L2Cache-0:0
|
||||
Directory-0:0
|
||||
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 223 count: 3294 average: 30.4624 | standard deviation: 61.2716 | 0 2722 0 0 0 0 0 0 0 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 156 96 122 80 3 4 5 3 3 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_1: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ]
|
||||
miss_latency_2: [binsize: 2 max: 217 count: 415 average: 79.6169 | standard deviation: 81.8661 | 0 211 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 58 25 52 15 1 2 2 2 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 2 max: 223 count: 294 average: 39.1837 | standard deviation: 68.3072 | 0 226 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 28 4 11 11 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 20 count: 3612 average: 0.0221484 | standard deviation: 0.622437 | 3607 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 3 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 2644 average: 0 | standard deviation: 0 | 2644 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 20 count: 968 average: 0.0826446 | standard deviation: 1.20065 | 963 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 3 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 431 average: 0 | standard deviation: 0 | 431 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 2213 average: 0 | standard deviation: 0 | 2213 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 7156
|
||||
page_faults: 2112
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.0891754
|
||||
links_utilized_percent_switch_0_link_0: 0.0687858 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.109565 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Request_Control: 431 3448 [ 431 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 572 41184 [ 0 572 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 124 992 [ 0 124 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 572 4576 [ 572 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Response_Control: 641 5128 [ 0 369 272 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 109 7848 [ 47 62 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 77 616 [ 77 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.230281
|
||||
links_utilized_percent_switch_1_link_0: 0.0932703 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.367292 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 572 4576 [ 572 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Data: 547 39384 [ 0 547 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Response_Control: 1180 9440 [ 0 908 272 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 109 7848 [ 47 62 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 77 616 [ 77 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Control: 547 4376 [ 547 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 431 3448 [ 431 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 675 48600 [ 0 675 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 560 4480 [ 0 560 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.143277
|
||||
links_utilized_percent_switch_2_link_0: 0.0230371 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.263516 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Control: 547 4376 [ 547 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 103 7416 [ 0 103 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 547 39384 [ 0 547 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Control: 539 4312 [ 0 539 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 0.246791
|
||||
links_utilized_percent_switch_3_link_0: 0.275143 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.373081 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.0921486 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Request_Control: 431 3448 [ 431 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 572 41184 [ 0 572 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 124 992 [ 0 124 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 572 4576 [ 572 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Data: 547 39384 [ 0 547 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Response_Control: 1180 9440 [ 0 908 272 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 109 7848 [ 47 62 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 77 616 [ 77 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Control: 547 4376 [ 547 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Data: 103 7416 [ 0 103 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
--- L1Cache 0 ---
|
||||
- Event Counts -
|
||||
Load 415
|
||||
Ifetch 2585
|
||||
Store 294
|
||||
Inv 431
|
||||
L1_Replacement 502
|
||||
Fwd_GETX 0
|
||||
Fwd_GETS 0
|
||||
Fwd_GET_INSTR 0
|
||||
Data 0
|
||||
Data_Exclusive 204
|
||||
DataS_fromL1 0
|
||||
Data_all_Acks 368
|
||||
Ack 0
|
||||
Ack_all 0
|
||||
WB_Ack 124
|
||||
|
||||
- Transitions -
|
||||
NP Load 182
|
||||
NP Ifetch 270
|
||||
NP Store 58
|
||||
NP Inv 162
|
||||
NP L1_Replacement 0 <--
|
||||
|
||||
I Load 22
|
||||
I Ifetch 30
|
||||
I Store 10
|
||||
I Inv 0 <--
|
||||
I L1_Replacement 206
|
||||
|
||||
S Load 0 <--
|
||||
S Ifetch 2285
|
||||
S Store 0 <--
|
||||
S Inv 124
|
||||
S L1_Replacement 172
|
||||
|
||||
E Load 140
|
||||
E Ifetch 0 <--
|
||||
E Store 41
|
||||
E Inv 83
|
||||
E L1_Replacement 79
|
||||
E Fwd_GETX 0 <--
|
||||
E Fwd_GETS 0 <--
|
||||
E Fwd_GET_INSTR 0 <--
|
||||
|
||||
M Load 71
|
||||
M Ifetch 0 <--
|
||||
M Store 185
|
||||
M Inv 62
|
||||
M L1_Replacement 45
|
||||
M Fwd_GETX 0 <--
|
||||
M Fwd_GETS 0 <--
|
||||
M Fwd_GET_INSTR 0 <--
|
||||
|
||||
IS Load 0 <--
|
||||
IS Ifetch 0 <--
|
||||
IS Store 0 <--
|
||||
IS Inv 0 <--
|
||||
IS L1_Replacement 0 <--
|
||||
IS Data_Exclusive 204
|
||||
IS DataS_fromL1 0 <--
|
||||
IS Data_all_Acks 300
|
||||
|
||||
IM Load 0 <--
|
||||
IM Ifetch 0 <--
|
||||
IM Store 0 <--
|
||||
IM Inv 0 <--
|
||||
IM L1_Replacement 0 <--
|
||||
IM Data 0 <--
|
||||
IM Data_all_Acks 68
|
||||
IM Ack 0 <--
|
||||
|
||||
SM Load 0 <--
|
||||
SM Ifetch 0 <--
|
||||
SM Store 0 <--
|
||||
SM Inv 0 <--
|
||||
SM L1_Replacement 0 <--
|
||||
SM Ack 0 <--
|
||||
SM Ack_all 0 <--
|
||||
|
||||
IS_I Load 0 <--
|
||||
IS_I Ifetch 0 <--
|
||||
IS_I Store 0 <--
|
||||
IS_I Inv 0 <--
|
||||
IS_I L1_Replacement 0 <--
|
||||
IS_I Data_Exclusive 0 <--
|
||||
IS_I DataS_fromL1 0 <--
|
||||
IS_I Data_all_Acks 0 <--
|
||||
|
||||
M_I Load 0 <--
|
||||
M_I Ifetch 0 <--
|
||||
M_I Store 0 <--
|
||||
M_I Inv 0 <--
|
||||
M_I L1_Replacement 0 <--
|
||||
M_I Fwd_GETX 0 <--
|
||||
M_I Fwd_GETS 0 <--
|
||||
M_I Fwd_GET_INSTR 0 <--
|
||||
M_I WB_Ack 124
|
||||
|
||||
E_I Load 0 <--
|
||||
E_I Ifetch 0 <--
|
||||
E_I Store 0 <--
|
||||
E_I L1_Replacement 0 <--
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
--- L2Cache 0 ---
|
||||
- Event Counts -
|
||||
L1_GET_INSTR 300
|
||||
L1_GETS 209
|
||||
L1_GETX 71
|
||||
L1_UPGRADE 0
|
||||
L1_PUTX 124
|
||||
L1_PUTX_old 0
|
||||
Fwd_L1_GETX 0
|
||||
Fwd_L1_GETS 0
|
||||
Fwd_L1_GET_INSTR 0
|
||||
L2_Replacement 43
|
||||
L2_Replacement_clean 496
|
||||
Mem_Data 547
|
||||
Mem_Ack 539
|
||||
WB_Data 62
|
||||
WB_Data_clean 0
|
||||
Ack 0
|
||||
Ack_all 369
|
||||
Unblock 0
|
||||
Unblock_Cancel 0
|
||||
Exclusive_Unblock 272
|
||||
MEM_Inv 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GET_INSTR 291
|
||||
NP L1_GETS 192
|
||||
NP L1_GETX 64
|
||||
NP L1_PUTX 0 <--
|
||||
NP L1_PUTX_old 0 <--
|
||||
|
||||
SS L1_GET_INSTR 9
|
||||
SS L1_GETS 0 <--
|
||||
SS L1_GETX 0 <--
|
||||
SS L1_UPGRADE 0 <--
|
||||
SS L1_PUTX 0 <--
|
||||
SS L1_PUTX_old 0 <--
|
||||
SS L2_Replacement 0 <--
|
||||
SS L2_Replacement_clean 286
|
||||
SS MEM_Inv 0 <--
|
||||
|
||||
M L1_GET_INSTR 0 <--
|
||||
M L1_GETS 12
|
||||
M L1_GETX 4
|
||||
M L1_PUTX 0 <--
|
||||
M L1_PUTX_old 0 <--
|
||||
M L2_Replacement 39
|
||||
M L2_Replacement_clean 69
|
||||
M MEM_Inv 0 <--
|
||||
|
||||
MT L1_GET_INSTR 0 <--
|
||||
MT L1_GETS 0 <--
|
||||
MT L1_GETX 0 <--
|
||||
MT L1_PUTX 124
|
||||
MT L1_PUTX_old 0 <--
|
||||
MT L2_Replacement 4
|
||||
MT L2_Replacement_clean 141
|
||||
MT MEM_Inv 0 <--
|
||||
|
||||
M_I L1_GET_INSTR 0 <--
|
||||
M_I L1_GETS 5
|
||||
M_I L1_GETX 3
|
||||
M_I L1_UPGRADE 0 <--
|
||||
M_I L1_PUTX 0 <--
|
||||
M_I L1_PUTX_old 0 <--
|
||||
M_I Mem_Ack 539
|
||||
M_I MEM_Inv 0 <--
|
||||
|
||||
MT_I L1_GET_INSTR 0 <--
|
||||
MT_I L1_GETS 0 <--
|
||||
MT_I L1_GETX 0 <--
|
||||
MT_I L1_UPGRADE 0 <--
|
||||
MT_I L1_PUTX 0 <--
|
||||
MT_I L1_PUTX_old 0 <--
|
||||
MT_I WB_Data 2
|
||||
MT_I WB_Data_clean 0 <--
|
||||
MT_I Ack_all 2
|
||||
MT_I MEM_Inv 0 <--
|
||||
|
||||
MCT_I L1_GET_INSTR 0 <--
|
||||
MCT_I L1_GETS 0 <--
|
||||
MCT_I L1_GETX 0 <--
|
||||
MCT_I L1_UPGRADE 0 <--
|
||||
MCT_I L1_PUTX 0 <--
|
||||
MCT_I L1_PUTX_old 0 <--
|
||||
MCT_I WB_Data 60
|
||||
MCT_I WB_Data_clean 0 <--
|
||||
MCT_I Ack_all 81
|
||||
|
||||
I_I L1_GET_INSTR 0 <--
|
||||
I_I L1_GETS 0 <--
|
||||
I_I L1_GETX 0 <--
|
||||
I_I L1_UPGRADE 0 <--
|
||||
I_I L1_PUTX 0 <--
|
||||
I_I L1_PUTX_old 0 <--
|
||||
I_I Ack 0 <--
|
||||
I_I Ack_all 286
|
||||
|
||||
S_I L1_GET_INSTR 0 <--
|
||||
S_I L1_GETS 0 <--
|
||||
S_I L1_GETX 0 <--
|
||||
S_I L1_UPGRADE 0 <--
|
||||
S_I L1_PUTX 0 <--
|
||||
S_I L1_PUTX_old 0 <--
|
||||
S_I Ack 0 <--
|
||||
S_I Ack_all 0 <--
|
||||
S_I MEM_Inv 0 <--
|
||||
|
||||
ISS L1_GET_INSTR 0 <--
|
||||
ISS L1_GETS 0 <--
|
||||
ISS L1_GETX 0 <--
|
||||
ISS L1_PUTX 0 <--
|
||||
ISS L1_PUTX_old 0 <--
|
||||
ISS L2_Replacement 0 <--
|
||||
ISS L2_Replacement_clean 0 <--
|
||||
ISS Mem_Data 192
|
||||
ISS MEM_Inv 0 <--
|
||||
|
||||
IS L1_GET_INSTR 0 <--
|
||||
IS L1_GETS 0 <--
|
||||
IS L1_GETX 0 <--
|
||||
IS L1_PUTX 0 <--
|
||||
IS L1_PUTX_old 0 <--
|
||||
IS L2_Replacement 0 <--
|
||||
IS L2_Replacement_clean 0 <--
|
||||
IS Mem_Data 291
|
||||
IS MEM_Inv 0 <--
|
||||
|
||||
IM L1_GET_INSTR 0 <--
|
||||
IM L1_GETS 0 <--
|
||||
IM L1_GETX 0 <--
|
||||
IM L1_PUTX 0 <--
|
||||
IM L1_PUTX_old 0 <--
|
||||
IM L2_Replacement 0 <--
|
||||
IM L2_Replacement_clean 0 <--
|
||||
IM Mem_Data 64
|
||||
IM MEM_Inv 0 <--
|
||||
|
||||
SS_MB L1_GET_INSTR 0 <--
|
||||
SS_MB L1_GETS 0 <--
|
||||
SS_MB L1_GETX 0 <--
|
||||
SS_MB L1_UPGRADE 0 <--
|
||||
SS_MB L1_PUTX 0 <--
|
||||
SS_MB L1_PUTX_old 0 <--
|
||||
SS_MB L2_Replacement 0 <--
|
||||
SS_MB L2_Replacement_clean 0 <--
|
||||
SS_MB Unblock_Cancel 0 <--
|
||||
SS_MB Exclusive_Unblock 0 <--
|
||||
SS_MB MEM_Inv 0 <--
|
||||
|
||||
MT_MB L1_GET_INSTR 0 <--
|
||||
MT_MB L1_GETS 0 <--
|
||||
MT_MB L1_GETX 0 <--
|
||||
MT_MB L1_UPGRADE 0 <--
|
||||
MT_MB L1_PUTX 0 <--
|
||||
MT_MB L1_PUTX_old 0 <--
|
||||
MT_MB L2_Replacement 0 <--
|
||||
MT_MB L2_Replacement_clean 0 <--
|
||||
MT_MB Unblock_Cancel 0 <--
|
||||
MT_MB Exclusive_Unblock 272
|
||||
MT_MB MEM_Inv 0 <--
|
||||
|
||||
M_MB L1_GET_INSTR 0 <--
|
||||
M_MB L1_GETS 0 <--
|
||||
M_MB L1_GETX 0 <--
|
||||
M_MB L1_UPGRADE 0 <--
|
||||
M_MB L1_PUTX 0 <--
|
||||
M_MB L1_PUTX_old 0 <--
|
||||
M_MB L2_Replacement 0 <--
|
||||
M_MB L2_Replacement_clean 0 <--
|
||||
M_MB Exclusive_Unblock 0 <--
|
||||
M_MB MEM_Inv 0 <--
|
||||
|
||||
MT_IIB L1_GET_INSTR 0 <--
|
||||
MT_IIB L1_GETS 0 <--
|
||||
MT_IIB L1_GETX 0 <--
|
||||
MT_IIB L1_UPGRADE 0 <--
|
||||
MT_IIB L1_PUTX 0 <--
|
||||
MT_IIB L1_PUTX_old 0 <--
|
||||
MT_IIB L2_Replacement 0 <--
|
||||
MT_IIB L2_Replacement_clean 0 <--
|
||||
MT_IIB WB_Data 0 <--
|
||||
MT_IIB WB_Data_clean 0 <--
|
||||
MT_IIB Unblock 0 <--
|
||||
MT_IIB MEM_Inv 0 <--
|
||||
|
||||
MT_IB L1_GET_INSTR 0 <--
|
||||
MT_IB L1_GETS 0 <--
|
||||
MT_IB L1_GETX 0 <--
|
||||
MT_IB L1_UPGRADE 0 <--
|
||||
MT_IB L1_PUTX 0 <--
|
||||
MT_IB L1_PUTX_old 0 <--
|
||||
MT_IB L2_Replacement 0 <--
|
||||
MT_IB L2_Replacement_clean 0 <--
|
||||
MT_IB WB_Data 0 <--
|
||||
MT_IB WB_Data_clean 0 <--
|
||||
MT_IB Unblock_Cancel 0 <--
|
||||
MT_IB MEM_Inv 0 <--
|
||||
|
||||
MT_SB L1_GET_INSTR 0 <--
|
||||
MT_SB L1_GETS 0 <--
|
||||
MT_SB L1_GETX 0 <--
|
||||
MT_SB L1_UPGRADE 0 <--
|
||||
MT_SB L1_PUTX 0 <--
|
||||
MT_SB L1_PUTX_old 0 <--
|
||||
MT_SB L2_Replacement 0 <--
|
||||
MT_SB L2_Replacement_clean 0 <--
|
||||
MT_SB Unblock 0 <--
|
||||
MT_SB MEM_Inv 0 <--
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
|
||||
memory_total_requests: 650
|
||||
memory_reads: 547
|
||||
memory_writes: 103
|
||||
memory_refreshes: 216
|
||||
memory_total_request_delays: 375
|
||||
memory_delays_per_request: 0.576923
|
||||
memory_delays_in_input_queue: 39
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 336
|
||||
memory_stalls_for_bank_busy: 44
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 6
|
||||
memory_stalls_for_bus: 91
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 195
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 26 14 0 49 21 21 42 25 6 4 7 4 24 42 26 3 5 7 7 18 10 29 15 50 19 5 6 16 14 24 19 92
|
||||
|
||||
--- Directory 0 ---
|
||||
- Event Counts -
|
||||
Fetch 547
|
||||
Data 103
|
||||
Memory_Data 547
|
||||
Memory_Ack 103
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
CleanReplacement 436
|
||||
|
||||
- Transitions -
|
||||
I Fetch 547
|
||||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
|
||||
ID Fetch 0 <--
|
||||
ID Data 0 <--
|
||||
ID Memory_Data 0 <--
|
||||
ID DMA_READ 0 <--
|
||||
ID DMA_WRITE 0 <--
|
||||
|
||||
ID_W Fetch 0 <--
|
||||
ID_W Data 0 <--
|
||||
ID_W Memory_Ack 0 <--
|
||||
ID_W DMA_READ 0 <--
|
||||
ID_W DMA_WRITE 0 <--
|
||||
|
||||
M Data 103
|
||||
M DMA_READ 0 <--
|
||||
M DMA_WRITE 0 <--
|
||||
M CleanReplacement 436
|
||||
|
||||
IM Fetch 0 <--
|
||||
IM Data 0 <--
|
||||
IM Memory_Data 547
|
||||
IM DMA_READ 0 <--
|
||||
IM DMA_WRITE 0 <--
|
||||
|
||||
MI Fetch 0 <--
|
||||
MI Data 0 <--
|
||||
MI Memory_Ack 103
|
||||
MI DMA_READ 0 <--
|
||||
MI DMA_WRITE 0 <--
|
||||
|
||||
M_DRD Data 0 <--
|
||||
M_DRD DMA_READ 0 <--
|
||||
M_DRD DMA_WRITE 0 <--
|
||||
|
||||
M_DRDI Fetch 0 <--
|
||||
M_DRDI Data 0 <--
|
||||
M_DRDI Memory_Ack 0 <--
|
||||
M_DRDI DMA_READ 0 <--
|
||||
M_DRDI DMA_WRITE 0 <--
|
||||
|
||||
M_DWR Data 0 <--
|
||||
M_DWR DMA_READ 0 <--
|
||||
M_DWR DMA_WRITE 0 <--
|
||||
|
||||
M_DWRI Fetch 0 <--
|
||||
M_DWRI Data 0 <--
|
||||
M_DWRI Memory_Ack 0 <--
|
||||
M_DWRI DMA_READ 0 <--
|
||||
M_DWRI DMA_WRITE 0 <--
|
||||
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 28 2010 13:54:58
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 13:57:44
|
||||
M5 executing on svvint03
|
||||
command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 103637 because target called exit()
|
||||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 10832 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 1360528 # Number of bytes of host memory used
|
||||
host_seconds 0.24 # Real time elapsed on the host
|
||||
host_tick_rate 5450330 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 21475 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214848 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
host_tick_rate 863649 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_seconds 0.000001 # Number of seconds simulated
|
||||
sim_ticks 1297500 # Number of ticks simulated
|
||||
sim_seconds 0.000104 # Number of seconds simulated
|
||||
sim_ticks 103637 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 717 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 709 # DTB hits
|
||||
|
|
@ -29,9 +29,9 @@ system.cpu.itb.data_accesses 0 # DT
|
|||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 2596 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 2597 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 2585 # ITB hits
|
||||
system.cpu.itb.fetch_hits 2586 # ITB hits
|
||||
system.cpu.itb.fetch_misses 11 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
|
|
@ -42,7 +42,7 @@ system.cpu.itb.write_acv 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 2596 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 103637 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2577 # Number of instructions executed
|
||||
system.cpu.num_refs 717 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
|
@ -0,0 +1,277 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
checker=Null
|
||||
clock=1
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
buffer_size=0
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
request_latency=2
|
||||
response_latency=2
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links2.ext_node
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links2.ext_node.directory
|
||||
directory_latency=6
|
||||
memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
size=134217728
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=0
|
||||
node_b=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=1
|
||||
node_b=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links2]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=2
|
||||
node_b=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
|
||||
[system.ruby.tracer]
|
||||
type=RubyTracer
|
||||
warmup_length=100000
|
||||
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,5 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 28 2010 14:49:51
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 15:08:15
|
||||
M5 executing on svvint05
|
||||
command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 85988 because target called exit()
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 14317 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214996 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
host_tick_rate 477706 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_seconds 0.000086 # Number of seconds simulated
|
||||
sim_ticks 85988 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 717 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 709 # DTB hits
|
||||
system.cpu.dtb.data_misses 8 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 419 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 415 # DTB read hits
|
||||
system.cpu.dtb.read_misses 4 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 298 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 294 # DTB write hits
|
||||
system.cpu.dtb.write_misses 4 # DTB write misses
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 2597 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 2586 # ITB hits
|
||||
system.cpu.itb.fetch_misses 11 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 85988 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2577 # Number of instructions executed
|
||||
system.cpu.num_refs 717 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -0,0 +1,287 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
checker=Null
|
||||
clock=1
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2
|
||||
num_int_nodes=4
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
dynamic_timeout_enabled=true
|
||||
fixed_timeout_latency=300
|
||||
l1_request_latency=2
|
||||
l1_response_latency=2
|
||||
l2_select_num_bits=0
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
retry_threshold=1
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=L2Cache_Controller
|
||||
children=L2cacheMemory
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
N_tokens=2
|
||||
buffer_size=0
|
||||
filtering_enabled=true
|
||||
l2_request_latency=10
|
||||
l2_response_latency=10
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links2]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links2.ext_node
|
||||
int_node=2
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links2.ext_node.directory
|
||||
directory_latency=6
|
||||
distributed_persistent=true
|
||||
fixed_timeout_latency=300
|
||||
l2_select_num_bits=0
|
||||
memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
size=134217728
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links2.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=0
|
||||
node_b=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=1
|
||||
node_b=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links2]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=2
|
||||
node_b=3
|
||||
weight=1
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
|
||||
[system.ruby.tracer]
|
||||
type=RubyTracer
|
||||
warmup_length=100000
|
||||
|
||||
|
|
@ -0,0 +1,912 @@
|
|||
|
||||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
RubySystem config:
|
||||
random_seed: 1234
|
||||
randomization: 0
|
||||
cycle_period: 1
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 134217728
|
||||
memory_size_bits: 27
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, unordered
|
||||
virtual_net_2: active, ordered
|
||||
virtual_net_3: active, unordered
|
||||
virtual_net_4: active, unordered
|
||||
virtual_net_5: active, ordered
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
virtual_net_9: inactive
|
||||
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
periodic_stats_period: 1000000
|
||||
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/28/2010 15:55:46
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.35
|
||||
Virtual_time_in_minutes: 0.00583333
|
||||
Virtual_time_in_hours: 9.72222e-05
|
||||
Virtual_time_in_days: 4.05093e-06
|
||||
|
||||
Ruby_current_time: 90308
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 90308
|
||||
|
||||
mbytes_resident: 33.1172
|
||||
mbytes_total: 33.125
|
||||
resident_ratio: 1
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
ruby_cycles_executed: 90309 [ 90309 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
L2Cache-0:0
|
||||
Directory-0:0
|
||||
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 283 count: 3294 average: 26.4159 | standard deviation: 58.1846 | 0 2776 0 0 0 0 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 89 61 81 78 45 5 4 1 0 2 20 13 13 11 10 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_1: [binsize: 2 max: 283 count: 2585 average: 19.2785 | standard deviation: 49.8133 | 0 2315 0 0 0 0 0 0 0 0 0 0 0 26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44 44 38 49 22 3 4 0 0 0 9 11 3 8 6 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 2 max: 273 count: 415 average: 66.3494 | standard deviation: 81.4668 | 0 233 0 0 0 0 0 0 0 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 15 34 18 20 1 0 1 0 2 6 2 10 2 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 2 max: 259 count: 294 average: 32.8027 | standard deviation: 63.5503 | 0 228 0 0 0 0 0 0 0 0 0 0 0 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 2 9 11 3 1 0 0 0 0 5 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 7136
|
||||
page_faults: 2141
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.160659
|
||||
links_utilized_percent_switch_0_link_0: 0.0646399 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.256677 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 442 31824 [ 0 442 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 76 5472 [ 0 76 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Control: 8 64 [ 0 8 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 518 4144 [ 0 0 0 0 518 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 452 32544 [ 0 452 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 50 400 [ 0 50 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.0939286
|
||||
links_utilized_percent_switch_1_link_0: 0.0641693 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.123688 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 518 4144 [ 0 0 0 0 518 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 452 32544 [ 0 452 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 50 400 [ 0 50 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Request_Control: 447 3576 [ 0 0 0 447 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 76 5472 [ 0 76 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Control: 8 64 [ 0 8 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Data: 81 5832 [ 0 81 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 366 2928 [ 0 366 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.120795
|
||||
links_utilized_percent_switch_2_link_0: 0.0213436 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.220246 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Request_Control: 447 3576 [ 0 0 0 447 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Data: 81 5832 [ 0 81 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 366 2928 [ 0 366 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Response_Data: 442 31824 [ 0 442 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 0.200204
|
||||
links_utilized_percent_switch_3_link_0: 0.25856 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.256677 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0.0853745 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 442 31824 [ 0 442 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 76 5472 [ 0 76 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Response_Control: 8 64 [ 0 8 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Request_Control: 518 4144 [ 0 0 0 0 518 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Data: 452 32544 [ 0 452 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Writeback_Control: 50 400 [ 0 50 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Request_Control: 447 3576 [ 0 0 0 447 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Data: 81 5832 [ 0 81 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_2_Writeback_Control: 366 2928 [ 0 366 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
--- L1Cache 0 ---
|
||||
- Event Counts -
|
||||
Load 415
|
||||
Ifetch 2585
|
||||
Store 294
|
||||
L1_Replacement 502
|
||||
Data_Shared 59
|
||||
Data_Owner 0
|
||||
Data_All_Tokens 459
|
||||
Ack 8
|
||||
Ack_All_Tokens 0
|
||||
Transient_GETX 0
|
||||
Transient_Local_GETX 0
|
||||
Transient_GETS 0
|
||||
Transient_Local_GETS 0
|
||||
Transient_GETS_Last_Token 0
|
||||
Transient_Local_GETS_Last_Token 0
|
||||
Persistent_GETX 0
|
||||
Persistent_GETS 0
|
||||
Own_Lock_or_Unlock 0
|
||||
Request_Timeout 0
|
||||
Use_TimeoutStarverX 0
|
||||
Use_TimeoutStarverS 0
|
||||
Use_TimeoutNoStarvers 458
|
||||
|
||||
- Transitions -
|
||||
NP Load 182
|
||||
NP Ifetch 270
|
||||
NP Store 58
|
||||
NP Data_Shared 0 <--
|
||||
NP Data_Owner 0 <--
|
||||
NP Data_All_Tokens 0 <--
|
||||
NP Ack 0 <--
|
||||
NP Transient_GETX 0 <--
|
||||
NP Transient_Local_GETX 0 <--
|
||||
NP Transient_GETS 0 <--
|
||||
NP Transient_Local_GETS 0 <--
|
||||
NP Persistent_GETX 0 <--
|
||||
NP Persistent_GETS 0 <--
|
||||
NP Own_Lock_or_Unlock 0 <--
|
||||
|
||||
I Load 0 <--
|
||||
I Ifetch 0 <--
|
||||
I Store 0 <--
|
||||
I L1_Replacement 0 <--
|
||||
I Data_Shared 0 <--
|
||||
I Data_Owner 0 <--
|
||||
I Data_All_Tokens 0 <--
|
||||
I Ack 0 <--
|
||||
I Transient_GETX 0 <--
|
||||
I Transient_Local_GETX 0 <--
|
||||
I Transient_GETS 0 <--
|
||||
I Transient_Local_GETS 0 <--
|
||||
I Transient_GETS_Last_Token 0 <--
|
||||
I Transient_Local_GETS_Last_Token 0 <--
|
||||
I Persistent_GETX 0 <--
|
||||
I Persistent_GETS 0 <--
|
||||
I Own_Lock_or_Unlock 0 <--
|
||||
|
||||
S Load 30
|
||||
S Ifetch 188
|
||||
S Store 8
|
||||
S L1_Replacement 50
|
||||
S Data_Shared 0 <--
|
||||
S Data_Owner 0 <--
|
||||
S Data_All_Tokens 0 <--
|
||||
S Ack 0 <--
|
||||
S Transient_GETX 0 <--
|
||||
S Transient_Local_GETX 0 <--
|
||||
S Transient_GETS 0 <--
|
||||
S Transient_Local_GETS 0 <--
|
||||
S Transient_GETS_Last_Token 0 <--
|
||||
S Transient_Local_GETS_Last_Token 0 <--
|
||||
S Persistent_GETX 0 <--
|
||||
S Persistent_GETS 0 <--
|
||||
S Own_Lock_or_Unlock 0 <--
|
||||
|
||||
O Load 0 <--
|
||||
O Ifetch 0 <--
|
||||
O Store 0 <--
|
||||
O L1_Replacement 0 <--
|
||||
O Data_Shared 0 <--
|
||||
O Data_All_Tokens 0 <--
|
||||
O Ack 0 <--
|
||||
O Ack_All_Tokens 0 <--
|
||||
O Transient_GETX 0 <--
|
||||
O Transient_Local_GETX 0 <--
|
||||
O Transient_GETS 0 <--
|
||||
O Transient_Local_GETS 0 <--
|
||||
O Transient_GETS_Last_Token 0 <--
|
||||
O Transient_Local_GETS_Last_Token 0 <--
|
||||
O Persistent_GETX 0 <--
|
||||
O Persistent_GETS 0 <--
|
||||
O Own_Lock_or_Unlock 0 <--
|
||||
|
||||
M Load 67
|
||||
M Ifetch 1196
|
||||
M Store 29
|
||||
M L1_Replacement 356
|
||||
M Transient_GETX 0 <--
|
||||
M Transient_Local_GETX 0 <--
|
||||
M Transient_GETS 0 <--
|
||||
M Transient_Local_GETS 0 <--
|
||||
M Persistent_GETX 0 <--
|
||||
M Persistent_GETS 0 <--
|
||||
M Own_Lock_or_Unlock 0 <--
|
||||
|
||||
MM Load 96
|
||||
MM Ifetch 0 <--
|
||||
MM Store 111
|
||||
MM L1_Replacement 96
|
||||
MM Transient_GETX 0 <--
|
||||
MM Transient_Local_GETX 0 <--
|
||||
MM Transient_GETS 0 <--
|
||||
MM Transient_Local_GETS 0 <--
|
||||
MM Persistent_GETX 0 <--
|
||||
MM Persistent_GETS 0 <--
|
||||
MM Own_Lock_or_Unlock 0 <--
|
||||
|
||||
M_W Load 34
|
||||
M_W Ifetch 931
|
||||
M_W Store 3
|
||||
M_W L1_Replacement 0 <--
|
||||
M_W Transient_GETX 0 <--
|
||||
M_W Transient_Local_GETX 0 <--
|
||||
M_W Transient_GETS 0 <--
|
||||
M_W Transient_Local_GETS 0 <--
|
||||
M_W Persistent_GETX 0 <--
|
||||
M_W Persistent_GETS 0 <--
|
||||
M_W Own_Lock_or_Unlock 0 <--
|
||||
M_W Use_TimeoutStarverX 0 <--
|
||||
M_W Use_TimeoutStarverS 0 <--
|
||||
M_W Use_TimeoutNoStarvers 389
|
||||
|
||||
MM_W Load 6
|
||||
MM_W Ifetch 0 <--
|
||||
MM_W Store 85
|
||||
MM_W L1_Replacement 0 <--
|
||||
MM_W Transient_GETX 0 <--
|
||||
MM_W Transient_Local_GETX 0 <--
|
||||
MM_W Transient_GETS 0 <--
|
||||
MM_W Transient_Local_GETS 0 <--
|
||||
MM_W Persistent_GETX 0 <--
|
||||
MM_W Persistent_GETS 0 <--
|
||||
MM_W Own_Lock_or_Unlock 0 <--
|
||||
MM_W Use_TimeoutStarverX 0 <--
|
||||
MM_W Use_TimeoutStarverS 0 <--
|
||||
MM_W Use_TimeoutNoStarvers 69
|
||||
|
||||
IM Load 0 <--
|
||||
IM Ifetch 0 <--
|
||||
IM Store 0 <--
|
||||
IM L1_Replacement 0 <--
|
||||
IM Data_Shared 0 <--
|
||||
IM Data_Owner 0 <--
|
||||
IM Data_All_Tokens 58
|
||||
IM Ack 1
|
||||
IM Transient_GETX 0 <--
|
||||
IM Transient_Local_GETX 0 <--
|
||||
IM Transient_GETS 0 <--
|
||||
IM Transient_Local_GETS 0 <--
|
||||
IM Transient_GETS_Last_Token 0 <--
|
||||
IM Transient_Local_GETS_Last_Token 0 <--
|
||||
IM Persistent_GETX 0 <--
|
||||
IM Persistent_GETS 0 <--
|
||||
IM Own_Lock_or_Unlock 0 <--
|
||||
IM Request_Timeout 0 <--
|
||||
|
||||
SM Load 0 <--
|
||||
SM Ifetch 0 <--
|
||||
SM Store 0 <--
|
||||
SM L1_Replacement 0 <--
|
||||
SM Data_Shared 0 <--
|
||||
SM Data_Owner 0 <--
|
||||
SM Data_All_Tokens 8
|
||||
SM Ack 0 <--
|
||||
SM Transient_GETX 0 <--
|
||||
SM Transient_Local_GETX 0 <--
|
||||
SM Transient_GETS 0 <--
|
||||
SM Transient_Local_GETS 0 <--
|
||||
SM Transient_GETS_Last_Token 0 <--
|
||||
SM Transient_Local_GETS_Last_Token 0 <--
|
||||
SM Persistent_GETX 0 <--
|
||||
SM Persistent_GETS 0 <--
|
||||
SM Own_Lock_or_Unlock 0 <--
|
||||
SM Request_Timeout 0 <--
|
||||
|
||||
OM Load 0 <--
|
||||
OM Ifetch 0 <--
|
||||
OM Store 0 <--
|
||||
OM L1_Replacement 0 <--
|
||||
OM Data_Shared 0 <--
|
||||
OM Data_All_Tokens 0 <--
|
||||
OM Ack 0 <--
|
||||
OM Ack_All_Tokens 0 <--
|
||||
OM Transient_GETX 0 <--
|
||||
OM Transient_Local_GETX 0 <--
|
||||
OM Transient_GETS 0 <--
|
||||
OM Transient_Local_GETS 0 <--
|
||||
OM Transient_GETS_Last_Token 0 <--
|
||||
OM Transient_Local_GETS_Last_Token 0 <--
|
||||
OM Persistent_GETX 0 <--
|
||||
OM Persistent_GETS 0 <--
|
||||
OM Own_Lock_or_Unlock 0 <--
|
||||
OM Request_Timeout 0 <--
|
||||
|
||||
IS Load 0 <--
|
||||
IS Ifetch 0 <--
|
||||
IS Store 0 <--
|
||||
IS L1_Replacement 0 <--
|
||||
IS Data_Shared 59
|
||||
IS Data_Owner 0 <--
|
||||
IS Data_All_Tokens 393
|
||||
IS Ack 7
|
||||
IS Transient_GETX 0 <--
|
||||
IS Transient_Local_GETX 0 <--
|
||||
IS Transient_GETS 0 <--
|
||||
IS Transient_Local_GETS 0 <--
|
||||
IS Transient_GETS_Last_Token 0 <--
|
||||
IS Transient_Local_GETS_Last_Token 0 <--
|
||||
IS Persistent_GETX 0 <--
|
||||
IS Persistent_GETS 0 <--
|
||||
IS Own_Lock_or_Unlock 0 <--
|
||||
IS Request_Timeout 0 <--
|
||||
|
||||
I_L Load 0 <--
|
||||
I_L Ifetch 0 <--
|
||||
I_L Store 0 <--
|
||||
I_L L1_Replacement 0 <--
|
||||
I_L Data_Shared 0 <--
|
||||
I_L Data_Owner 0 <--
|
||||
I_L Data_All_Tokens 0 <--
|
||||
I_L Ack 0 <--
|
||||
I_L Transient_GETX 0 <--
|
||||
I_L Transient_Local_GETX 0 <--
|
||||
I_L Transient_GETS 0 <--
|
||||
I_L Transient_Local_GETS 0 <--
|
||||
I_L Transient_GETS_Last_Token 0 <--
|
||||
I_L Transient_Local_GETS_Last_Token 0 <--
|
||||
I_L Persistent_GETX 0 <--
|
||||
I_L Persistent_GETS 0 <--
|
||||
I_L Own_Lock_or_Unlock 0 <--
|
||||
|
||||
S_L Load 0 <--
|
||||
S_L Ifetch 0 <--
|
||||
S_L Store 0 <--
|
||||
S_L L1_Replacement 0 <--
|
||||
S_L Data_Shared 0 <--
|
||||
S_L Data_Owner 0 <--
|
||||
S_L Data_All_Tokens 0 <--
|
||||
S_L Ack 0 <--
|
||||
S_L Transient_GETX 0 <--
|
||||
S_L Transient_Local_GETX 0 <--
|
||||
S_L Transient_GETS 0 <--
|
||||
S_L Transient_Local_GETS 0 <--
|
||||
S_L Transient_GETS_Last_Token 0 <--
|
||||
S_L Transient_Local_GETS_Last_Token 0 <--
|
||||
S_L Persistent_GETX 0 <--
|
||||
S_L Persistent_GETS 0 <--
|
||||
S_L Own_Lock_or_Unlock 0 <--
|
||||
|
||||
IM_L Load 0 <--
|
||||
IM_L Ifetch 0 <--
|
||||
IM_L Store 0 <--
|
||||
IM_L L1_Replacement 0 <--
|
||||
IM_L Data_Shared 0 <--
|
||||
IM_L Data_Owner 0 <--
|
||||
IM_L Data_All_Tokens 0 <--
|
||||
IM_L Ack 0 <--
|
||||
IM_L Transient_GETX 0 <--
|
||||
IM_L Transient_Local_GETX 0 <--
|
||||
IM_L Transient_GETS 0 <--
|
||||
IM_L Transient_Local_GETS 0 <--
|
||||
IM_L Transient_GETS_Last_Token 0 <--
|
||||
IM_L Transient_Local_GETS_Last_Token 0 <--
|
||||
IM_L Persistent_GETX 0 <--
|
||||
IM_L Persistent_GETS 0 <--
|
||||
IM_L Own_Lock_or_Unlock 0 <--
|
||||
IM_L Request_Timeout 0 <--
|
||||
|
||||
SM_L Load 0 <--
|
||||
SM_L Ifetch 0 <--
|
||||
SM_L Store 0 <--
|
||||
SM_L L1_Replacement 0 <--
|
||||
SM_L Data_Shared 0 <--
|
||||
SM_L Data_Owner 0 <--
|
||||
SM_L Data_All_Tokens 0 <--
|
||||
SM_L Ack 0 <--
|
||||
SM_L Transient_GETX 0 <--
|
||||
SM_L Transient_Local_GETX 0 <--
|
||||
SM_L Transient_GETS 0 <--
|
||||
SM_L Transient_Local_GETS 0 <--
|
||||
SM_L Transient_GETS_Last_Token 0 <--
|
||||
SM_L Transient_Local_GETS_Last_Token 0 <--
|
||||
SM_L Persistent_GETX 0 <--
|
||||
SM_L Persistent_GETS 0 <--
|
||||
SM_L Own_Lock_or_Unlock 0 <--
|
||||
SM_L Request_Timeout 0 <--
|
||||
|
||||
IS_L Load 0 <--
|
||||
IS_L Ifetch 0 <--
|
||||
IS_L Store 0 <--
|
||||
IS_L L1_Replacement 0 <--
|
||||
IS_L Data_Shared 0 <--
|
||||
IS_L Data_Owner 0 <--
|
||||
IS_L Data_All_Tokens 0 <--
|
||||
IS_L Ack 0 <--
|
||||
IS_L Transient_GETX 0 <--
|
||||
IS_L Transient_Local_GETX 0 <--
|
||||
IS_L Transient_GETS 0 <--
|
||||
IS_L Transient_Local_GETS 0 <--
|
||||
IS_L Transient_GETS_Last_Token 0 <--
|
||||
IS_L Transient_Local_GETS_Last_Token 0 <--
|
||||
IS_L Persistent_GETX 0 <--
|
||||
IS_L Persistent_GETS 0 <--
|
||||
IS_L Own_Lock_or_Unlock 0 <--
|
||||
IS_L Request_Timeout 0 <--
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
--- L2Cache 0 ---
|
||||
- Event Counts -
|
||||
L1_GETS 445
|
||||
L1_GETS_Last_Token 7
|
||||
L1_GETX 66
|
||||
L1_INV 0
|
||||
Transient_GETX 0
|
||||
Transient_GETS 0
|
||||
Transient_GETS_Last_Token 0
|
||||
L2_Replacement 463
|
||||
Writeback_Tokens 27
|
||||
Writeback_Shared_Data 0
|
||||
Writeback_All_Tokens 475
|
||||
Writeback_Owned 0
|
||||
Data_Shared 0
|
||||
Data_Owner 0
|
||||
Data_All_Tokens 0
|
||||
Ack 0
|
||||
Ack_All_Tokens 0
|
||||
Persistent_GETX 0
|
||||
Persistent_GETS 0
|
||||
Own_Lock_or_Unlock 0
|
||||
|
||||
- Transitions -
|
||||
NP L1_GETS 386
|
||||
NP L1_GETX 48
|
||||
NP L1_INV 0 <--
|
||||
NP Transient_GETX 0 <--
|
||||
NP Transient_GETS 0 <--
|
||||
NP Writeback_Tokens 27
|
||||
NP Writeback_Shared_Data 0 <--
|
||||
NP Writeback_All_Tokens 444
|
||||
NP Writeback_Owned 0 <--
|
||||
NP Data_Shared 0 <--
|
||||
NP Data_Owner 0 <--
|
||||
NP Data_All_Tokens 0 <--
|
||||
NP Ack 0 <--
|
||||
NP Persistent_GETX 0 <--
|
||||
NP Persistent_GETS 0 <--
|
||||
NP Own_Lock_or_Unlock 0 <--
|
||||
|
||||
I L1_GETS 0 <--
|
||||
I L1_GETS_Last_Token 7
|
||||
I L1_GETX 1
|
||||
I L1_INV 0 <--
|
||||
I Transient_GETX 0 <--
|
||||
I Transient_GETS 0 <--
|
||||
I Transient_GETS_Last_Token 0 <--
|
||||
I L2_Replacement 34
|
||||
I Writeback_Tokens 0 <--
|
||||
I Writeback_Shared_Data 0 <--
|
||||
I Writeback_All_Tokens 8
|
||||
I Writeback_Owned 0 <--
|
||||
I Data_Shared 0 <--
|
||||
I Data_Owner 0 <--
|
||||
I Data_All_Tokens 0 <--
|
||||
I Ack 0 <--
|
||||
I Persistent_GETX 0 <--
|
||||
I Persistent_GETS 0 <--
|
||||
I Own_Lock_or_Unlock 0 <--
|
||||
|
||||
S L1_GETS 0 <--
|
||||
S L1_GETS_Last_Token 0 <--
|
||||
S L1_GETX 0 <--
|
||||
S L1_INV 0 <--
|
||||
S Transient_GETX 0 <--
|
||||
S Transient_GETS 0 <--
|
||||
S Transient_GETS_Last_Token 0 <--
|
||||
S L2_Replacement 0 <--
|
||||
S Writeback_Tokens 0 <--
|
||||
S Writeback_Shared_Data 0 <--
|
||||
S Writeback_All_Tokens 0 <--
|
||||
S Writeback_Owned 0 <--
|
||||
S Data_Shared 0 <--
|
||||
S Data_Owner 0 <--
|
||||
S Data_All_Tokens 0 <--
|
||||
S Ack 0 <--
|
||||
S Persistent_GETX 0 <--
|
||||
S Persistent_GETS 0 <--
|
||||
S Own_Lock_or_Unlock 0 <--
|
||||
|
||||
O L1_GETS 0 <--
|
||||
O L1_GETS_Last_Token 0 <--
|
||||
O L1_GETX 5
|
||||
O L1_INV 0 <--
|
||||
O Transient_GETX 0 <--
|
||||
O Transient_GETS 0 <--
|
||||
O Transient_GETS_Last_Token 0 <--
|
||||
O L2_Replacement 31
|
||||
O Writeback_Tokens 0 <--
|
||||
O Writeback_Shared_Data 0 <--
|
||||
O Writeback_All_Tokens 23
|
||||
O Data_Shared 0 <--
|
||||
O Data_All_Tokens 0 <--
|
||||
O Ack 0 <--
|
||||
O Ack_All_Tokens 0 <--
|
||||
O Persistent_GETX 0 <--
|
||||
O Persistent_GETS 0 <--
|
||||
O Own_Lock_or_Unlock 0 <--
|
||||
|
||||
M L1_GETS 59
|
||||
M L1_GETX 12
|
||||
M L1_INV 0 <--
|
||||
M Transient_GETX 0 <--
|
||||
M Transient_GETS 0 <--
|
||||
M L2_Replacement 398
|
||||
M Persistent_GETX 0 <--
|
||||
M Persistent_GETS 0 <--
|
||||
M Own_Lock_or_Unlock 0 <--
|
||||
|
||||
I_L L1_GETS 0 <--
|
||||
I_L L1_GETX 0 <--
|
||||
I_L L1_INV 0 <--
|
||||
I_L Transient_GETX 0 <--
|
||||
I_L Transient_GETS 0 <--
|
||||
I_L Transient_GETS_Last_Token 0 <--
|
||||
I_L L2_Replacement 0 <--
|
||||
I_L Writeback_Tokens 0 <--
|
||||
I_L Writeback_Shared_Data 0 <--
|
||||
I_L Writeback_All_Tokens 0 <--
|
||||
I_L Writeback_Owned 0 <--
|
||||
I_L Data_Shared 0 <--
|
||||
I_L Data_Owner 0 <--
|
||||
I_L Data_All_Tokens 0 <--
|
||||
I_L Ack 0 <--
|
||||
I_L Persistent_GETX 0 <--
|
||||
I_L Persistent_GETS 0 <--
|
||||
I_L Own_Lock_or_Unlock 0 <--
|
||||
|
||||
S_L L1_GETS 0 <--
|
||||
S_L L1_GETS_Last_Token 0 <--
|
||||
S_L L1_GETX 0 <--
|
||||
S_L L1_INV 0 <--
|
||||
S_L Transient_GETX 0 <--
|
||||
S_L Transient_GETS 0 <--
|
||||
S_L Transient_GETS_Last_Token 0 <--
|
||||
S_L L2_Replacement 0 <--
|
||||
S_L Writeback_Tokens 0 <--
|
||||
S_L Writeback_Shared_Data 0 <--
|
||||
S_L Writeback_All_Tokens 0 <--
|
||||
S_L Writeback_Owned 0 <--
|
||||
S_L Data_Shared 0 <--
|
||||
S_L Data_Owner 0 <--
|
||||
S_L Data_All_Tokens 0 <--
|
||||
S_L Ack 0 <--
|
||||
S_L Persistent_GETX 0 <--
|
||||
S_L Persistent_GETS 0 <--
|
||||
S_L Own_Lock_or_Unlock 0 <--
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer:
|
||||
memory_total_requests: 523
|
||||
memory_reads: 442
|
||||
memory_writes: 81
|
||||
memory_refreshes: 189
|
||||
memory_total_request_delays: 199
|
||||
memory_delays_per_request: 0.380497
|
||||
memory_delays_in_input_queue: 67
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 132
|
||||
memory_stalls_for_bank_busy: 41
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 7
|
||||
memory_stalls_for_bus: 80
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 4
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 19 10 0 41 20 19 31 22 5 3 6 4 21 40 20 3 4 6 7 14 10 16 14 41 16 5 5 12 12 18 14 65
|
||||
|
||||
--- Directory 0 ---
|
||||
- Event Counts -
|
||||
GETX 63
|
||||
GETS 409
|
||||
Lockdown 0
|
||||
Unlockdown 0
|
||||
Own_Lock_or_Unlock 0
|
||||
Data_Owner 6
|
||||
Data_All_Tokens 75
|
||||
Ack_Owner 25
|
||||
Ack_Owner_All_Tokens 323
|
||||
Tokens 0
|
||||
Ack_All_Tokens 18
|
||||
Request_Timeout 0
|
||||
Memory_Data 442
|
||||
Memory_Ack 81
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
DMA_WRITE_All_Tokens 0
|
||||
|
||||
- Transitions -
|
||||
O GETX 49
|
||||
O GETS 393
|
||||
O Lockdown 0 <--
|
||||
O Own_Lock_or_Unlock 0 <--
|
||||
O Data_Owner 0 <--
|
||||
O Data_All_Tokens 0 <--
|
||||
O Tokens 0 <--
|
||||
O Ack_All_Tokens 18
|
||||
O DMA_READ 0 <--
|
||||
O DMA_WRITE 0 <--
|
||||
O DMA_WRITE_All_Tokens 0 <--
|
||||
|
||||
NO GETX 5
|
||||
NO GETS 0 <--
|
||||
NO Lockdown 0 <--
|
||||
NO Own_Lock_or_Unlock 0 <--
|
||||
NO Data_Owner 6
|
||||
NO Data_All_Tokens 75
|
||||
NO Ack_Owner 25
|
||||
NO Ack_Owner_All_Tokens 323
|
||||
NO Tokens 0 <--
|
||||
NO DMA_READ 0 <--
|
||||
NO DMA_WRITE 0 <--
|
||||
|
||||
L GETX 0 <--
|
||||
L GETS 0 <--
|
||||
L Lockdown 0 <--
|
||||
L Unlockdown 0 <--
|
||||
L Own_Lock_or_Unlock 0 <--
|
||||
L Data_Owner 0 <--
|
||||
L Data_All_Tokens 0 <--
|
||||
L Ack_Owner 0 <--
|
||||
L Ack_Owner_All_Tokens 0 <--
|
||||
L Tokens 0 <--
|
||||
L DMA_READ 0 <--
|
||||
L DMA_WRITE 0 <--
|
||||
|
||||
O_W GETX 9
|
||||
O_W GETS 16
|
||||
O_W Lockdown 0 <--
|
||||
O_W Unlockdown 0 <--
|
||||
O_W Own_Lock_or_Unlock 0 <--
|
||||
O_W Data_Owner 0 <--
|
||||
O_W Ack_Owner 0 <--
|
||||
O_W Tokens 0 <--
|
||||
O_W Ack_All_Tokens 0 <--
|
||||
O_W Memory_Data 0 <--
|
||||
O_W Memory_Ack 81
|
||||
O_W DMA_READ 0 <--
|
||||
O_W DMA_WRITE 0 <--
|
||||
|
||||
L_O_W GETX 0 <--
|
||||
L_O_W GETS 0 <--
|
||||
L_O_W Lockdown 0 <--
|
||||
L_O_W Unlockdown 0 <--
|
||||
L_O_W Own_Lock_or_Unlock 0 <--
|
||||
L_O_W Data_Owner 0 <--
|
||||
L_O_W Ack_Owner 0 <--
|
||||
L_O_W Tokens 0 <--
|
||||
L_O_W Ack_All_Tokens 0 <--
|
||||
L_O_W Memory_Data 0 <--
|
||||
L_O_W Memory_Ack 0 <--
|
||||
L_O_W DMA_READ 0 <--
|
||||
L_O_W DMA_WRITE 0 <--
|
||||
|
||||
L_NO_W GETX 0 <--
|
||||
L_NO_W GETS 0 <--
|
||||
L_NO_W Lockdown 0 <--
|
||||
L_NO_W Unlockdown 0 <--
|
||||
L_NO_W Own_Lock_or_Unlock 0 <--
|
||||
L_NO_W Data_Owner 0 <--
|
||||
L_NO_W Ack_Owner 0 <--
|
||||
L_NO_W Tokens 0 <--
|
||||
L_NO_W Ack_All_Tokens 0 <--
|
||||
L_NO_W Memory_Data 0 <--
|
||||
L_NO_W DMA_READ 0 <--
|
||||
L_NO_W DMA_WRITE 0 <--
|
||||
|
||||
DR_L_W GETX 0 <--
|
||||
DR_L_W GETS 0 <--
|
||||
DR_L_W Lockdown 0 <--
|
||||
DR_L_W Unlockdown 0 <--
|
||||
DR_L_W Own_Lock_or_Unlock 0 <--
|
||||
DR_L_W Data_Owner 0 <--
|
||||
DR_L_W Ack_Owner 0 <--
|
||||
DR_L_W Tokens 0 <--
|
||||
DR_L_W Ack_All_Tokens 0 <--
|
||||
DR_L_W Request_Timeout 0 <--
|
||||
DR_L_W Memory_Data 0 <--
|
||||
DR_L_W DMA_READ 0 <--
|
||||
DR_L_W DMA_WRITE 0 <--
|
||||
|
||||
NO_W GETX 0 <--
|
||||
NO_W GETS 0 <--
|
||||
NO_W Lockdown 0 <--
|
||||
NO_W Unlockdown 0 <--
|
||||
NO_W Own_Lock_or_Unlock 0 <--
|
||||
NO_W Data_Owner 0 <--
|
||||
NO_W Ack_Owner 0 <--
|
||||
NO_W Tokens 0 <--
|
||||
NO_W Ack_All_Tokens 0 <--
|
||||
NO_W Memory_Data 442
|
||||
NO_W DMA_READ 0 <--
|
||||
NO_W DMA_WRITE 0 <--
|
||||
|
||||
O_DW_W GETX 0 <--
|
||||
O_DW_W GETS 0 <--
|
||||
O_DW_W Data_Owner 0 <--
|
||||
O_DW_W Ack_Owner 0 <--
|
||||
O_DW_W Tokens 0 <--
|
||||
O_DW_W Ack_All_Tokens 0 <--
|
||||
O_DW_W Memory_Ack 0 <--
|
||||
O_DW_W DMA_READ 0 <--
|
||||
O_DW_W DMA_WRITE 0 <--
|
||||
|
||||
O_DR_W GETX 0 <--
|
||||
O_DR_W GETS 0 <--
|
||||
O_DR_W Lockdown 0 <--
|
||||
O_DR_W Unlockdown 0 <--
|
||||
O_DR_W Own_Lock_or_Unlock 0 <--
|
||||
O_DR_W Data_Owner 0 <--
|
||||
O_DR_W Ack_Owner 0 <--
|
||||
O_DR_W Tokens 0 <--
|
||||
O_DR_W Ack_All_Tokens 0 <--
|
||||
O_DR_W Memory_Data 0 <--
|
||||
O_DR_W DMA_READ 0 <--
|
||||
O_DR_W DMA_WRITE 0 <--
|
||||
|
||||
O_DW GETX 0 <--
|
||||
O_DW GETS 0 <--
|
||||
O_DW Lockdown 0 <--
|
||||
O_DW Own_Lock_or_Unlock 0 <--
|
||||
O_DW Data_Owner 0 <--
|
||||
O_DW Data_All_Tokens 0 <--
|
||||
O_DW Ack_Owner 0 <--
|
||||
O_DW Ack_Owner_All_Tokens 0 <--
|
||||
O_DW Tokens 0 <--
|
||||
O_DW Ack_All_Tokens 0 <--
|
||||
O_DW DMA_READ 0 <--
|
||||
O_DW DMA_WRITE 0 <--
|
||||
|
||||
NO_DW GETX 0 <--
|
||||
NO_DW GETS 0 <--
|
||||
NO_DW Lockdown 0 <--
|
||||
NO_DW Own_Lock_or_Unlock 0 <--
|
||||
NO_DW Data_Owner 0 <--
|
||||
NO_DW Data_All_Tokens 0 <--
|
||||
NO_DW Tokens 0 <--
|
||||
NO_DW Request_Timeout 0 <--
|
||||
NO_DW DMA_READ 0 <--
|
||||
NO_DW DMA_WRITE 0 <--
|
||||
|
||||
NO_DR GETX 0 <--
|
||||
NO_DR GETS 0 <--
|
||||
NO_DR Lockdown 0 <--
|
||||
NO_DR Own_Lock_or_Unlock 0 <--
|
||||
NO_DR Data_Owner 0 <--
|
||||
NO_DR Data_All_Tokens 0 <--
|
||||
NO_DR Tokens 0 <--
|
||||
NO_DR Request_Timeout 0 <--
|
||||
NO_DR DMA_READ 0 <--
|
||||
NO_DR DMA_WRITE 0 <--
|
||||
|
||||
DW_L GETX 0 <--
|
||||
DW_L GETS 0 <--
|
||||
DW_L Lockdown 0 <--
|
||||
DW_L Unlockdown 0 <--
|
||||
DW_L Own_Lock_or_Unlock 0 <--
|
||||
DW_L Data_Owner 0 <--
|
||||
DW_L Data_All_Tokens 0 <--
|
||||
DW_L Ack_Owner 0 <--
|
||||
DW_L Ack_Owner_All_Tokens 0 <--
|
||||
DW_L Tokens 0 <--
|
||||
DW_L Request_Timeout 0 <--
|
||||
DW_L DMA_READ 0 <--
|
||||
DW_L DMA_WRITE 0 <--
|
||||
|
||||
DR_L GETX 0 <--
|
||||
DR_L GETS 0 <--
|
||||
DR_L Lockdown 0 <--
|
||||
DR_L Unlockdown 0 <--
|
||||
DR_L Own_Lock_or_Unlock 0 <--
|
||||
DR_L Data_Owner 0 <--
|
||||
DR_L Data_All_Tokens 0 <--
|
||||
DR_L Ack_Owner 0 <--
|
||||
DR_L Ack_Owner_All_Tokens 0 <--
|
||||
DR_L Tokens 0 <--
|
||||
DR_L Request_Timeout 0 <--
|
||||
DR_L DMA_READ 0 <--
|
||||
DR_L DMA_WRITE 0 <--
|
||||
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 28 2010 15:54:34
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 15:55:46
|
||||
M5 executing on svvint04
|
||||
command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 90308 because target called exit()
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 18406 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214900 # Number of bytes of host memory used
|
||||
host_seconds 0.15 # Real time elapsed on the host
|
||||
host_tick_rate 602029 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_seconds 0.000090 # Number of seconds simulated
|
||||
sim_ticks 90308 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 717 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 709 # DTB hits
|
||||
system.cpu.dtb.data_misses 8 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 419 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 415 # DTB read hits
|
||||
system.cpu.dtb.read_misses 4 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 298 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 294 # DTB write hits
|
||||
system.cpu.dtb.write_misses 4 # DTB write misses
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 2597 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 2586 # ITB hits
|
||||
system.cpu.itb.fetch_misses 11 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 90308 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2577 # Number of instructions executed
|
||||
system.cpu.num_refs 717 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -0,0 +1,249 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
checker=Null
|
||||
clock=1
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
progress_interval=0
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.itb]
|
||||
type=AlphaTLB
|
||||
size=48
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=L2cacheMemory sequencer
|
||||
L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
|
||||
buffer_size=0
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=15
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=512
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=dcache icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links1.ext_node.directory
|
||||
memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
|
||||
memory_controller_latency=12
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
size=134217728
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=0
|
||||
node_b=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=1
|
||||
node_b=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
|
||||
[system.ruby.tracer]
|
||||
type=RubyTracer
|
||||
warmup_length=100000
|
||||
|
||||
|
|
@ -0,0 +1,576 @@
|
|||
|
||||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
RubySystem config:
|
||||
random_seed: 1234
|
||||
randomization: 0
|
||||
cycle_period: 1
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 134217728
|
||||
memory_size_bits: 27
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, unordered
|
||||
virtual_net_1: active, unordered
|
||||
virtual_net_2: active, unordered
|
||||
virtual_net_3: active, unordered
|
||||
virtual_net_4: active, ordered
|
||||
virtual_net_5: active, ordered
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
virtual_net_9: inactive
|
||||
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
periodic_stats_period: 1000000
|
||||
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jan/28/2010 11:48:25
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.33
|
||||
Virtual_time_in_minutes: 0.0055
|
||||
Virtual_time_in_hours: 9.16667e-05
|
||||
Virtual_time_in_days: 3.81944e-06
|
||||
|
||||
Ruby_current_time: 81672
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 81672
|
||||
|
||||
mbytes_resident: 31.8555
|
||||
mbytes_total: 31.8633
|
||||
resident_ratio: 1
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
ruby_cycles_executed: 81673 [ 81673 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
Directory-0:0
|
||||
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 333 count: 3294 average: 23.7942 | standard deviation: 53.6415 | 0 2853 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 87 74 46 111 83 4 0 4 2 0 2 2 0 0 1 1 2 0 0 0 2 2 2 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_1: [binsize: 2 max: 243 count: 2585 average: 17.6507 | standard deviation: 45.0947 | 0 2337 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 47 26 56 63 2 0 2 1 0 1 2 0 0 0 1 1 0 0 0 1 1 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 2 max: 333 count: 415 average: 57.9108 | standard deviation: 76.4181 | 0 269 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 16 18 39 18 1 0 1 0 0 1 0 0 0 1 0 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 2 max: 333 count: 294 average: 29.6531 | standard deviation: 64.3241 | 0 247 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 11 2 16 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 1 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 6878
|
||||
page_faults: 2029
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.106447
|
||||
links_utilized_percent_switch_0_link_0: 0.0672507 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.145644 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 441 31752 [ 0 441 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 425 3400 [ 0 0 425 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Request_Control: 441 3528 [ 0 0 0 441 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Data: 81 5832 [ 81 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Writeback_Control: 769 6152 [ 344 0 0 425 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Unblock_Control: 440 3520 [ 440 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.152707
|
||||
links_utilized_percent_switch_1_link_0: 0.0364109 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.269003 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Request_Control: 441 3528 [ 0 0 0 441 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Data: 81 5832 [ 81 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Writeback_Control: 769 6152 [ 344 0 0 425 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Unblock_Control: 440 3520 [ 440 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 441 31752 [ 0 441 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 425 3400 [ 0 0 425 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0.207323
|
||||
links_utilized_percent_switch_2_link_0: 0.269003 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.145644 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 441 31752 [ 0 441 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 425 3400 [ 0 0 425 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Request_Control: 441 3528 [ 0 0 0 441 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Data: 81 5832 [ 81 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 344 0 0 425 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 440 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 248
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 248
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 100%
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 248 100%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 4 count: 248 average: 4 | standard deviation: 0 | 0 0 0 0 248 ]
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 193
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 193
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: inf
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_LD: 75.6477%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_ST: 24.3523%
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 193 100%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 8 count: 193 average: 7.25389 | standard deviation: 1.56292 | 0 0 0 0 36 0 0 0 157 ]
|
||||
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_misses_per_transaction: nan
|
||||
|
||||
system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
--- L1Cache 0 ---
|
||||
- Event Counts -
|
||||
Load 437
|
||||
Ifetch 2603
|
||||
Store 306
|
||||
L2_Replacement 425
|
||||
L1_to_L2 502
|
||||
L2_to_L1D 47
|
||||
L2_to_L1I 22
|
||||
Other_GETX 0
|
||||
Other_GETS 0
|
||||
Ack 0
|
||||
Shared_Ack 0
|
||||
Data 0
|
||||
Shared_Data 0
|
||||
Exclusive_Data 441
|
||||
Writeback_Ack 425
|
||||
Writeback_Nack 0
|
||||
All_acks 0
|
||||
All_acks_no_sharers 441
|
||||
|
||||
- Transitions -
|
||||
I Load 146
|
||||
I Ifetch 248
|
||||
I Store 47
|
||||
I L2_Replacement 0 <--
|
||||
I L1_to_L2 0 <--
|
||||
I L2_to_L1D 0 <--
|
||||
I L2_to_L1I 0 <--
|
||||
I Other_GETX 0 <--
|
||||
I Other_GETS 0 <--
|
||||
|
||||
S Load 0 <--
|
||||
S Ifetch 0 <--
|
||||
S Store 0 <--
|
||||
S L2_Replacement 0 <--
|
||||
S L1_to_L2 0 <--
|
||||
S L2_to_L1D 0 <--
|
||||
S L2_to_L1I 0 <--
|
||||
S Other_GETX 0 <--
|
||||
S Other_GETS 0 <--
|
||||
|
||||
O Load 0 <--
|
||||
O Ifetch 0 <--
|
||||
O Store 0 <--
|
||||
O L2_Replacement 0 <--
|
||||
O L1_to_L2 0 <--
|
||||
O L2_to_L1D 0 <--
|
||||
O L2_to_L1I 0 <--
|
||||
O Other_GETX 0 <--
|
||||
O Other_GETS 0 <--
|
||||
|
||||
M Load 131
|
||||
M Ifetch 2337
|
||||
M Store 36
|
||||
M L2_Replacement 344
|
||||
M L1_to_L2 397
|
||||
M L2_to_L1D 23
|
||||
M L2_to_L1I 22
|
||||
M Other_GETX 0 <--
|
||||
M Other_GETS 0 <--
|
||||
|
||||
MM Load 138
|
||||
MM Ifetch 0 <--
|
||||
MM Store 211
|
||||
MM L2_Replacement 81
|
||||
MM L1_to_L2 105
|
||||
MM L2_to_L1D 24
|
||||
MM L2_to_L1I 0 <--
|
||||
MM Other_GETX 0 <--
|
||||
MM Other_GETS 0 <--
|
||||
|
||||
IM Load 0 <--
|
||||
IM Ifetch 0 <--
|
||||
IM Store 0 <--
|
||||
IM L2_Replacement 0 <--
|
||||
IM L1_to_L2 0 <--
|
||||
IM Other_GETX 0 <--
|
||||
IM Other_GETS 0 <--
|
||||
IM Ack 0 <--
|
||||
IM Data 0 <--
|
||||
IM Exclusive_Data 47
|
||||
|
||||
SM Load 0 <--
|
||||
SM Ifetch 0 <--
|
||||
SM Store 0 <--
|
||||
SM L2_Replacement 0 <--
|
||||
SM L1_to_L2 0 <--
|
||||
SM Other_GETX 0 <--
|
||||
SM Other_GETS 0 <--
|
||||
SM Ack 0 <--
|
||||
SM Data 0 <--
|
||||
|
||||
OM Load 0 <--
|
||||
OM Ifetch 0 <--
|
||||
OM Store 0 <--
|
||||
OM L2_Replacement 0 <--
|
||||
OM L1_to_L2 0 <--
|
||||
OM Other_GETX 0 <--
|
||||
OM Other_GETS 0 <--
|
||||
OM Ack 0 <--
|
||||
OM All_acks 0 <--
|
||||
OM All_acks_no_sharers 0 <--
|
||||
|
||||
ISM Load 0 <--
|
||||
ISM Ifetch 0 <--
|
||||
ISM Store 0 <--
|
||||
ISM L2_Replacement 0 <--
|
||||
ISM L1_to_L2 0 <--
|
||||
ISM Ack 0 <--
|
||||
ISM All_acks_no_sharers 0 <--
|
||||
|
||||
M_W Load 0 <--
|
||||
M_W Ifetch 0 <--
|
||||
M_W Store 0 <--
|
||||
M_W L2_Replacement 0 <--
|
||||
M_W L1_to_L2 0 <--
|
||||
M_W Ack 0 <--
|
||||
M_W All_acks_no_sharers 394
|
||||
|
||||
MM_W Load 0 <--
|
||||
MM_W Ifetch 0 <--
|
||||
MM_W Store 0 <--
|
||||
MM_W L2_Replacement 0 <--
|
||||
MM_W L1_to_L2 0 <--
|
||||
MM_W Ack 0 <--
|
||||
MM_W All_acks_no_sharers 47
|
||||
|
||||
IS Load 0 <--
|
||||
IS Ifetch 0 <--
|
||||
IS Store 0 <--
|
||||
IS L2_Replacement 0 <--
|
||||
IS L1_to_L2 0 <--
|
||||
IS Other_GETX 0 <--
|
||||
IS Other_GETS 0 <--
|
||||
IS Ack 0 <--
|
||||
IS Shared_Ack 0 <--
|
||||
IS Data 0 <--
|
||||
IS Shared_Data 0 <--
|
||||
IS Exclusive_Data 394
|
||||
|
||||
SS Load 0 <--
|
||||
SS Ifetch 0 <--
|
||||
SS Store 0 <--
|
||||
SS L2_Replacement 0 <--
|
||||
SS L1_to_L2 0 <--
|
||||
SS Ack 0 <--
|
||||
SS Shared_Ack 0 <--
|
||||
SS All_acks 0 <--
|
||||
SS All_acks_no_sharers 0 <--
|
||||
|
||||
OI Load 0 <--
|
||||
OI Ifetch 0 <--
|
||||
OI Store 0 <--
|
||||
OI L2_Replacement 0 <--
|
||||
OI L1_to_L2 0 <--
|
||||
OI Other_GETX 0 <--
|
||||
OI Other_GETS 0 <--
|
||||
OI Writeback_Ack 0 <--
|
||||
|
||||
MI Load 22
|
||||
MI Ifetch 18
|
||||
MI Store 12
|
||||
MI L2_Replacement 0 <--
|
||||
MI L1_to_L2 0 <--
|
||||
MI Other_GETX 0 <--
|
||||
MI Other_GETS 0 <--
|
||||
MI Writeback_Ack 425
|
||||
|
||||
II Load 0 <--
|
||||
II Ifetch 0 <--
|
||||
II Store 0 <--
|
||||
II L2_Replacement 0 <--
|
||||
II L1_to_L2 0 <--
|
||||
II Other_GETX 0 <--
|
||||
II Other_GETS 0 <--
|
||||
II Writeback_Ack 0 <--
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
|
||||
memory_total_requests: 522
|
||||
memory_reads: 441
|
||||
memory_writes: 81
|
||||
memory_refreshes: 171
|
||||
memory_total_request_delays: 124
|
||||
memory_delays_per_request: 0.237548
|
||||
memory_delays_in_input_queue: 2
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 122
|
||||
memory_stalls_for_bank_busy: 45
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 8
|
||||
memory_stalls_for_bus: 23
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 46
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 18 10 0 36 20 19 31 22 5 4 7 4 22 41 22 3 4 6 7 13 10 18 14 41 16 5 5 12 13 18 14 62
|
||||
|
||||
--- Directory 0 ---
|
||||
- Event Counts -
|
||||
GETX 106
|
||||
GETS 464
|
||||
PUT 425
|
||||
Unblock 440
|
||||
Writeback_Clean 0
|
||||
Writeback_Dirty 0
|
||||
Writeback_Exclusive_Clean 344
|
||||
Writeback_Exclusive_Dirty 81
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
Memory_Data 441
|
||||
Memory_Ack 81
|
||||
Ack 0
|
||||
Shared_Ack 0
|
||||
Shared_Data 0
|
||||
Exclusive_Data 0
|
||||
All_acks_and_data 0
|
||||
All_acks_and_data_no_sharers 0
|
||||
|
||||
- Transitions -
|
||||
NO GETX 0 <--
|
||||
NO GETS 0 <--
|
||||
NO PUT 425
|
||||
NO DMA_READ 0 <--
|
||||
NO DMA_WRITE 0 <--
|
||||
|
||||
O GETX 0 <--
|
||||
O GETS 0 <--
|
||||
O PUT 0 <--
|
||||
O DMA_READ 0 <--
|
||||
O DMA_WRITE 0 <--
|
||||
|
||||
E GETX 47
|
||||
E GETS 394
|
||||
E PUT 0 <--
|
||||
E DMA_READ 0 <--
|
||||
E DMA_WRITE 0 <--
|
||||
|
||||
NO_B GETX 0 <--
|
||||
NO_B GETS 0 <--
|
||||
NO_B PUT 0 <--
|
||||
NO_B Unblock 440
|
||||
NO_B DMA_READ 0 <--
|
||||
NO_B DMA_WRITE 0 <--
|
||||
|
||||
O_B GETX 0 <--
|
||||
O_B GETS 0 <--
|
||||
O_B PUT 0 <--
|
||||
O_B Unblock 0 <--
|
||||
O_B DMA_READ 0 <--
|
||||
O_B DMA_WRITE 0 <--
|
||||
|
||||
NO_B_W GETX 0 <--
|
||||
NO_B_W GETS 0 <--
|
||||
NO_B_W PUT 0 <--
|
||||
NO_B_W Unblock 0 <--
|
||||
NO_B_W DMA_READ 0 <--
|
||||
NO_B_W DMA_WRITE 0 <--
|
||||
NO_B_W Memory_Data 441
|
||||
|
||||
O_B_W GETX 0 <--
|
||||
O_B_W GETS 0 <--
|
||||
O_B_W PUT 0 <--
|
||||
O_B_W Unblock 0 <--
|
||||
O_B_W DMA_READ 0 <--
|
||||
O_B_W DMA_WRITE 0 <--
|
||||
O_B_W Memory_Data 0 <--
|
||||
|
||||
NO_W GETX 0 <--
|
||||
NO_W GETS 0 <--
|
||||
NO_W PUT 0 <--
|
||||
NO_W DMA_READ 0 <--
|
||||
NO_W DMA_WRITE 0 <--
|
||||
NO_W Memory_Data 0 <--
|
||||
|
||||
O_W GETX 0 <--
|
||||
O_W GETS 0 <--
|
||||
O_W PUT 0 <--
|
||||
O_W DMA_READ 0 <--
|
||||
O_W DMA_WRITE 0 <--
|
||||
O_W Memory_Data 0 <--
|
||||
|
||||
NO_DW_B_W GETX 0 <--
|
||||
NO_DW_B_W GETS 0 <--
|
||||
NO_DW_B_W PUT 0 <--
|
||||
NO_DW_B_W DMA_READ 0 <--
|
||||
NO_DW_B_W DMA_WRITE 0 <--
|
||||
NO_DW_B_W Ack 0 <--
|
||||
NO_DW_B_W Exclusive_Data 0 <--
|
||||
NO_DW_B_W All_acks_and_data_no_sharers 0 <--
|
||||
|
||||
NO_DR_B_W GETX 0 <--
|
||||
NO_DR_B_W GETS 0 <--
|
||||
NO_DR_B_W PUT 0 <--
|
||||
NO_DR_B_W DMA_READ 0 <--
|
||||
NO_DR_B_W DMA_WRITE 0 <--
|
||||
NO_DR_B_W Memory_Data 0 <--
|
||||
NO_DR_B_W Ack 0 <--
|
||||
NO_DR_B_W Shared_Ack 0 <--
|
||||
NO_DR_B_W Shared_Data 0 <--
|
||||
NO_DR_B_W Exclusive_Data 0 <--
|
||||
|
||||
NO_DR_B_D GETX 0 <--
|
||||
NO_DR_B_D GETS 0 <--
|
||||
NO_DR_B_D PUT 0 <--
|
||||
NO_DR_B_D DMA_READ 0 <--
|
||||
NO_DR_B_D DMA_WRITE 0 <--
|
||||
NO_DR_B_D Ack 0 <--
|
||||
NO_DR_B_D Shared_Ack 0 <--
|
||||
NO_DR_B_D Shared_Data 0 <--
|
||||
NO_DR_B_D Exclusive_Data 0 <--
|
||||
NO_DR_B_D All_acks_and_data 0 <--
|
||||
NO_DR_B_D All_acks_and_data_no_sharers 0 <--
|
||||
|
||||
NO_DR_B GETX 0 <--
|
||||
NO_DR_B GETS 0 <--
|
||||
NO_DR_B PUT 0 <--
|
||||
NO_DR_B DMA_READ 0 <--
|
||||
NO_DR_B DMA_WRITE 0 <--
|
||||
NO_DR_B Ack 0 <--
|
||||
NO_DR_B Shared_Ack 0 <--
|
||||
NO_DR_B Shared_Data 0 <--
|
||||
NO_DR_B Exclusive_Data 0 <--
|
||||
NO_DR_B All_acks_and_data 0 <--
|
||||
NO_DR_B All_acks_and_data_no_sharers 0 <--
|
||||
|
||||
NO_DW_W GETX 0 <--
|
||||
NO_DW_W GETS 0 <--
|
||||
NO_DW_W PUT 0 <--
|
||||
NO_DW_W DMA_READ 0 <--
|
||||
NO_DW_W DMA_WRITE 0 <--
|
||||
NO_DW_W Memory_Ack 0 <--
|
||||
|
||||
O_DR_B_W GETX 0 <--
|
||||
O_DR_B_W GETS 0 <--
|
||||
O_DR_B_W PUT 0 <--
|
||||
O_DR_B_W DMA_READ 0 <--
|
||||
O_DR_B_W DMA_WRITE 0 <--
|
||||
O_DR_B_W Memory_Data 0 <--
|
||||
|
||||
O_DR_B GETX 0 <--
|
||||
O_DR_B GETS 0 <--
|
||||
O_DR_B PUT 0 <--
|
||||
O_DR_B DMA_READ 0 <--
|
||||
O_DR_B DMA_WRITE 0 <--
|
||||
O_DR_B Ack 0 <--
|
||||
O_DR_B All_acks_and_data_no_sharers 0 <--
|
||||
|
||||
WB GETX 4
|
||||
WB GETS 15
|
||||
WB PUT 0 <--
|
||||
WB Unblock 0 <--
|
||||
WB Writeback_Clean 0 <--
|
||||
WB Writeback_Dirty 0 <--
|
||||
WB Writeback_Exclusive_Clean 344
|
||||
WB Writeback_Exclusive_Dirty 81
|
||||
WB DMA_READ 0 <--
|
||||
WB DMA_WRITE 0 <--
|
||||
|
||||
WB_O_W GETX 0 <--
|
||||
WB_O_W GETS 0 <--
|
||||
WB_O_W PUT 0 <--
|
||||
WB_O_W DMA_READ 0 <--
|
||||
WB_O_W DMA_WRITE 0 <--
|
||||
WB_O_W Memory_Ack 0 <--
|
||||
|
||||
WB_E_W GETX 55
|
||||
WB_E_W GETS 55
|
||||
WB_E_W PUT 0 <--
|
||||
WB_E_W DMA_READ 0 <--
|
||||
WB_E_W DMA_WRITE 0 <--
|
||||
WB_E_W Memory_Ack 81
|
||||
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
17
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
Executable file
17
tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
Executable file
|
|
@ -0,0 +1,17 @@
|
|||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 28 2010 11:30:01
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 11:48:25
|
||||
M5 executing on svvint06
|
||||
command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 81672 because target called exit()
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 32212 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 212236 # Number of bytes of host memory used
|
||||
host_seconds 0.08 # Real time elapsed on the host
|
||||
host_tick_rate 1020887 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_seconds 0.000082 # Number of seconds simulated
|
||||
sim_ticks 81672 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 717 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 709 # DTB hits
|
||||
system.cpu.dtb.data_misses 8 # DTB misses
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.read_accesses 419 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 415 # DTB read hits
|
||||
system.cpu.dtb.read_misses 4 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 298 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 294 # DTB write hits
|
||||
system.cpu.dtb.write_misses 4 # DTB write misses
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_hits 0 # DTB hits
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.fetch_accesses 2597 # ITB accesses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_hits 2586 # ITB hits
|
||||
system.cpu.itb.fetch_misses 11 # ITB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_acv 0 # DTB write access violations
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 81672 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2577 # Number of instructions executed
|
||||
system.cpu.num_refs 717 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -5,15 +5,15 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
children=cpu physmem ruby
|
||||
mem_mode=timing
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=TimingSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
clock=1
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
|
|
@ -32,8 +32,8 @@ progress_interval=0
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=AlphaTLB
|
||||
|
|
@ -54,7 +54,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
executable=tests/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -65,30 +65,169 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=RubyMemory
|
||||
clock=1
|
||||
config_file=build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby/ruby.config
|
||||
debug=false
|
||||
debug_file=ruby.debug
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30000
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
num_cpus=1
|
||||
phase=0
|
||||
range=0:134217727
|
||||
stats_file=ruby.stats
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links1.ext_node.directory
|
||||
directory_latency=12
|
||||
memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
size=134217728
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=0
|
||||
node_b=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=1
|
||||
node_b=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
|
||||
[system.ruby.tracer]
|
||||
type=RubyTracer
|
||||
warmup_length=100000
|
||||
|
||||
|
|
|
|||
|
|
@ -2,73 +2,18 @@
|
|||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
RubySystem config:
|
||||
random_seed: 752800
|
||||
random_seed: 1234
|
||||
randomization: 0
|
||||
tech_nm: 45
|
||||
freq_mhz: 3000
|
||||
cycle_period: 1
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 1073741824
|
||||
memory_size_bits: 30
|
||||
DMA_Controller config: DMAController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
dma_sequencer: DMASequencer_0
|
||||
number_of_TBEs: 128
|
||||
transitions_per_cycle: 32
|
||||
Directory_Controller config: DirectoryController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
directory_latency: 6
|
||||
directory_name: DirectoryMemory_0
|
||||
memory_controller_name: MemoryControl_0
|
||||
memory_latency: 158
|
||||
number_of_TBEs: 128
|
||||
recycle_latency: 10
|
||||
to_mem_ctrl_latency: 1
|
||||
transitions_per_cycle: 32
|
||||
L1Cache_Controller config: L1CacheController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
cache: l1u_0
|
||||
cache_response_latency: 12
|
||||
issue_latency: 2
|
||||
number_of_TBEs: 128
|
||||
sequencer: Sequencer_0
|
||||
transitions_per_cycle: 32
|
||||
Cache config: l1u_0
|
||||
controller: L1CacheController_0
|
||||
cache_associativity: 8
|
||||
num_cache_sets_bits: 2
|
||||
num_cache_sets: 4
|
||||
cache_set_size_bytes: 256
|
||||
cache_set_size_Kbytes: 0.25
|
||||
cache_set_size_Mbytes: 0.000244141
|
||||
cache_size_bytes: 2048
|
||||
cache_size_Kbytes: 2
|
||||
cache_size_Mbytes: 0.00195312
|
||||
DirectoryMemory Global Config:
|
||||
number of directory memories: 1
|
||||
total memory size bytes: 1073741824
|
||||
total memory size bits: 30
|
||||
DirectoryMemory module config: DirectoryMemory_0
|
||||
controller: DirectoryController_0
|
||||
version: 0
|
||||
memory_bits: 30
|
||||
memory_size_bytes: 1073741824
|
||||
memory_size_Kbytes: 1.04858e+06
|
||||
memory_size_Mbytes: 1024
|
||||
memory_size_Gbytes: 1
|
||||
Seqeuncer config: Sequencer_0
|
||||
controller: L1CacheController_0
|
||||
version: 0
|
||||
max_outstanding_requests: 16
|
||||
deadlock_threshold: 500000
|
||||
memory_size_bytes: 134217728
|
||||
memory_size_bits: 27
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology: theTopology
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
|
|
@ -76,25 +21,11 @@ virtual_net_2: active, ordered
|
|||
virtual_net_3: inactive
|
||||
virtual_net_4: active, ordered
|
||||
virtual_net_5: active, ordered
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
virtual_net_9: inactive
|
||||
|
||||
--- Begin Topology Print ---
|
||||
|
||||
Topology print ONLY indicates the _NETWORK_ latency between two machines
|
||||
It does NOT include the latency within the machines
|
||||
|
||||
L1Cache-0 Network Latencies
|
||||
L1Cache-0 -> Directory-0 net_lat: 7
|
||||
L1Cache-0 -> DMA-0 net_lat: 7
|
||||
|
||||
Directory-0 Network Latencies
|
||||
Directory-0 -> L1Cache-0 net_lat: 7
|
||||
Directory-0 -> DMA-0 net_lat: 7
|
||||
|
||||
DMA-0 Network Latencies
|
||||
DMA-0 -> L1Cache-0 net_lat: 7
|
||||
DMA-0 -> Directory-0 net_lat: 7
|
||||
|
||||
--- End Topology Print ---
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
|
|
@ -103,132 +34,61 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jul/06/2009 11:11:07
|
||||
Real time: Jan/28/2010 10:26:06
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.44
|
||||
Virtual_time_in_minutes: 0.00733333
|
||||
Virtual_time_in_hours: 0.000122222
|
||||
Virtual_time_in_days: 0.000122222
|
||||
Virtual_time_in_seconds: 0.25
|
||||
Virtual_time_in_minutes: 0.00416667
|
||||
Virtual_time_in_hours: 6.94444e-05
|
||||
Virtual_time_in_days: 2.89352e-06
|
||||
|
||||
Ruby_current_time: 9880001
|
||||
Ruby_start_time: 1
|
||||
Ruby_cycles: 9880000
|
||||
Ruby_current_time: 123378
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 123378
|
||||
|
||||
mbytes_resident: 143.812
|
||||
mbytes_total: 1328.75
|
||||
resident_ratio: 0.108234
|
||||
mbytes_resident: 32.8828
|
||||
mbytes_total: 32.8906
|
||||
resident_ratio: 1
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
instruction_executed: 1 [ 1 ]
|
||||
ruby_cycles_executed: 9880001 [ 9880001 ]
|
||||
cycles_per_instruction: 9.88e+06 [ 9.88e+06 ]
|
||||
misses_per_thousand_instructions: 0 [ 0 ]
|
||||
ruby_cycles_executed: 123379 [ 123379 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
instructions_per_transaction: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
|
||||
L1D_cache cache stats:
|
||||
L1D_cache_total_misses: 0
|
||||
L1D_cache_total_demand_misses: 0
|
||||
L1D_cache_total_prefetches: 0
|
||||
L1D_cache_total_sw_prefetches: 0
|
||||
L1D_cache_total_hw_prefetches: 0
|
||||
L1D_cache_misses_per_transaction: 0
|
||||
L1D_cache_misses_per_instruction: 0
|
||||
L1D_cache_instructions_per_misses: NaN
|
||||
|
||||
L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
L1I_cache cache stats:
|
||||
L1I_cache_total_misses: 0
|
||||
L1I_cache_total_demand_misses: 0
|
||||
L1I_cache_total_prefetches: 0
|
||||
L1I_cache_total_sw_prefetches: 0
|
||||
L1I_cache_total_hw_prefetches: 0
|
||||
L1I_cache_misses_per_transaction: 0
|
||||
L1I_cache_misses_per_instruction: 0
|
||||
L1I_cache_instructions_per_misses: NaN
|
||||
|
||||
L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
L2_cache cache stats:
|
||||
L2_cache_total_misses: 0
|
||||
L2_cache_total_demand_misses: 0
|
||||
L2_cache_total_prefetches: 0
|
||||
L2_cache_total_sw_prefetches: 0
|
||||
L2_cache_total_hw_prefetches: 0
|
||||
L2_cache_misses_per_transaction: 0
|
||||
L2_cache_misses_per_instruction: 0
|
||||
L2_cache_instructions_per_misses: NaN
|
||||
|
||||
L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
|
||||
Memory control:
|
||||
memory_total_requests: 658
|
||||
memory_reads: 345
|
||||
memory_writes: 313
|
||||
memory_refreshes: 6486
|
||||
memory_total_request_delays: 795
|
||||
memory_delays_per_request: 1.20821
|
||||
memory_delays_in_input_queue: 313
|
||||
memory_delays_behind_head_of_bank_queue: 1
|
||||
memory_delays_stalled_at_head_of_bank_queue: 481
|
||||
memory_stalls_for_bank_busy: 108
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 30
|
||||
memory_stalls_for_bus: 335
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 8
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 29 14 0 38 34 30 44 23 10 6 5 8 28 46 21 6 8 7 10 16 20 17 20 51 22 10 10 22 18 28 15 42
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
Directory-0:0
|
||||
DMA-0:0
|
||||
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
L2TBE_usage: [binsize: 1 max: 1 count: 658 average: 0.475684 | standard deviation: 0.50114 | 345 313 ]
|
||||
StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3294 average: 1 | standard deviation: 0 | 0 3294 ]
|
||||
store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 280 count: 3294 average: 19.8021 | standard deviation: 52.3549 | 0 2949 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28 0 0 0 0 4 0 0 0 0 283 0 0 0 0 7 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 7 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_1: [binsize: 2 max: 280 count: 2585 average: 15.4932 | standard deviation: 46.2081 | 0 2380 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 0 0 0 0 3 0 0 0 0 169 0 0 0 0 6 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 2 max: 270 count: 415 average: 44.4916 | standard deviation: 74.7872 | 0 312 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 86 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 1 max: 190 count: 294 average: 22.8367 | standard deviation: 55.1047 | 0 0 257 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
|
||||
miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency: [binsize: 2 max: 375 count: 3294 average: 36.4554 | standard deviation: 69.7725 | 0 2668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 3 1 1 4 2 101 88 63 177 126 0 1 1 8 0 2 1 1 4 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 4 5 13 2 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_1: [binsize: 2 max: 375 count: 2585 average: 23.1702 | standard deviation: 56.4841 | 0 2288 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 2 2 31 53 29 71 82 0 1 0 5 0 1 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 3 2 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_2: [binsize: 2 max: 281 count: 415 average: 107.304 | standard deviation: 88.8453 | 0 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 2 0 56 24 27 75 32 0 0 1 3 0 1 0 0 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 4 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 2 max: 265 count: 294 average: 53.2585 | standard deviation: 80.456 | 0 210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 14 11 7 31 12 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
|
@ -237,104 +97,159 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
|
|||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 658 average: 0 | standard deviation: 0 | 658 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 658 average: 0 | standard deviation: 0 | 658 ]
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 1248 average: 0 | standard deviation: 0 | 1248 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1248 average: 0 | standard deviation: 0 | 1248 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 345 average: 0 | standard deviation: 0 | 345 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 313 average: 0 | standard deviation: 0 | 313 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 626 average: 0 | standard deviation: 0 | 626 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 622 average: 0 | standard deviation: 0 | 622 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 37575
|
||||
page_faults: 0
|
||||
page_reclaims: 7118
|
||||
page_faults: 2103
|
||||
swaps: 0
|
||||
block_inputs: 8
|
||||
block_outputs: 48
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.000208122
|
||||
links_utilized_percent_switch_0_link_0: 8.3249e-05 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.000332996 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.157808
|
||||
links_utilized_percent_switch_0_link_0: 0.0633825 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.252233 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 345 2760 [ 0 345 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 313 2504 [ 0 0 313 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 345 2760 [ 345 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 313 2504 [ 313 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.000208122
|
||||
links_utilized_percent_switch_1_link_0: 8.3249e-05 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.000332996 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 0.158294
|
||||
links_utilized_percent_switch_1_link_0: 0.0630582 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.25353 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 345 2760 [ 345 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 313 2504 [ 313 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 345 2760 [ 0 345 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 313 2504 [ 0 0 313 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0
|
||||
links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.252881
|
||||
links_utilized_percent_switch_2_link_0: 0.25353 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.252233 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 626 45072 [ 0 626 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 622 4976 [ 0 0 622 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 626 5008 [ 626 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 622 44784 [ 622 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 0.000221997
|
||||
links_utilized_percent_switch_3_link_0: 0.000332996 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.000332996 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 626
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 626
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
|
||||
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 345 2760 [ 0 345 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 313 2504 [ 0 0 313 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 345 2760 [ 345 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Data: 313 2504 [ 313 0 0 0 0 0 ] base_latency: 1
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 39.1374%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 13.4185%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 47.4441%
|
||||
|
||||
--- DMA ---
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 626 100%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 626 average: 5.71885 | standard deviation: 1.98192 | 0 0 0 0 357 0 0 0 269 ]
|
||||
|
||||
--- L1Cache 0 ---
|
||||
- Event Counts -
|
||||
ReadRequest 0
|
||||
WriteRequest 0
|
||||
Data 0
|
||||
Ack 0
|
||||
Load 415
|
||||
Ifetch 2585
|
||||
Store 294
|
||||
Data 626
|
||||
Fwd_GETX 0
|
||||
Inv 0
|
||||
Replacement 622
|
||||
Writeback_Ack 622
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
READY ReadRequest 0 <--
|
||||
READY WriteRequest 0 <--
|
||||
I Load 245
|
||||
I Ifetch 297
|
||||
I Store 84
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
BUSY_RD Data 0 <--
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
BUSY_WR Ack 0 <--
|
||||
M Load 170
|
||||
M Ifetch 2288
|
||||
M Store 210
|
||||
M Fwd_GETX 0 <--
|
||||
M Inv 0 <--
|
||||
M Replacement 622
|
||||
|
||||
--- Directory ---
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 622
|
||||
MI Writeback_Nack 0 <--
|
||||
|
||||
MII Fwd_GETX 0 <--
|
||||
|
||||
IS Data 542
|
||||
|
||||
IM Data 84
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
|
||||
memory_total_requests: 1248
|
||||
memory_reads: 626
|
||||
memory_writes: 622
|
||||
memory_refreshes: 258
|
||||
memory_total_request_delays: 1710
|
||||
memory_delays_per_request: 1.37019
|
||||
memory_delays_in_input_queue: 622
|
||||
memory_delays_behind_head_of_bank_queue: 3
|
||||
memory_delays_stalled_at_head_of_bank_queue: 1085
|
||||
memory_stalls_for_bank_busy: 404
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 39
|
||||
memory_stalls_for_bus: 620
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 22
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 55 40 0 100 42 42 88 45 14 10 14 10 46 82 38 6 22 14 14 48 20 52 26 92 34 10 12 24 28 44 38 138
|
||||
|
||||
--- Directory 0 ---
|
||||
- Event Counts -
|
||||
GETX 345
|
||||
GETX 626
|
||||
GETS 0
|
||||
PUTX 313
|
||||
PUTX 622
|
||||
PUTX_NotOwner 0
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
Memory_Data 345
|
||||
Memory_Ack 313
|
||||
Memory_Data 626
|
||||
Memory_Ack 622
|
||||
|
||||
- Transitions -
|
||||
I GETX 345
|
||||
I GETX 626
|
||||
I PUTX_NotOwner 0 <--
|
||||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
|
||||
M GETX 0 <--
|
||||
M PUTX 313
|
||||
M PUTX 622
|
||||
M PUTX_NotOwner 0 <--
|
||||
M DMA_READ 0 <--
|
||||
M DMA_WRITE 0 <--
|
||||
|
|
@ -345,15 +260,19 @@ M_DRD PUTX 0 <--
|
|||
M_DWR GETX 0 <--
|
||||
M_DWR PUTX 0 <--
|
||||
|
||||
M_DWRI GETX 0 <--
|
||||
M_DWRI Memory_Ack 0 <--
|
||||
|
||||
M_DRDI GETX 0 <--
|
||||
M_DRDI Memory_Ack 0 <--
|
||||
|
||||
IM GETX 0 <--
|
||||
IM GETS 0 <--
|
||||
IM PUTX 0 <--
|
||||
IM PUTX_NotOwner 0 <--
|
||||
IM DMA_READ 0 <--
|
||||
IM DMA_WRITE 0 <--
|
||||
IM Memory_Data 345
|
||||
IM Memory_Data 626
|
||||
|
||||
MI GETX 0 <--
|
||||
MI GETS 0 <--
|
||||
|
|
@ -361,7 +280,7 @@ MI PUTX 0 <--
|
|||
MI PUTX_NotOwner 0 <--
|
||||
MI DMA_READ 0 <--
|
||||
MI DMA_WRITE 0 <--
|
||||
MI Memory_Ack 313
|
||||
MI Memory_Ack 622
|
||||
|
||||
ID GETX 0 <--
|
||||
ID GETS 0 <--
|
||||
|
|
@ -379,39 +298,3 @@ ID_W DMA_READ 0 <--
|
|||
ID_W DMA_WRITE 0 <--
|
||||
ID_W Memory_Ack 0 <--
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load 415
|
||||
Ifetch 2585
|
||||
Store 294
|
||||
Data 345
|
||||
Fwd_GETX 0
|
||||
Inv 0
|
||||
Replacement 313
|
||||
Writeback_Ack 313
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 103
|
||||
I Ifetch 205
|
||||
I Store 37
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 312
|
||||
M Ifetch 2380
|
||||
M Store 257
|
||||
M Fwd_GETX 0 <--
|
||||
M Inv 0 <--
|
||||
M Replacement 313
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 313
|
||||
|
||||
IS Data 308
|
||||
|
||||
IM Data 37
|
||||
|
||||
|
|
|
|||
|
|
@ -1,25 +1,5 @@
|
|||
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
|
||||
print config: 1
|
||||
Creating new MessageBuffer for 0 0
|
||||
Creating new MessageBuffer for 0 1
|
||||
Creating new MessageBuffer for 0 2
|
||||
Creating new MessageBuffer for 0 3
|
||||
Creating new MessageBuffer for 0 4
|
||||
Creating new MessageBuffer for 0 5
|
||||
Creating new MessageBuffer for 1 0
|
||||
Creating new MessageBuffer for 1 1
|
||||
Creating new MessageBuffer for 1 2
|
||||
Creating new MessageBuffer for 1 3
|
||||
Creating new MessageBuffer for 1 4
|
||||
Creating new MessageBuffer for 1 5
|
||||
Creating new MessageBuffer for 2 0
|
||||
Creating new MessageBuffer for 2 1
|
||||
Creating new MessageBuffer for 2 2
|
||||
Creating new MessageBuffer for 2 3
|
||||
Creating new MessageBuffer for 2 4
|
||||
Creating new MessageBuffer for 2 5
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
|
||||
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
|
||||
For more information see: http://www.m5sim.org/warn/5c5b547f
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,14 +5,13 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 6 2009 11:03:45
|
||||
M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
|
||||
M5 started Jul 6 2009 11:11:06
|
||||
M5 executing on maize
|
||||
M5 compiled Jan 27 2010 22:23:20
|
||||
M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate
|
||||
M5 started Jan 28 2010 10:26:06
|
||||
M5 executing on svvint07
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Debug: Adding to filter: 'q' (Queue)
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello world!
|
||||
Exiting @ tick 9880000 because target called exit()
|
||||
Exiting @ tick 123378 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 7760 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 1360644 # Number of bytes of host memory used
|
||||
host_seconds 0.33 # Real time elapsed on the host
|
||||
host_tick_rate 29737002 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 51538 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214632 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
host_tick_rate 2467461 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_seconds 0.000010 # Number of seconds simulated
|
||||
sim_ticks 9880000 # Number of ticks simulated
|
||||
sim_seconds 0.000123 # Number of seconds simulated
|
||||
sim_ticks 123378 # Number of ticks simulated
|
||||
system.cpu.dtb.data_accesses 717 # DTB accesses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_hits 709 # DTB hits
|
||||
|
|
@ -42,7 +42,7 @@ system.cpu.itb.write_acv 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 19760 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 123378 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2577 # Number of instructions executed
|
||||
system.cpu.num_refs 717 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,153 +0,0 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
CP0_Config=0
|
||||
CP0_Config1=0
|
||||
CP0_Config1_C2=false
|
||||
CP0_Config1_CA=false
|
||||
CP0_Config1_DA=0
|
||||
CP0_Config1_DL=0
|
||||
CP0_Config1_DS=0
|
||||
CP0_Config1_EP=false
|
||||
CP0_Config1_FP=false
|
||||
CP0_Config1_IA=0
|
||||
CP0_Config1_IL=0
|
||||
CP0_Config1_IS=0
|
||||
CP0_Config1_M=0
|
||||
CP0_Config1_MD=false
|
||||
CP0_Config1_MMU=0
|
||||
CP0_Config1_PC=false
|
||||
CP0_Config1_WR=false
|
||||
CP0_Config2=0
|
||||
CP0_Config2_M=false
|
||||
CP0_Config2_SA=0
|
||||
CP0_Config2_SL=0
|
||||
CP0_Config2_SS=0
|
||||
CP0_Config2_SU=0
|
||||
CP0_Config2_TA=0
|
||||
CP0_Config2_TL=0
|
||||
CP0_Config2_TS=0
|
||||
CP0_Config2_TU=0
|
||||
CP0_Config3=0
|
||||
CP0_Config3_DSPP=false
|
||||
CP0_Config3_LPA=false
|
||||
CP0_Config3_M=false
|
||||
CP0_Config3_MT=false
|
||||
CP0_Config3_SM=false
|
||||
CP0_Config3_SP=false
|
||||
CP0_Config3_TL=false
|
||||
CP0_Config3_VEIC=false
|
||||
CP0_Config3_VInt=false
|
||||
CP0_Config_AR=0
|
||||
CP0_Config_AT=0
|
||||
CP0_Config_BE=0
|
||||
CP0_Config_MT=0
|
||||
CP0_Config_VI=0
|
||||
CP0_EBase_CPUNum=0
|
||||
CP0_IntCtl_IPPCI=0
|
||||
CP0_IntCtl_IPTI=0
|
||||
CP0_PRId=0
|
||||
CP0_PRId_CompanyID=0
|
||||
CP0_PRId_CompanyOptions=0
|
||||
CP0_PRId_ProcessorID=1
|
||||
CP0_PRId_Revision=0
|
||||
CP0_PerfCtr_M=false
|
||||
CP0_PerfCtr_W=false
|
||||
CP0_SrsCtl_HSS=0
|
||||
CP0_WatchHi_M=false
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=MipsTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.itb]
|
||||
type=MipsTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=RubyMemory
|
||||
clock=1
|
||||
config_file=build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic-ruby/ruby.config
|
||||
debug=false
|
||||
debug_file=ruby.debug
|
||||
file=
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
num_cpus=1
|
||||
num_dmas=1
|
||||
phase=0
|
||||
ports_per_core=2
|
||||
range=0:1073741823
|
||||
stats_file=ruby.stats
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
|
|
@ -1,5 +0,0 @@
|
|||
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024", "-C", "32768", "-A", "8", "-D", "1"]
|
||||
print config: 1
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 2 2010 07:01:31
|
||||
M5 revision a538feb8a617 6813 default qtip tip qbase fixhelp.patch
|
||||
M5 started Jan 2 2010 07:03:09
|
||||
M5 executing on fajita
|
||||
command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic-ruby -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic-ruby
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello World!
|
||||
Exiting @ tick 2913500 because target called exit()
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 57498 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 2303472 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_tick_rate 28699061 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5827 # Number of instructions simulated
|
||||
sim_seconds 0.000003 # Number of seconds simulated
|
||||
sim_ticks 2913500 # Number of ticks simulated
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.dtb.read_hits 0 # DTB read hits
|
||||
system.cpu.dtb.read_misses 0 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 5828 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 5827 # Number of instructions executed
|
||||
system.cpu.num_refs 2090 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -5,7 +5,7 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=cpu physmem ruby
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
|
||||
|
|
@ -67,7 +67,7 @@ CP0_PerfCtr_W=false
|
|||
CP0_SrsCtl_HSS=0
|
||||
CP0_WatchHi_M=false
|
||||
checker=Null
|
||||
clock=500
|
||||
clock=1
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
|
|
@ -86,8 +86,8 @@ progress_interval=0
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=MipsTLB
|
||||
|
|
@ -108,7 +108,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
|
||||
executable=tests/test-progs/hello/bin/mips/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -119,32 +119,170 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=RubyMemory
|
||||
clock=1
|
||||
config_file=build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby/ruby.config
|
||||
debug=false
|
||||
debug_file=ruby.debug
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30000
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
num_cpus=1
|
||||
num_dmas=1
|
||||
phase=0
|
||||
ports_per_core=2
|
||||
range=0:1073741823
|
||||
stats_file=ruby.stats
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tech_nm=45
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links1.ext_node.directory
|
||||
directory_latency=12
|
||||
memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
size=134217728
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=0
|
||||
node_b=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=1
|
||||
node_b=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
|
||||
[system.ruby.tracer]
|
||||
type=RubyTracer
|
||||
warmup_length=100000
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,3 @@
|
|||
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024", "-C", "32768", "-A", "8", "-D", "1"]
|
||||
print config: 1
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,13 +5,13 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jan 2 2010 07:01:31
|
||||
M5 revision a538feb8a617 6813 default qtip tip qbase fixhelp.patch
|
||||
M5 started Jan 2 2010 07:03:09
|
||||
M5 executing on fajita
|
||||
command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
M5 compiled Jan 21 2010 11:12:15
|
||||
M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip
|
||||
M5 started Jan 21 2010 11:12:51
|
||||
M5 executing on svvint07
|
||||
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Hello World!
|
||||
Exiting @ tick 23749000 because target called exit()
|
||||
Exiting @ tick 292960 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 6560 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 2303716 # Number of bytes of host memory used
|
||||
host_seconds 0.89 # Real time elapsed on the host
|
||||
host_tick_rate 26729951 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 24278 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 347460 # Number of bytes of host memory used
|
||||
host_seconds 0.24 # Real time elapsed on the host
|
||||
host_tick_rate 1220626 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 5827 # Number of instructions simulated
|
||||
sim_seconds 0.000024 # Number of seconds simulated
|
||||
sim_ticks 23749000 # Number of ticks simulated
|
||||
sim_seconds 0.000293 # Number of seconds simulated
|
||||
sim_ticks 292960 # Number of ticks simulated
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
|
|
@ -28,7 +28,7 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 47498 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 292960 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 5827 # Number of instructions executed
|
||||
system.cpu.num_refs 2090 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,97 +0,0 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.itb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=RubyMemory
|
||||
clock=1
|
||||
config_file=build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic-ruby/ruby.config
|
||||
debug=false
|
||||
debug_file=ruby.debug
|
||||
file=
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
num_cpus=1
|
||||
phase=0
|
||||
range=0:134217727
|
||||
stats_file=ruby.stats
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
|
|
@ -1,382 +0,0 @@
|
|||
|
||||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
RubySystem config:
|
||||
random_seed: 539659
|
||||
randomization: 0
|
||||
tech_nm: 45
|
||||
freq_mhz: 3000
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 1073741824
|
||||
memory_size_bits: 30
|
||||
DMA_Controller config: DMAController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
dma_sequencer: DMASequencer_0
|
||||
number_of_TBEs: 128
|
||||
transitions_per_cycle: 32
|
||||
Directory_Controller config: DirectoryController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
directory_latency: 6
|
||||
directory_name: DirectoryMemory_0
|
||||
memory_controller_name: MemoryControl_0
|
||||
memory_latency: 158
|
||||
number_of_TBEs: 128
|
||||
recycle_latency: 10
|
||||
to_mem_ctrl_latency: 1
|
||||
transitions_per_cycle: 32
|
||||
L1Cache_Controller config: L1CacheController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
cache: l1u_0
|
||||
cache_response_latency: 12
|
||||
issue_latency: 2
|
||||
number_of_TBEs: 128
|
||||
sequencer: Sequencer_0
|
||||
transitions_per_cycle: 32
|
||||
Cache config: l1u_0
|
||||
controller: L1CacheController_0
|
||||
cache_associativity: 8
|
||||
num_cache_sets_bits: 2
|
||||
num_cache_sets: 4
|
||||
cache_set_size_bytes: 256
|
||||
cache_set_size_Kbytes: 0.25
|
||||
cache_set_size_Mbytes: 0.000244141
|
||||
cache_size_bytes: 2048
|
||||
cache_size_Kbytes: 2
|
||||
cache_size_Mbytes: 0.00195312
|
||||
DirectoryMemory Global Config:
|
||||
number of directory memories: 1
|
||||
total memory size bytes: 1073741824
|
||||
total memory size bits: 30
|
||||
DirectoryMemory module config: DirectoryMemory_0
|
||||
controller: DirectoryController_0
|
||||
version: 0
|
||||
memory_bits: 30
|
||||
memory_size_bytes: 1073741824
|
||||
memory_size_Kbytes: 1.04858e+06
|
||||
memory_size_Mbytes: 1024
|
||||
memory_size_Gbytes: 1
|
||||
Seqeuncer config: Sequencer_0
|
||||
controller: L1CacheController_0
|
||||
version: 0
|
||||
max_outstanding_requests: 16
|
||||
deadlock_threshold: 500000
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology: theTopology
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
virtual_net_2: active, ordered
|
||||
virtual_net_3: inactive
|
||||
virtual_net_4: active, ordered
|
||||
virtual_net_5: active, ordered
|
||||
|
||||
--- Begin Topology Print ---
|
||||
|
||||
Topology print ONLY indicates the _NETWORK_ latency between two machines
|
||||
It does NOT include the latency within the machines
|
||||
|
||||
L1Cache-0 Network Latencies
|
||||
L1Cache-0 -> Directory-0 net_lat: 7
|
||||
L1Cache-0 -> DMA-0 net_lat: 7
|
||||
|
||||
Directory-0 Network Latencies
|
||||
Directory-0 -> L1Cache-0 net_lat: 7
|
||||
Directory-0 -> DMA-0 net_lat: 7
|
||||
|
||||
DMA-0 Network Latencies
|
||||
DMA-0 -> L1Cache-0 net_lat: 7
|
||||
DMA-0 -> Directory-0 net_lat: 7
|
||||
|
||||
--- End Topology Print ---
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
periodic_stats_period: 1000000
|
||||
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jul/06/2009 11:11:24
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 0.23
|
||||
Virtual_time_in_minutes: 0.00383333
|
||||
Virtual_time_in_hours: 6.38889e-05
|
||||
Virtual_time_in_days: 6.38889e-05
|
||||
|
||||
Ruby_current_time: 2701001
|
||||
Ruby_start_time: 1
|
||||
Ruby_cycles: 2701000
|
||||
|
||||
mbytes_resident: 144.91
|
||||
mbytes_total: 1330.19
|
||||
resident_ratio: 0.108942
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
instruction_executed: 1 [ 1 ]
|
||||
ruby_cycles_executed: 2701001 [ 2701001 ]
|
||||
cycles_per_instruction: 2.701e+06 [ 2.701e+06 ]
|
||||
misses_per_thousand_instructions: 0 [ 0 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
instructions_per_transaction: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
|
||||
L1D_cache cache stats:
|
||||
L1D_cache_total_misses: 0
|
||||
L1D_cache_total_demand_misses: 0
|
||||
L1D_cache_total_prefetches: 0
|
||||
L1D_cache_total_sw_prefetches: 0
|
||||
L1D_cache_total_hw_prefetches: 0
|
||||
L1D_cache_misses_per_transaction: 0
|
||||
L1D_cache_misses_per_instruction: 0
|
||||
L1D_cache_instructions_per_misses: NaN
|
||||
|
||||
L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
L1I_cache cache stats:
|
||||
L1I_cache_total_misses: 0
|
||||
L1I_cache_total_demand_misses: 0
|
||||
L1I_cache_total_prefetches: 0
|
||||
L1I_cache_total_sw_prefetches: 0
|
||||
L1I_cache_total_hw_prefetches: 0
|
||||
L1I_cache_misses_per_transaction: 0
|
||||
L1I_cache_misses_per_instruction: 0
|
||||
L1I_cache_instructions_per_misses: NaN
|
||||
|
||||
L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
L2_cache cache stats:
|
||||
L2_cache_total_misses: 0
|
||||
L2_cache_total_demand_misses: 0
|
||||
L2_cache_total_prefetches: 0
|
||||
L2_cache_total_sw_prefetches: 0
|
||||
L2_cache_total_hw_prefetches: 0
|
||||
L2_cache_misses_per_transaction: 0
|
||||
L2_cache_misses_per_instruction: 0
|
||||
L2_cache_instructions_per_misses: NaN
|
||||
|
||||
L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
Directory-0:0
|
||||
DMA-0:0
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 37843
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 40
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0
|
||||
links_utilized_percent_switch_0_link_0: 0 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0 bw: 160000 base_latency: 1
|
||||
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0
|
||||
links_utilized_percent_switch_1_link_0: 0 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0 bw: 160000 base_latency: 1
|
||||
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0
|
||||
links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
|
||||
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 0
|
||||
links_utilized_percent_switch_3_link_0: 0 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
|
||||
|
||||
|
||||
--- DMA ---
|
||||
- Event Counts -
|
||||
ReadRequest 0
|
||||
WriteRequest 0
|
||||
Data 0
|
||||
Ack 0
|
||||
|
||||
- Transitions -
|
||||
READY ReadRequest 0 <--
|
||||
READY WriteRequest 0 <--
|
||||
|
||||
BUSY_RD Data 0 <--
|
||||
|
||||
BUSY_WR Ack 0 <--
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
GETX 0
|
||||
GETS 0
|
||||
PUTX 0
|
||||
PUTX_NotOwner 0
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
Memory_Data 0
|
||||
Memory_Ack 0
|
||||
|
||||
- Transitions -
|
||||
I GETX 0 <--
|
||||
I PUTX_NotOwner 0 <--
|
||||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
|
||||
M GETX 0 <--
|
||||
M PUTX 0 <--
|
||||
M PUTX_NotOwner 0 <--
|
||||
M DMA_READ 0 <--
|
||||
M DMA_WRITE 0 <--
|
||||
|
||||
M_DRD GETX 0 <--
|
||||
M_DRD PUTX 0 <--
|
||||
|
||||
M_DWR GETX 0 <--
|
||||
M_DWR PUTX 0 <--
|
||||
|
||||
M_DWRI Memory_Ack 0 <--
|
||||
|
||||
IM GETX 0 <--
|
||||
IM GETS 0 <--
|
||||
IM PUTX 0 <--
|
||||
IM PUTX_NotOwner 0 <--
|
||||
IM DMA_READ 0 <--
|
||||
IM DMA_WRITE 0 <--
|
||||
IM Memory_Data 0 <--
|
||||
|
||||
MI GETX 0 <--
|
||||
MI GETS 0 <--
|
||||
MI PUTX 0 <--
|
||||
MI PUTX_NotOwner 0 <--
|
||||
MI DMA_READ 0 <--
|
||||
MI DMA_WRITE 0 <--
|
||||
MI Memory_Ack 0 <--
|
||||
|
||||
ID GETX 0 <--
|
||||
ID GETS 0 <--
|
||||
ID PUTX 0 <--
|
||||
ID PUTX_NotOwner 0 <--
|
||||
ID DMA_READ 0 <--
|
||||
ID DMA_WRITE 0 <--
|
||||
ID Memory_Data 0 <--
|
||||
|
||||
ID_W GETX 0 <--
|
||||
ID_W GETS 0 <--
|
||||
ID_W PUTX 0 <--
|
||||
ID_W PUTX_NotOwner 0 <--
|
||||
ID_W DMA_READ 0 <--
|
||||
ID_W DMA_WRITE 0 <--
|
||||
ID_W Memory_Ack 0 <--
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load 0
|
||||
Ifetch 0
|
||||
Store 0
|
||||
Data 0
|
||||
Fwd_GETX 0
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 0 <--
|
||||
I Ifetch 0 <--
|
||||
I Store 0 <--
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M Fwd_GETX 0 <--
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
|
||||
IS Data 0 <--
|
||||
|
||||
IM Data 0 <--
|
||||
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
|
||||
print config: 1
|
||||
Creating new MessageBuffer for 0 0
|
||||
Creating new MessageBuffer for 0 1
|
||||
Creating new MessageBuffer for 0 2
|
||||
Creating new MessageBuffer for 0 3
|
||||
Creating new MessageBuffer for 0 4
|
||||
Creating new MessageBuffer for 0 5
|
||||
Creating new MessageBuffer for 1 0
|
||||
Creating new MessageBuffer for 1 1
|
||||
Creating new MessageBuffer for 1 2
|
||||
Creating new MessageBuffer for 1 3
|
||||
Creating new MessageBuffer for 1 4
|
||||
Creating new MessageBuffer for 1 5
|
||||
Creating new MessageBuffer for 2 0
|
||||
Creating new MessageBuffer for 2 1
|
||||
Creating new MessageBuffer for 2 2
|
||||
Creating new MessageBuffer for 2 3
|
||||
Creating new MessageBuffer for 2 4
|
||||
Creating new MessageBuffer for 2 5
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 6 2009 11:07:18
|
||||
M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
|
||||
M5 started Jul 6 2009 11:11:24
|
||||
M5 executing on maize
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic-ruby -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic-ruby
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Debug: Adding to filter: 'q' (Queue)
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello World!Exiting @ tick 2701000 because target called exit()
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 49084 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 201040 # Number of bytes of host memory used
|
||||
host_seconds 0.11 # Real time elapsed on the host
|
||||
host_tick_rate 24773225 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5340 # Number of instructions simulated
|
||||
sim_seconds 0.000003 # Number of seconds simulated
|
||||
sim_ticks 2701000 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 5403 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 5340 # Number of instructions executed
|
||||
system.cpu.num_refs 1402 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -5,7 +5,7 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=cpu physmem ruby
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
|
||||
|
|
@ -13,7 +13,7 @@ physmem=system.physmem
|
|||
type=TimingSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
clock=1
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
|
|
@ -32,8 +32,8 @@ progress_interval=0
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=SparcTLB
|
||||
|
|
@ -54,7 +54,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
|
||||
executable=tests/test-progs/hello/bin/sparc/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -65,30 +65,170 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=RubyMemory
|
||||
clock=1
|
||||
config_file=build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby/ruby.config
|
||||
debug=false
|
||||
debug_file=ruby.debug
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30000
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
num_cpus=1
|
||||
phase=0
|
||||
range=0:134217727
|
||||
stats_file=ruby.stats
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tech_nm=45
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links1.ext_node.directory
|
||||
directory_latency=12
|
||||
memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
size=134217728
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=0
|
||||
node_b=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=1
|
||||
node_b=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
|
||||
[system.ruby.tracer]
|
||||
type=RubyTracer
|
||||
warmup_length=100000
|
||||
|
||||
|
|
|
|||
|
|
@ -2,73 +2,23 @@
|
|||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
RubySystem config:
|
||||
random_seed: 229628
|
||||
random_seed: 1234
|
||||
randomization: 0
|
||||
tech_nm: 45
|
||||
freq_mhz: 3000
|
||||
cycle_period: 1
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 1073741824
|
||||
memory_size_bits: 30
|
||||
DMA_Controller config: DMAController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
dma_sequencer: DMASequencer_0
|
||||
number_of_TBEs: 128
|
||||
transitions_per_cycle: 32
|
||||
Directory_Controller config: DirectoryController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
directory_latency: 6
|
||||
directory_name: DirectoryMemory_0
|
||||
memory_controller_name: MemoryControl_0
|
||||
memory_latency: 158
|
||||
number_of_TBEs: 128
|
||||
recycle_latency: 10
|
||||
to_mem_ctrl_latency: 1
|
||||
transitions_per_cycle: 32
|
||||
L1Cache_Controller config: L1CacheController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
cache: l1u_0
|
||||
cache_response_latency: 12
|
||||
issue_latency: 2
|
||||
number_of_TBEs: 128
|
||||
sequencer: Sequencer_0
|
||||
transitions_per_cycle: 32
|
||||
Cache config: l1u_0
|
||||
controller: L1CacheController_0
|
||||
cache_associativity: 8
|
||||
num_cache_sets_bits: 2
|
||||
num_cache_sets: 4
|
||||
cache_set_size_bytes: 256
|
||||
cache_set_size_Kbytes: 0.25
|
||||
cache_set_size_Mbytes: 0.000244141
|
||||
cache_size_bytes: 2048
|
||||
cache_size_Kbytes: 2
|
||||
cache_size_Mbytes: 0.00195312
|
||||
memory_size_bytes: 134217728
|
||||
memory_size_bits: 27
|
||||
DirectoryMemory Global Config:
|
||||
number of directory memories: 1
|
||||
total memory size bytes: 1073741824
|
||||
total memory size bits: 30
|
||||
DirectoryMemory module config: DirectoryMemory_0
|
||||
controller: DirectoryController_0
|
||||
version: 0
|
||||
memory_bits: 30
|
||||
memory_size_bytes: 1073741824
|
||||
memory_size_Kbytes: 1.04858e+06
|
||||
memory_size_Mbytes: 1024
|
||||
memory_size_Gbytes: 1
|
||||
Seqeuncer config: Sequencer_0
|
||||
controller: L1CacheController_0
|
||||
version: 0
|
||||
max_outstanding_requests: 16
|
||||
deadlock_threshold: 500000
|
||||
total memory size bytes: 134217728
|
||||
total memory size bits: 27
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology: theTopology
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
|
|
@ -76,25 +26,11 @@ virtual_net_2: active, ordered
|
|||
virtual_net_3: inactive
|
||||
virtual_net_4: active, ordered
|
||||
virtual_net_5: active, ordered
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
virtual_net_9: inactive
|
||||
|
||||
--- Begin Topology Print ---
|
||||
|
||||
Topology print ONLY indicates the _NETWORK_ latency between two machines
|
||||
It does NOT include the latency within the machines
|
||||
|
||||
L1Cache-0 Network Latencies
|
||||
L1Cache-0 -> Directory-0 net_lat: 7
|
||||
L1Cache-0 -> DMA-0 net_lat: 7
|
||||
|
||||
Directory-0 Network Latencies
|
||||
Directory-0 -> L1Cache-0 net_lat: 7
|
||||
Directory-0 -> DMA-0 net_lat: 7
|
||||
|
||||
DMA-0 Network Latencies
|
||||
DMA-0 -> L1Cache-0 net_lat: 7
|
||||
DMA-0 -> Directory-0 net_lat: 7
|
||||
|
||||
--- End Topology Print ---
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
|
|
@ -103,7 +39,7 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Jul/06/2009 11:11:36
|
||||
Real time: Jan/21/2010 11:30:49
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
|
|
@ -112,123 +48,52 @@ Elapsed_time_in_minutes: 0.0166667
|
|||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 0.71
|
||||
Virtual_time_in_minutes: 0.0118333
|
||||
Virtual_time_in_hours: 0.000197222
|
||||
Virtual_time_in_days: 0.000197222
|
||||
Virtual_time_in_seconds: 0.28
|
||||
Virtual_time_in_minutes: 0.00466667
|
||||
Virtual_time_in_hours: 7.77778e-05
|
||||
Virtual_time_in_days: 3.24074e-06
|
||||
|
||||
Ruby_current_time: 20314001
|
||||
Ruby_start_time: 1
|
||||
Ruby_cycles: 20314000
|
||||
Ruby_current_time: 253364
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 253364
|
||||
|
||||
mbytes_resident: 145.32
|
||||
mbytes_total: 1330.48
|
||||
resident_ratio: 0.109227
|
||||
mbytes_resident: 34.3555
|
||||
mbytes_total: 34.5312
|
||||
resident_ratio: 0.995136
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
instruction_executed: 1 [ 1 ]
|
||||
ruby_cycles_executed: 20314001 [ 20314001 ]
|
||||
cycles_per_instruction: 2.0314e+07 [ 2.0314e+07 ]
|
||||
misses_per_thousand_instructions: 0 [ 0 ]
|
||||
ruby_cycles_executed: 253365 [ 253365 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
instructions_per_transaction: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
|
||||
L1D_cache cache stats:
|
||||
L1D_cache_total_misses: 0
|
||||
L1D_cache_total_demand_misses: 0
|
||||
L1D_cache_total_prefetches: 0
|
||||
L1D_cache_total_sw_prefetches: 0
|
||||
L1D_cache_total_hw_prefetches: 0
|
||||
L1D_cache_misses_per_transaction: 0
|
||||
L1D_cache_misses_per_instruction: 0
|
||||
L1D_cache_instructions_per_misses: NaN
|
||||
|
||||
L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
L1I_cache cache stats:
|
||||
L1I_cache_total_misses: 0
|
||||
L1I_cache_total_demand_misses: 0
|
||||
L1I_cache_total_prefetches: 0
|
||||
L1I_cache_total_sw_prefetches: 0
|
||||
L1I_cache_total_hw_prefetches: 0
|
||||
L1I_cache_misses_per_transaction: 0
|
||||
L1I_cache_misses_per_instruction: 0
|
||||
L1I_cache_instructions_per_misses: NaN
|
||||
|
||||
L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
L2_cache cache stats:
|
||||
L2_cache_total_misses: 0
|
||||
L2_cache_total_demand_misses: 0
|
||||
L2_cache_total_prefetches: 0
|
||||
L2_cache_total_sw_prefetches: 0
|
||||
L2_cache_total_hw_prefetches: 0
|
||||
L2_cache_misses_per_transaction: 0
|
||||
L2_cache_misses_per_instruction: 0
|
||||
L2_cache_instructions_per_misses: NaN
|
||||
|
||||
L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
|
||||
Memory control:
|
||||
memory_total_requests: 1262
|
||||
memory_reads: 647
|
||||
memory_writes: 615
|
||||
memory_refreshes: 12114
|
||||
memory_total_request_delays: 1568
|
||||
memory_delays_per_request: 1.24247
|
||||
memory_delays_in_input_queue: 615
|
||||
memory_delays_behind_head_of_bank_queue: 1
|
||||
memory_delays_stalled_at_head_of_bank_queue: 952
|
||||
memory_stalls_for_bank_busy: 261
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 39
|
||||
memory_stalls_for_bus: 627
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 25
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 90 30 28 38 62 36 45 47 17 28 13 18 28 22 6 14 12 27 39 28 18 42 13 12 41 72 76 92 62 79 86 41
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
Directory-0:0
|
||||
DMA-0:0
|
||||
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
L2TBE_usage: [binsize: 1 max: 1 count: 1262 average: 0.487322 | standard deviation: 0.500594 | 647 615 ]
|
||||
StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 6772 average: 1 | standard deviation: 0 | 0 6772 ]
|
||||
store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 6773 average: 1 | standard deviation: 0 | 0 6773 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 270 count: 6772 average: 18.3048 | standard deviation: 50.462 | 0 6125 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 0 0 0 13 0 0 0 0 558 0 0 0 0 5 0 0 0 0 17 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_1: [binsize: 2 max: 270 count: 5383 average: 13.4873 | standard deviation: 43.0215 | 0 5021 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 0 0 0 0 3 0 0 0 0 316 0 0 0 0 4 0 0 0 0 10 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 2 max: 260 count: 716 average: 41.8128 | standard deviation: 72.7521 | 0 549 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 7 0 0 0 0 141 0 0 0 0 1 0 0 0 0 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 2 max: 260 count: 673 average: 31.8276 | standard deviation: 65.1506 | 0 555 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 3 0 0 0 0 101 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency: [binsize: 2 max: 371 count: 6772 average: 36.4135 | standard deviation: 69.5949 | 0 5483 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 4 2 2 10 2 309 224 133 323 144 9 3 1 0 0 11 11 1 16 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 25 14 6 15 3 1 1 1 0 0 1 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
miss_latency_1: [binsize: 2 max: 285 count: 5383 average: 26.3539 | standard deviation: 60.2129 | 0 4668 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 5 2 172 118 76 168 91 3 1 1 0 0 8 9 0 10 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 18 3 4 10 1 0 0 1 0 0 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 2 max: 285 count: 716 average: 98.7235 | standard deviation: 87.4535 | 0 321 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 1 2 3 0 110 62 31 116 36 4 1 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 2 3 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 2 max: 371 count: 673 average: 50.584 | standard deviation: 80.4924 | 0 494 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 27 44 26 39 17 2 1 0 0 0 2 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
|
@ -237,104 +102,156 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
|
|||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 1262 average: 0 | standard deviation: 0 | 1262 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1262 average: 0 | standard deviation: 0 | 1262 ]
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 2574 average: 0 | standard deviation: 0 | 2574 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 2574 average: 0 | standard deviation: 0 | 2574 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 647 average: 0 | standard deviation: 0 | 647 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 615 average: 0 | standard deviation: 0 | 615 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1289 average: 0 | standard deviation: 0 | 1289 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1285 average: 0 | standard deviation: 0 | 1285 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 37948
|
||||
page_faults: 0
|
||||
page_reclaims: 7494
|
||||
page_faults: 2200
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 48
|
||||
block_outputs: 0
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.00019414
|
||||
links_utilized_percent_switch_0_link_0: 7.76558e-05 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.000310623 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.158621
|
||||
links_utilized_percent_switch_0_link_0: 0.0635745 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.253667 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 647 5176 [ 0 647 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 615 4920 [ 0 0 615 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 647 5176 [ 647 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 615 4920 [ 615 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.00019414
|
||||
links_utilized_percent_switch_1_link_0: 7.76558e-05 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.000310623 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 0.158857
|
||||
links_utilized_percent_switch_1_link_0: 0.0634167 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.254298 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 647 5176 [ 647 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 615 4920 [ 615 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 647 5176 [ 0 647 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 615 4920 [ 0 0 615 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0
|
||||
links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.253982
|
||||
links_utilized_percent_switch_2_link_0: 0.254298 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.253667 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 1289 92808 [ 0 1289 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 1285 10280 [ 0 0 1285 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 1289 10312 [ 1289 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 1285 92520 [ 1285 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 0.000207082
|
||||
links_utilized_percent_switch_3_link_0: 0.000310623 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.000310623 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1289
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1289
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
|
||||
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 647 5176 [ 0 647 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 615 4920 [ 0 0 615 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 647 5176 [ 647 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Data: 615 4920 [ 615 0 0 0 0 0 ] base_latency: 1
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 30.6439%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 13.8867%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 55.4694%
|
||||
|
||||
--- DMA ---
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 1289 100%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1289 average: 5.1249 | standard deviation: 2.01759 | 0 50 2 0 836 0 0 0 401 ]
|
||||
|
||||
--- L1Cache 0 ---
|
||||
- Event Counts -
|
||||
ReadRequest 0
|
||||
WriteRequest 0
|
||||
Data 0
|
||||
Ack 0
|
||||
Load 716
|
||||
Ifetch 5383
|
||||
Store 673
|
||||
Data 1289
|
||||
Fwd_GETX 0
|
||||
Inv 0
|
||||
Replacement 1285
|
||||
Writeback_Ack 1285
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
READY ReadRequest 0 <--
|
||||
READY WriteRequest 0 <--
|
||||
I Load 395
|
||||
I Ifetch 715
|
||||
I Store 179
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
BUSY_RD Data 0 <--
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
BUSY_WR Ack 0 <--
|
||||
M Load 321
|
||||
M Ifetch 4668
|
||||
M Store 494
|
||||
M Fwd_GETX 0 <--
|
||||
M Inv 0 <--
|
||||
M Replacement 1285
|
||||
|
||||
--- Directory ---
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 1285
|
||||
|
||||
IS Data 1110
|
||||
|
||||
IM Data 179
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
|
||||
memory_total_requests: 2574
|
||||
memory_reads: 1289
|
||||
memory_writes: 1285
|
||||
memory_refreshes: 528
|
||||
memory_total_request_delays: 3552
|
||||
memory_delays_per_request: 1.37995
|
||||
memory_delays_in_input_queue: 1284
|
||||
memory_delays_behind_head_of_bank_queue: 3
|
||||
memory_delays_stalled_at_head_of_bank_queue: 2265
|
||||
memory_stalls_for_bank_busy: 847
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 88
|
||||
memory_stalls_for_bus: 1292
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 38
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 166 40 36 48 109 42 63 241 50 34 16 26 60 64 38 46 30 88 202 144 40 58 22 20 60 120 136 125 84 134 166 66
|
||||
|
||||
--- Directory 0 ---
|
||||
- Event Counts -
|
||||
GETX 647
|
||||
GETX 1289
|
||||
GETS 0
|
||||
PUTX 615
|
||||
PUTX 1285
|
||||
PUTX_NotOwner 0
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
Memory_Data 647
|
||||
Memory_Ack 615
|
||||
Memory_Data 1289
|
||||
Memory_Ack 1285
|
||||
|
||||
- Transitions -
|
||||
I GETX 647
|
||||
I GETX 1289
|
||||
I PUTX_NotOwner 0 <--
|
||||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
|
||||
M GETX 0 <--
|
||||
M PUTX 615
|
||||
M PUTX 1285
|
||||
M PUTX_NotOwner 0 <--
|
||||
M DMA_READ 0 <--
|
||||
M DMA_WRITE 0 <--
|
||||
|
|
@ -345,15 +262,19 @@ M_DRD PUTX 0 <--
|
|||
M_DWR GETX 0 <--
|
||||
M_DWR PUTX 0 <--
|
||||
|
||||
M_DWRI GETX 0 <--
|
||||
M_DWRI Memory_Ack 0 <--
|
||||
|
||||
M_DRDI GETX 0 <--
|
||||
M_DRDI Memory_Ack 0 <--
|
||||
|
||||
IM GETX 0 <--
|
||||
IM GETS 0 <--
|
||||
IM PUTX 0 <--
|
||||
IM PUTX_NotOwner 0 <--
|
||||
IM DMA_READ 0 <--
|
||||
IM DMA_WRITE 0 <--
|
||||
IM Memory_Data 647
|
||||
IM Memory_Data 1289
|
||||
|
||||
MI GETX 0 <--
|
||||
MI GETS 0 <--
|
||||
|
|
@ -361,7 +282,7 @@ MI PUTX 0 <--
|
|||
MI PUTX_NotOwner 0 <--
|
||||
MI DMA_READ 0 <--
|
||||
MI DMA_WRITE 0 <--
|
||||
MI Memory_Ack 615
|
||||
MI Memory_Ack 1285
|
||||
|
||||
ID GETX 0 <--
|
||||
ID GETS 0 <--
|
||||
|
|
@ -379,39 +300,3 @@ ID_W DMA_READ 0 <--
|
|||
ID_W DMA_WRITE 0 <--
|
||||
ID_W Memory_Ack 0 <--
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load 716
|
||||
Ifetch 5383
|
||||
Store 673
|
||||
Data 647
|
||||
Fwd_GETX 0
|
||||
Inv 0
|
||||
Replacement 615
|
||||
Writeback_Ack 615
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 167
|
||||
I Ifetch 362
|
||||
I Store 118
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 549
|
||||
M Ifetch 5021
|
||||
M Store 555
|
||||
M Fwd_GETX 0 <--
|
||||
M Inv 0 <--
|
||||
M Replacement 615
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 615
|
||||
|
||||
IS Data 529
|
||||
|
||||
IM Data 118
|
||||
|
||||
|
|
|
|||
|
|
@ -1,23 +1,3 @@
|
|||
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
|
||||
print config: 1
|
||||
Creating new MessageBuffer for 0 0
|
||||
Creating new MessageBuffer for 0 1
|
||||
Creating new MessageBuffer for 0 2
|
||||
Creating new MessageBuffer for 0 3
|
||||
Creating new MessageBuffer for 0 4
|
||||
Creating new MessageBuffer for 0 5
|
||||
Creating new MessageBuffer for 1 0
|
||||
Creating new MessageBuffer for 1 1
|
||||
Creating new MessageBuffer for 1 2
|
||||
Creating new MessageBuffer for 1 3
|
||||
Creating new MessageBuffer for 1 4
|
||||
Creating new MessageBuffer for 1 5
|
||||
Creating new MessageBuffer for 2 0
|
||||
Creating new MessageBuffer for 2 1
|
||||
Creating new MessageBuffer for 2 2
|
||||
Creating new MessageBuffer for 2 3
|
||||
Creating new MessageBuffer for 2 4
|
||||
Creating new MessageBuffer for 2 5
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,12 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 6 2009 11:07:18
|
||||
M5 revision d3635cac686a 6289 default ruby_refs.diff qtip tip
|
||||
M5 started Jul 6 2009 11:11:35
|
||||
M5 executing on maize
|
||||
M5 compiled Jan 21 2010 11:29:25
|
||||
M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip
|
||||
M5 started Jan 21 2010 11:30:48
|
||||
M5 executing on svvint07
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Debug: Adding to filter: 'q' (Queue)
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello World!Exiting @ tick 20314000 because target called exit()
|
||||
Hello World!Exiting @ tick 253364 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,16 +1,16 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 3344 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 1362412 # Number of bytes of host memory used
|
||||
host_seconds 1.60 # Real time elapsed on the host
|
||||
host_tick_rate 12720005 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 59331 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 347024 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_tick_rate 2815062 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 5340 # Number of instructions simulated
|
||||
sim_seconds 0.000020 # Number of seconds simulated
|
||||
sim_ticks 20314000 # Number of ticks simulated
|
||||
sim_seconds 0.000253 # Number of seconds simulated
|
||||
sim_ticks 253364 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 40628 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 253364 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 5340 # Number of instructions executed
|
||||
system.cpu.num_refs 1402 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,97 +0,0 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
itb=system.cpu.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
width=1
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
size=64
|
||||
|
||||
[system.cpu.itb]
|
||||
type=X86TLB
|
||||
size=64
|
||||
|
||||
[system.cpu.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=hello
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=RubyMemory
|
||||
clock=1
|
||||
config_file=build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic-ruby/ruby.config
|
||||
debug=false
|
||||
debug_file=ruby.debug
|
||||
file=
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
num_cpus=1
|
||||
phase=0
|
||||
range=0:134217727
|
||||
stats_file=ruby.stats
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
|
|
@ -1,344 +0,0 @@
|
|||
|
||||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
RubySystem config:
|
||||
random_seed: 1234
|
||||
randomization: 0
|
||||
tech_nm: 45
|
||||
freq_mhz: 3000
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 1073741824
|
||||
memory_size_bits: 30
|
||||
DMA_Controller config: DMAController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
dma_sequencer: DMASequencer_0
|
||||
number_of_TBEs: 256
|
||||
recycle_latency: 10
|
||||
request_latency: 6
|
||||
transitions_per_cycle: 32
|
||||
Directory_Controller config: DirectoryController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
directory_latency: 6
|
||||
directory_name: DirectoryMemory_0
|
||||
dma_select_low_bit: 6
|
||||
dma_select_num_bits: 0
|
||||
memory_controller_name: MemoryControl_0
|
||||
number_of_TBEs: 256
|
||||
recycle_latency: 10
|
||||
transitions_per_cycle: 32
|
||||
L1Cache_Controller config: L1CacheController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
cache: l1u_0
|
||||
cache_response_latency: 12
|
||||
issue_latency: 2
|
||||
number_of_TBEs: 256
|
||||
recycle_latency: 10
|
||||
sequencer: Sequencer_0
|
||||
transitions_per_cycle: 32
|
||||
Cache config: l1u_0
|
||||
controller: L1CacheController_0
|
||||
cache_associativity: 8
|
||||
num_cache_sets_bits: 2
|
||||
num_cache_sets: 4
|
||||
cache_set_size_bytes: 256
|
||||
cache_set_size_Kbytes: 0.25
|
||||
cache_set_size_Mbytes: 0.000244141
|
||||
cache_size_bytes: 2048
|
||||
cache_size_Kbytes: 2
|
||||
cache_size_Mbytes: 0.00195312
|
||||
DirectoryMemory Global Config:
|
||||
number of directory memories: 1
|
||||
total memory size bytes: 1073741824
|
||||
total memory size bits: 30
|
||||
DirectoryMemory module config: DirectoryMemory_0
|
||||
controller: DirectoryController_0
|
||||
version: 0
|
||||
memory_bits: 30
|
||||
memory_size_bytes: 1073741824
|
||||
memory_size_Kbytes: 1.04858e+06
|
||||
memory_size_Mbytes: 1024
|
||||
memory_size_Gbytes: 1
|
||||
Seqeuncer config: Sequencer_0
|
||||
controller: L1CacheController_0
|
||||
version: 0
|
||||
max_outstanding_requests: 16
|
||||
deadlock_threshold: 500000
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology: theTopology
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
virtual_net_2: active, ordered
|
||||
virtual_net_3: inactive
|
||||
virtual_net_4: active, ordered
|
||||
virtual_net_5: active, ordered
|
||||
|
||||
--- Begin Topology Print ---
|
||||
|
||||
Topology print ONLY indicates the _NETWORK_ latency between two machines
|
||||
It does NOT include the latency within the machines
|
||||
|
||||
L1Cache-0 Network Latencies
|
||||
L1Cache-0 -> Directory-0 net_lat: 7
|
||||
L1Cache-0 -> DMA-0 net_lat: 7
|
||||
|
||||
Directory-0 Network Latencies
|
||||
Directory-0 -> L1Cache-0 net_lat: 7
|
||||
Directory-0 -> DMA-0 net_lat: 7
|
||||
|
||||
DMA-0 Network Latencies
|
||||
DMA-0 -> L1Cache-0 net_lat: 7
|
||||
DMA-0 -> Directory-0 net_lat: 7
|
||||
|
||||
--- End Topology Print ---
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
periodic_stats_period: 1000000
|
||||
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Aug/09/2009 03:58:51
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 1
|
||||
Elapsed_time_in_minutes: 0.0166667
|
||||
Elapsed_time_in_hours: 0.000277778
|
||||
Elapsed_time_in_days: 1.15741e-05
|
||||
|
||||
Virtual_time_in_seconds: 0.34
|
||||
Virtual_time_in_minutes: 0.00566667
|
||||
Virtual_time_in_hours: 9.44444e-05
|
||||
Virtual_time_in_days: 3.93519e-06
|
||||
|
||||
Ruby_current_time: 5504001
|
||||
Ruby_start_time: 1
|
||||
Ruby_cycles: 5504000
|
||||
|
||||
mbytes_resident: 144.359
|
||||
mbytes_total: 1352.23
|
||||
resident_ratio: 0.106763
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
ruby_cycles_executed: 5504001 [ 5504001 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
cycles_per_transaction: 0 [ 0 ]
|
||||
misses_per_transaction: 0 [ 0 ]
|
||||
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
Directory-0:0
|
||||
DMA-0:0
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 38267
|
||||
page_faults: 1
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0
|
||||
links_utilized_percent_switch_0_link_0: 0 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0 bw: 160000 base_latency: 1
|
||||
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0
|
||||
links_utilized_percent_switch_1_link_0: 0 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0 bw: 160000 base_latency: 1
|
||||
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0
|
||||
links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
|
||||
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 0
|
||||
links_utilized_percent_switch_3_link_0: 0 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
|
||||
|
||||
|
||||
l1u_0 cache stats:
|
||||
l1u_0_total_misses: 0
|
||||
l1u_0_total_demand_misses: 0
|
||||
l1u_0_total_prefetches: 0
|
||||
l1u_0_total_sw_prefetches: 0
|
||||
l1u_0_total_hw_prefetches: 0
|
||||
l1u_0_misses_per_transaction: nan
|
||||
|
||||
l1u_0_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
--- DMA 0 ---
|
||||
- Event Counts -
|
||||
ReadRequest 0
|
||||
WriteRequest 0
|
||||
Data 0
|
||||
Ack 0
|
||||
|
||||
- Transitions -
|
||||
READY ReadRequest 0 <--
|
||||
READY WriteRequest 0 <--
|
||||
|
||||
BUSY_RD Data 0 <--
|
||||
|
||||
BUSY_WR Ack 0 <--
|
||||
|
||||
--- Directory 0 ---
|
||||
- Event Counts -
|
||||
GETX 0
|
||||
GETS 0
|
||||
PUTX 0
|
||||
PUTX_NotOwner 0
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
Memory_Data 0
|
||||
Memory_Ack 0
|
||||
|
||||
- Transitions -
|
||||
I GETX 0 <--
|
||||
I PUTX_NotOwner 0 <--
|
||||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
|
||||
M GETX 0 <--
|
||||
M PUTX 0 <--
|
||||
M PUTX_NotOwner 0 <--
|
||||
M DMA_READ 0 <--
|
||||
M DMA_WRITE 0 <--
|
||||
|
||||
M_DRD GETX 0 <--
|
||||
M_DRD PUTX 0 <--
|
||||
|
||||
M_DWR GETX 0 <--
|
||||
M_DWR PUTX 0 <--
|
||||
|
||||
M_DWRI Memory_Ack 0 <--
|
||||
|
||||
IM GETX 0 <--
|
||||
IM GETS 0 <--
|
||||
IM PUTX 0 <--
|
||||
IM PUTX_NotOwner 0 <--
|
||||
IM DMA_READ 0 <--
|
||||
IM DMA_WRITE 0 <--
|
||||
IM Memory_Data 0 <--
|
||||
|
||||
MI GETX 0 <--
|
||||
MI GETS 0 <--
|
||||
MI PUTX 0 <--
|
||||
MI PUTX_NotOwner 0 <--
|
||||
MI DMA_READ 0 <--
|
||||
MI DMA_WRITE 0 <--
|
||||
MI Memory_Ack 0 <--
|
||||
|
||||
ID GETX 0 <--
|
||||
ID GETS 0 <--
|
||||
ID PUTX 0 <--
|
||||
ID PUTX_NotOwner 0 <--
|
||||
ID DMA_READ 0 <--
|
||||
ID DMA_WRITE 0 <--
|
||||
ID Memory_Data 0 <--
|
||||
|
||||
ID_W GETX 0 <--
|
||||
ID_W GETS 0 <--
|
||||
ID_W PUTX 0 <--
|
||||
ID_W PUTX_NotOwner 0 <--
|
||||
ID_W DMA_READ 0 <--
|
||||
ID_W DMA_WRITE 0 <--
|
||||
ID_W Memory_Ack 0 <--
|
||||
|
||||
--- L1Cache 0 ---
|
||||
- Event Counts -
|
||||
Load 0
|
||||
Ifetch 0
|
||||
Store 0
|
||||
Data 0
|
||||
Fwd_GETX 0
|
||||
Inv 0
|
||||
Replacement 0
|
||||
Writeback_Ack 0
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 0 <--
|
||||
I Ifetch 0 <--
|
||||
I Store 0 <--
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M Fwd_GETX 0 <--
|
||||
M Inv 0 <--
|
||||
M Replacement 0 <--
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 0 <--
|
||||
|
||||
IS Data 0 <--
|
||||
|
||||
IM Data 0 <--
|
||||
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
|
||||
Error: User specified set of debug components, but the RUBY_DEBUG compile-time flag is false.
|
||||
Solution: Re-compile with RUBY_DEBUG set to true.
|
||||
print config: 1
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
warn: instruction 'fldcw_Mw' unimplemented
|
||||
For more information see: http://www.m5sim.org/warn/437d5238
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
M5 Simulator System
|
||||
|
||||
Copyright (c) 2001-2008
|
||||
The Regents of The University of Michigan
|
||||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 9 2009 03:58:47
|
||||
M5 revision 33faa9915d16 6486 default tip
|
||||
M5 started Aug 9 2009 03:58:49
|
||||
M5 executing on tater
|
||||
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic-ruby
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello world!
|
||||
Exiting @ tick 5504000 because target called exit()
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 7886 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 1384684 # Number of bytes of host memory used
|
||||
host_seconds 1.21 # Real time elapsed on the host
|
||||
host_tick_rate 4559114 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 9519 # Number of instructions simulated
|
||||
sim_seconds 0.000006 # Number of seconds simulated
|
||||
sim_ticks 5504000 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 11009 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 9519 # Number of instructions executed
|
||||
system.cpu.num_refs 1987 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
@ -5,7 +5,7 @@ dummy=0
|
|||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu membus physmem
|
||||
children=cpu physmem ruby
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
|
||||
|
|
@ -13,7 +13,7 @@ physmem=system.physmem
|
|||
type=TimingSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
clock=1
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
|
|
@ -32,8 +32,8 @@ progress_interval=0
|
|||
system=system
|
||||
tracer=system.cpu.tracer
|
||||
workload=system.cpu.workload
|
||||
dcache_port=system.membus.port[2]
|
||||
icache_port=system.membus.port[1]
|
||||
dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1]
|
||||
icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0]
|
||||
|
||||
[system.cpu.dtb]
|
||||
type=X86TLB
|
||||
|
|
@ -54,7 +54,7 @@ egid=100
|
|||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
|
||||
executable=tests/test-progs/hello/bin/x86/linux/hello
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
|
|
@ -65,30 +65,170 @@ simpoint=0
|
|||
system=system
|
||||
uid=100
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.physmem]
|
||||
type=RubyMemory
|
||||
clock=1
|
||||
config_file=build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby/ruby.config
|
||||
debug=false
|
||||
debug_file=ruby.debug
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=30000
|
||||
latency=30
|
||||
latency_var=0
|
||||
null=false
|
||||
num_cpus=1
|
||||
phase=0
|
||||
range=0:134217727
|
||||
stats_file=ruby.stats
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort
|
||||
|
||||
[system.ruby]
|
||||
type=RubySystem
|
||||
children=debug network profiler tracer
|
||||
block_size_bytes=64
|
||||
clock=1
|
||||
debug=system.ruby.debug
|
||||
mem_size=134217728
|
||||
network=system.ruby.network
|
||||
profiler=system.ruby.profiler
|
||||
random_seed=1234
|
||||
randomization=false
|
||||
stats_filename=ruby.stats
|
||||
tech_nm=45
|
||||
tracer=system.ruby.tracer
|
||||
|
||||
[system.ruby.debug]
|
||||
type=RubyDebug
|
||||
filter_string=none
|
||||
output_filename=none
|
||||
protocol_trace=false
|
||||
start_time=1
|
||||
verbosity_string=none
|
||||
|
||||
[system.ruby.network]
|
||||
type=SimpleNetwork
|
||||
children=topology
|
||||
adaptive_routing=true
|
||||
buffer_size=0
|
||||
control_msg_size=8
|
||||
endpoint_bandwidth=10000
|
||||
link_latency=1
|
||||
number_of_virtual_networks=10
|
||||
topology=system.ruby.network.topology
|
||||
|
||||
[system.ruby.network.topology]
|
||||
type=Topology
|
||||
children=ext_links0 ext_links1 int_links0 int_links1
|
||||
ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1
|
||||
int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1
|
||||
num_int_nodes=3
|
||||
print_config=false
|
||||
|
||||
[system.ruby.network.topology.ext_links0]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links0.ext_node
|
||||
int_node=0
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node]
|
||||
type=L1Cache_Controller
|
||||
children=sequencer
|
||||
buffer_size=0
|
||||
cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
cache_response_latency=12
|
||||
issue_latency=2
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer]
|
||||
type=RubySequencer
|
||||
children=icache
|
||||
dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
deadlock_threshold=500000
|
||||
icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
max_outstanding_requests=16
|
||||
physmem=system.physmem
|
||||
using_ruby_tester=false
|
||||
version=0
|
||||
physMemPort=system.physmem.port[0]
|
||||
port=system.cpu.icache_port system.cpu.dcache_port
|
||||
|
||||
[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache]
|
||||
type=RubyCache
|
||||
assoc=2
|
||||
latency=3
|
||||
replacement_policy=PSEUDO_LRU
|
||||
size=256
|
||||
|
||||
[system.ruby.network.topology.ext_links1]
|
||||
type=ExtLink
|
||||
children=ext_node
|
||||
bw_multiplier=64
|
||||
ext_node=system.ruby.network.topology.ext_links1.ext_node
|
||||
int_node=1
|
||||
latency=1
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node]
|
||||
type=Directory_Controller
|
||||
children=directory memBuffer
|
||||
buffer_size=0
|
||||
directory=system.ruby.network.topology.ext_links1.ext_node.directory
|
||||
directory_latency=12
|
||||
memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer
|
||||
number_of_TBEs=256
|
||||
recycle_latency=10
|
||||
transitions_per_cycle=32
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.directory]
|
||||
type=RubyDirectoryMemory
|
||||
size=134217728
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.ext_links1.ext_node.memBuffer]
|
||||
type=RubyMemoryControl
|
||||
bank_bit_0=8
|
||||
bank_busy_time=11
|
||||
bank_queue_size=12
|
||||
banks_per_rank=8
|
||||
basic_bus_busy_time=2
|
||||
dimm_bit_0=12
|
||||
dimms_per_channel=2
|
||||
mem_bus_cycle_multiplier=10
|
||||
mem_ctl_latency=12
|
||||
mem_fixed_delay=0
|
||||
mem_random_arbitrate=0
|
||||
rank_bit_0=11
|
||||
rank_rank_delay=1
|
||||
ranks_per_dimm=2
|
||||
read_write_delay=2
|
||||
refresh_period=1560
|
||||
tFaw=0
|
||||
version=0
|
||||
|
||||
[system.ruby.network.topology.int_links0]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=0
|
||||
node_b=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.network.topology.int_links1]
|
||||
type=IntLink
|
||||
bw_multiplier=16
|
||||
latency=1
|
||||
node_a=1
|
||||
node_b=2
|
||||
weight=1
|
||||
|
||||
[system.ruby.profiler]
|
||||
type=RubyProfiler
|
||||
all_instructions=false
|
||||
hot_lines=false
|
||||
num_of_sequencers=1
|
||||
|
||||
[system.ruby.tracer]
|
||||
type=RubyTracer
|
||||
warmup_length=100000
|
||||
|
||||
|
|
|
|||
|
|
@ -5,73 +5,20 @@ RubySystem config:
|
|||
random_seed: 1234
|
||||
randomization: 0
|
||||
tech_nm: 45
|
||||
freq_mhz: 3000
|
||||
cycle_period: 1
|
||||
block_size_bytes: 64
|
||||
block_size_bits: 6
|
||||
memory_size_bytes: 1073741824
|
||||
memory_size_bits: 30
|
||||
DMA_Controller config: DMAController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
dma_sequencer: DMASequencer_0
|
||||
number_of_TBEs: 256
|
||||
recycle_latency: 10
|
||||
request_latency: 6
|
||||
transitions_per_cycle: 32
|
||||
Directory_Controller config: DirectoryController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
directory_latency: 6
|
||||
directory_name: DirectoryMemory_0
|
||||
dma_select_low_bit: 6
|
||||
dma_select_num_bits: 0
|
||||
memory_controller_name: MemoryControl_0
|
||||
number_of_TBEs: 256
|
||||
recycle_latency: 10
|
||||
transitions_per_cycle: 32
|
||||
L1Cache_Controller config: L1CacheController_0
|
||||
version: 0
|
||||
buffer_size: 32
|
||||
cache: l1u_0
|
||||
cache_response_latency: 12
|
||||
issue_latency: 2
|
||||
number_of_TBEs: 256
|
||||
recycle_latency: 10
|
||||
sequencer: Sequencer_0
|
||||
transitions_per_cycle: 32
|
||||
Cache config: l1u_0
|
||||
controller: L1CacheController_0
|
||||
cache_associativity: 8
|
||||
num_cache_sets_bits: 2
|
||||
num_cache_sets: 4
|
||||
cache_set_size_bytes: 256
|
||||
cache_set_size_Kbytes: 0.25
|
||||
cache_set_size_Mbytes: 0.000244141
|
||||
cache_size_bytes: 2048
|
||||
cache_size_Kbytes: 2
|
||||
cache_size_Mbytes: 0.00195312
|
||||
memory_size_bytes: 134217728
|
||||
memory_size_bits: 27
|
||||
DirectoryMemory Global Config:
|
||||
number of directory memories: 1
|
||||
total memory size bytes: 1073741824
|
||||
total memory size bits: 30
|
||||
DirectoryMemory module config: DirectoryMemory_0
|
||||
controller: DirectoryController_0
|
||||
version: 0
|
||||
memory_bits: 30
|
||||
memory_size_bytes: 1073741824
|
||||
memory_size_Kbytes: 1.04858e+06
|
||||
memory_size_Mbytes: 1024
|
||||
memory_size_Gbytes: 1
|
||||
Seqeuncer config: Sequencer_0
|
||||
controller: L1CacheController_0
|
||||
version: 0
|
||||
max_outstanding_requests: 16
|
||||
deadlock_threshold: 500000
|
||||
total memory size bytes: 134217728
|
||||
total memory size bits: 27
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology: theTopology
|
||||
topology:
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, ordered
|
||||
|
|
@ -79,25 +26,11 @@ virtual_net_2: active, ordered
|
|||
virtual_net_3: inactive
|
||||
virtual_net_4: active, ordered
|
||||
virtual_net_5: active, ordered
|
||||
virtual_net_6: inactive
|
||||
virtual_net_7: inactive
|
||||
virtual_net_8: inactive
|
||||
virtual_net_9: inactive
|
||||
|
||||
--- Begin Topology Print ---
|
||||
|
||||
Topology print ONLY indicates the _NETWORK_ latency between two machines
|
||||
It does NOT include the latency within the machines
|
||||
|
||||
L1Cache-0 Network Latencies
|
||||
L1Cache-0 -> Directory-0 net_lat: 7
|
||||
L1Cache-0 -> DMA-0 net_lat: 7
|
||||
|
||||
Directory-0 Network Latencies
|
||||
Directory-0 -> L1Cache-0 net_lat: 7
|
||||
Directory-0 -> DMA-0 net_lat: 7
|
||||
|
||||
DMA-0 Network Latencies
|
||||
DMA-0 -> L1Cache-0 net_lat: 7
|
||||
DMA-0 -> Directory-0 net_lat: 7
|
||||
|
||||
--- End Topology Print ---
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
|
|
@ -106,34 +39,34 @@ periodic_stats_period: 1000000
|
|||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: Aug/09/2009 04:00:22
|
||||
Real time: Jan/21/2010 12:14:46
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 4
|
||||
Elapsed_time_in_minutes: 0.0666667
|
||||
Elapsed_time_in_hours: 0.00111111
|
||||
Elapsed_time_in_days: 4.62963e-05
|
||||
Elapsed_time_in_seconds: 0
|
||||
Elapsed_time_in_minutes: 0
|
||||
Elapsed_time_in_hours: 0
|
||||
Elapsed_time_in_days: 0
|
||||
|
||||
Virtual_time_in_seconds: 1.19
|
||||
Virtual_time_in_minutes: 0.0198333
|
||||
Virtual_time_in_hours: 0.000330556
|
||||
Virtual_time_in_days: 1.37731e-05
|
||||
Virtual_time_in_seconds: 0.32
|
||||
Virtual_time_in_minutes: 0.00533333
|
||||
Virtual_time_in_hours: 8.88889e-05
|
||||
Virtual_time_in_days: 3.7037e-06
|
||||
|
||||
Ruby_current_time: 26617001
|
||||
Ruby_start_time: 1
|
||||
Ruby_cycles: 26617000
|
||||
Ruby_current_time: 287334
|
||||
Ruby_start_time: 0
|
||||
Ruby_cycles: 287334
|
||||
|
||||
mbytes_resident: 144.777
|
||||
mbytes_total: 1352.41
|
||||
resident_ratio: 0.107057
|
||||
mbytes_resident: 34.1406
|
||||
mbytes_total: 34.3242
|
||||
resident_ratio: 0.994879
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 ]
|
||||
user_misses: 0 [ 0 ]
|
||||
supervisor_misses: 0 [ 0 ]
|
||||
|
||||
ruby_cycles_executed: 26617001 [ 26617001 ]
|
||||
ruby_cycles_executed: 287335 [ 287335 ]
|
||||
|
||||
transactions_started: 0 [ 0 ]
|
||||
transactions_ended: 0 [ 0 ]
|
||||
|
|
@ -141,41 +74,21 @@ cycles_per_transaction: 0 [ 0 ]
|
|||
misses_per_transaction: 0 [ 0 ]
|
||||
|
||||
|
||||
Memory control MemoryControl_0:
|
||||
memory_total_requests: 1082
|
||||
memory_reads: 557
|
||||
memory_writes: 525
|
||||
memory_refreshes: 10431
|
||||
memory_total_request_delays: 1311
|
||||
memory_delays_per_request: 1.21165
|
||||
memory_delays_in_input_queue: 525
|
||||
memory_delays_behind_head_of_bank_queue: 0
|
||||
memory_delays_stalled_at_head_of_bank_queue: 786
|
||||
memory_stalls_for_bank_busy: 180
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 38
|
||||
memory_stalls_for_bus: 546
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 22
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 58 43 53 51 67 43 40 32 18 19 34 51 41 46 28 10 31 8 8 12 42 34 9 20 10 25 44 26 25 58 55 41
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0
|
||||
Directory-0:0
|
||||
DMA-0:0
|
||||
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8873 average: 1 | standard deviation: 0 | 0 8873 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8874 average: 1 | standard deviation: 0 | 0 8874 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 2 max: 277 count: 8873 average: 11.531 | standard deviation: 40.8912 | 8316 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 0 0 0 11 0 0 0 0 480 0 0 0 0 10 0 0 0 0 10 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_1: [binsize: 2 max: 277 count: 6886 average: 8.82021 | standard deviation: 35.5704 | 6566 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 6 0 0 0 0 280 0 0 0 0 7 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 2 max: 277 count: 1053 average: 23.3457 | standard deviation: 57.517 | 913 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 0 0 0 4 0 0 0 0 118 0 0 0 0 2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 2 max: 257 count: 934 average: 18.197 | standard deviation: 50.763 | 837 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 1 0 0 0 0 82 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency: [binsize: 2 max: 373 count: 8873 average: 31.383 | standard deviation: 65.1247 | 0 7435 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 6 5 6 6 3 335 255 166 323 190 5 5 4 3 1 12 13 5 9 4 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 7 13 16 13 8 0 3 3 2 2 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_1: [binsize: 2 max: 287 count: 6886 average: 19.1856 | standard deviation: 51.0326 | 0 6248 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 4 1 3 2 158 129 57 116 103 3 1 2 2 1 4 7 1 5 4 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 6 4 3 5 5 0 1 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_2: [binsize: 2 max: 373 count: 1053 average: 91.7255 | standard deviation: 89.279 | 0 521 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 1 5 2 1 109 51 79 167 65 1 3 0 1 0 4 5 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 11 8 2 0 0 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ]
|
||||
miss_latency_3: [binsize: 2 max: 281 count: 934 average: 53.2784 | standard deviation: 80.2311 | 0 666 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 68 75 30 40 22 1 1 2 0 0 4 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 8 2 0 1 0 2 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
|
|
@ -189,22 +102,26 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
|
|||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 1082 average: 0 | standard deviation: 0 | 1082 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 1082 average: 0 | standard deviation: 0 | 1082 ]
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 2872 average: 0 | standard deviation: 0 | 2872 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 2872 average: 0 | standard deviation: 0 | 2872 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 557 average: 0 | standard deviation: 0 | 557 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 525 average: 0 | standard deviation: 0 | 525 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1438 average: 0 | standard deviation: 0 | 1438 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1434 average: 0 | standard deviation: 0 | 1434 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 1
|
||||
user_time: 0
|
||||
system_time: 0
|
||||
page_reclaims: 38363
|
||||
page_faults: 0
|
||||
page_reclaims: 7403
|
||||
page_faults: 2289
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 0
|
||||
|
|
@ -214,94 +131,127 @@ Network Stats
|
|||
|
||||
switch_0_inlinks: 2
|
||||
switch_0_outlinks: 2
|
||||
links_utilized_percent_switch_0: 0.000127033
|
||||
links_utilized_percent_switch_0_link_0: 5.08134e-05 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.000203254 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_0: 0.156073
|
||||
links_utilized_percent_switch_0_link_0: 0.0625405 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_0_link_1: 0.249605 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 557 4456 [ 0 557 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 525 4200 [ 0 0 525 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 557 4456 [ 557 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 525 4200 [ 525 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Response_Data: 1438 103536 [ 0 1438 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_0_Writeback_Control: 1434 11472 [ 0 0 1434 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Control: 1438 11504 [ 1438 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_0_link_1_Data: 1434 103248 [ 1434 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_1_inlinks: 2
|
||||
switch_1_outlinks: 2
|
||||
links_utilized_percent_switch_1: 0.000127033
|
||||
links_utilized_percent_switch_1_link_0: 5.08134e-05 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.000203254 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_1: 0.156282
|
||||
links_utilized_percent_switch_1_link_0: 0.0624012 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_1_link_1: 0.250162 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_1_link_0_Control: 557 4456 [ 557 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 525 4200 [ 525 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 557 4456 [ 0 557 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 525 4200 [ 0 0 525 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Control: 1438 11504 [ 1438 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_0_Data: 1434 103248 [ 1434 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Response_Data: 1438 103536 [ 0 1438 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_1_link_1_Writeback_Control: 1434 11472 [ 0 0 1434 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_2_inlinks: 2
|
||||
switch_2_outlinks: 2
|
||||
links_utilized_percent_switch_2: 0
|
||||
links_utilized_percent_switch_2_link_0: 0 bw: 640000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2: 0.249883
|
||||
links_utilized_percent_switch_2_link_0: 0.250162 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_2_link_1: 0.249605 bw: 160000 base_latency: 1
|
||||
|
||||
outgoing_messages_switch_2_link_0_Response_Data: 1438 103536 [ 0 1438 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_0_Writeback_Control: 1434 11472 [ 0 0 1434 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Control: 1438 11504 [ 1438 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_2_link_1_Data: 1434 103248 [ 1434 0 0 0 0 0 0 0 0 0 ] base_latency: 1
|
||||
|
||||
switch_3_inlinks: 3
|
||||
switch_3_outlinks: 3
|
||||
links_utilized_percent_switch_3: 0.000135502
|
||||
links_utilized_percent_switch_3_link_0: 0.000203254 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_1: 0.000203254 bw: 160000 base_latency: 1
|
||||
links_utilized_percent_switch_3_link_2: 0 bw: 160000 base_latency: 1
|
||||
Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 1438
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 1438
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf
|
||||
|
||||
outgoing_messages_switch_3_link_0_Response_Data: 557 4456 [ 0 557 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_0_Writeback_Control: 525 4200 [ 0 0 525 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Control: 557 4456 [ 557 0 0 0 0 0 ] base_latency: 1
|
||||
outgoing_messages_switch_3_link_1_Data: 525 4200 [ 525 0 0 0 0 0 ] base_latency: 1
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 36.9958%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 18.637%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 44.3672%
|
||||
|
||||
l1u_0 cache stats:
|
||||
l1u_0_total_misses: 557
|
||||
l1u_0_total_demand_misses: 557
|
||||
l1u_0_total_prefetches: 0
|
||||
l1u_0_total_sw_prefetches: 0
|
||||
l1u_0_total_hw_prefetches: 0
|
||||
l1u_0_misses_per_transaction: inf
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 1438 100%
|
||||
system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 8 count: 1438 average: 7.26912 | standard deviation: 1.85842 | 0 71 3 0 134 0 0 0 1230 ]
|
||||
|
||||
l1u_0_request_type_LD: 25.1346%
|
||||
l1u_0_request_type_ST: 17.4147%
|
||||
l1u_0_request_type_IFETCH: 57.4506%
|
||||
|
||||
l1u_0_access_mode_type_SupervisorMode: 557 100%
|
||||
l1u_0_request_size: [binsize: log2 max: 8 count: 557 average: 7.5368 | standard deviation: 1.45496 | 0 12 1 42 502 ]
|
||||
|
||||
--- DMA 0 ---
|
||||
--- L1Cache 0 ---
|
||||
- Event Counts -
|
||||
ReadRequest 0
|
||||
WriteRequest 0
|
||||
Data 0
|
||||
Ack 0
|
||||
Load 1053
|
||||
Ifetch 6886
|
||||
Store 934
|
||||
Data 1438
|
||||
Fwd_GETX 0
|
||||
Inv 0
|
||||
Replacement 1434
|
||||
Writeback_Ack 1434
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
READY ReadRequest 0 <--
|
||||
READY WriteRequest 0 <--
|
||||
I Load 532
|
||||
I Ifetch 638
|
||||
I Store 268
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
BUSY_RD Data 0 <--
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
BUSY_WR Ack 0 <--
|
||||
M Load 521
|
||||
M Ifetch 6248
|
||||
M Store 666
|
||||
M Fwd_GETX 0 <--
|
||||
M Inv 0 <--
|
||||
M Replacement 1434
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 1434
|
||||
|
||||
IS Data 1170
|
||||
|
||||
IM Data 268
|
||||
|
||||
Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer:
|
||||
memory_total_requests: 2872
|
||||
memory_reads: 1438
|
||||
memory_writes: 1434
|
||||
memory_refreshes: 599
|
||||
memory_total_request_delays: 3924
|
||||
memory_delays_per_request: 1.3663
|
||||
memory_delays_in_input_queue: 1431
|
||||
memory_delays_behind_head_of_bank_queue: 7
|
||||
memory_delays_stalled_at_head_of_bank_queue: 2486
|
||||
memory_stalls_for_bank_busy: 841
|
||||
memory_stalls_for_random_busy: 0
|
||||
memory_stalls_for_anti_starvation: 0
|
||||
memory_stalls_for_arbitration: 109
|
||||
memory_stalls_for_bus: 1466
|
||||
memory_stalls_for_tfaw: 0
|
||||
memory_stalls_for_read_write_turnaround: 70
|
||||
memory_stalls_for_read_read_turnaround: 0
|
||||
accesses_per_bank: 162 142 210 172 216 84 102 44 22 20 146 276 148 116 62 30 84 8 8 14 116 56 12 60 34 58 82 64 44 122 104 54
|
||||
|
||||
--- Directory 0 ---
|
||||
- Event Counts -
|
||||
GETX 557
|
||||
GETX 1438
|
||||
GETS 0
|
||||
PUTX 525
|
||||
PUTX 1434
|
||||
PUTX_NotOwner 0
|
||||
DMA_READ 0
|
||||
DMA_WRITE 0
|
||||
Memory_Data 557
|
||||
Memory_Ack 525
|
||||
Memory_Data 1438
|
||||
Memory_Ack 1434
|
||||
|
||||
- Transitions -
|
||||
I GETX 557
|
||||
I GETX 1438
|
||||
I PUTX_NotOwner 0 <--
|
||||
I DMA_READ 0 <--
|
||||
I DMA_WRITE 0 <--
|
||||
|
||||
M GETX 0 <--
|
||||
M PUTX 525
|
||||
M PUTX 1434
|
||||
M PUTX_NotOwner 0 <--
|
||||
M DMA_READ 0 <--
|
||||
M DMA_WRITE 0 <--
|
||||
|
|
@ -312,15 +262,19 @@ M_DRD PUTX 0 <--
|
|||
M_DWR GETX 0 <--
|
||||
M_DWR PUTX 0 <--
|
||||
|
||||
M_DWRI GETX 0 <--
|
||||
M_DWRI Memory_Ack 0 <--
|
||||
|
||||
M_DRDI GETX 0 <--
|
||||
M_DRDI Memory_Ack 0 <--
|
||||
|
||||
IM GETX 0 <--
|
||||
IM GETS 0 <--
|
||||
IM PUTX 0 <--
|
||||
IM PUTX_NotOwner 0 <--
|
||||
IM DMA_READ 0 <--
|
||||
IM DMA_WRITE 0 <--
|
||||
IM Memory_Data 557
|
||||
IM Memory_Data 1438
|
||||
|
||||
MI GETX 0 <--
|
||||
MI GETS 0 <--
|
||||
|
|
@ -328,7 +282,7 @@ MI PUTX 0 <--
|
|||
MI PUTX_NotOwner 0 <--
|
||||
MI DMA_READ 0 <--
|
||||
MI DMA_WRITE 0 <--
|
||||
MI Memory_Ack 525
|
||||
MI Memory_Ack 1434
|
||||
|
||||
ID GETX 0 <--
|
||||
ID GETS 0 <--
|
||||
|
|
@ -346,39 +300,3 @@ ID_W DMA_READ 0 <--
|
|||
ID_W DMA_WRITE 0 <--
|
||||
ID_W Memory_Ack 0 <--
|
||||
|
||||
--- L1Cache 0 ---
|
||||
- Event Counts -
|
||||
Load 1053
|
||||
Ifetch 6886
|
||||
Store 934
|
||||
Data 557
|
||||
Fwd_GETX 0
|
||||
Inv 0
|
||||
Replacement 525
|
||||
Writeback_Ack 525
|
||||
Writeback_Nack 0
|
||||
|
||||
- Transitions -
|
||||
I Load 140
|
||||
I Ifetch 320
|
||||
I Store 97
|
||||
I Inv 0 <--
|
||||
I Replacement 0 <--
|
||||
|
||||
II Writeback_Nack 0 <--
|
||||
|
||||
M Load 913
|
||||
M Ifetch 6566
|
||||
M Store 837
|
||||
M Fwd_GETX 0 <--
|
||||
M Inv 0 <--
|
||||
M Replacement 525
|
||||
|
||||
MI Fwd_GETX 0 <--
|
||||
MI Inv 0 <--
|
||||
MI Writeback_Ack 525
|
||||
|
||||
IS Data 460
|
||||
|
||||
IM Data 97
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,3 @@
|
|||
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "1", "-m", "1", "-s", "1024"]
|
||||
Error: User specified set of debug components, but the RUBY_DEBUG compile-time flag is false.
|
||||
Solution: Re-compile with RUBY_DEBUG set to true.
|
||||
print config: 1
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
warn: instruction 'fnstcw_Mw' unimplemented
|
||||
|
|
|
|||
|
|
@ -5,12 +5,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Aug 9 2009 04:00:16
|
||||
M5 revision 33faa9915d16+ 6486+ default tip
|
||||
M5 started Aug 9 2009 04:00:18
|
||||
M5 executing on tater
|
||||
command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
M5 compiled Jan 21 2010 12:13:38
|
||||
M5 revision a2fac757fb31+ 6860+ default qtip brad/rubycfg_orion_update tip
|
||||
M5 started Jan 21 2010 12:14:46
|
||||
M5 executing on svvint07
|
||||
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing-ruby
|
||||
Global frequency set at 1000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello world!
|
||||
Exiting @ tick 26617000 because target called exit()
|
||||
Exiting @ tick 287334 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,16 +1,16 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 2962 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 1384872 # Number of bytes of host memory used
|
||||
host_seconds 3.21 # Real time elapsed on the host
|
||||
host_tick_rate 8282962 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 52882 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 349184 # Number of bytes of host memory used
|
||||
host_seconds 0.18 # Real time elapsed on the host
|
||||
host_tick_rate 1596256 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
sim_insts 9519 # Number of instructions simulated
|
||||
sim_seconds 0.000027 # Number of seconds simulated
|
||||
sim_ticks 26617000 # Number of ticks simulated
|
||||
sim_seconds 0.000287 # Number of seconds simulated
|
||||
sim_ticks 287334 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 53234 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 287334 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 9519 # Number of instructions executed
|
||||
system.cpu.num_refs 1987 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,218 +0,0 @@
|
|||
[root]
|
||||
type=Root
|
||||
children=system
|
||||
dummy=0
|
||||
|
||||
[system]
|
||||
type=System
|
||||
children=cpu0 cpu1 cpu2 cpu3 membus physmem
|
||||
mem_mode=atomic
|
||||
physmem=system.physmem
|
||||
|
||||
[system.cpu0]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb itb tracer workload
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=0
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu0.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
itb=system.cpu0.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu0.tracer
|
||||
width=1
|
||||
workload=system.cpu0.workload
|
||||
dcache_port=system.membus.port[1]
|
||||
icache_port=system.membus.port[0]
|
||||
|
||||
[system.cpu0.dtb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu0.itb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu0.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu0.workload]
|
||||
type=LiveProcess
|
||||
cmd=test_atomic 4
|
||||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
|
||||
gid=100
|
||||
input=cin
|
||||
max_stack_size=67108864
|
||||
output=cout
|
||||
pid=100
|
||||
ppid=99
|
||||
simpoint=0
|
||||
system=system
|
||||
uid=100
|
||||
|
||||
[system.cpu1]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=1
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu1.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
itb=system.cpu1.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu1.tracer
|
||||
width=1
|
||||
workload=system.cpu0.workload
|
||||
dcache_port=system.membus.port[3]
|
||||
icache_port=system.membus.port[2]
|
||||
|
||||
[system.cpu1.dtb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu1.itb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu1.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu2]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=2
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu2.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
itb=system.cpu2.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu2.tracer
|
||||
width=1
|
||||
workload=system.cpu0.workload
|
||||
dcache_port=system.membus.port[5]
|
||||
icache_port=system.membus.port[4]
|
||||
|
||||
[system.cpu2.dtb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu2.itb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu2.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.cpu3]
|
||||
type=AtomicSimpleCPU
|
||||
children=dtb itb tracer
|
||||
checker=Null
|
||||
clock=500
|
||||
cpu_id=3
|
||||
defer_registration=false
|
||||
do_checkpoint_insts=true
|
||||
do_statistics_insts=true
|
||||
dtb=system.cpu3.dtb
|
||||
function_trace=false
|
||||
function_trace_start=0
|
||||
itb=system.cpu3.itb
|
||||
max_insts_all_threads=0
|
||||
max_insts_any_thread=0
|
||||
max_loads_all_threads=0
|
||||
max_loads_any_thread=0
|
||||
numThreads=1
|
||||
phase=0
|
||||
progress_interval=0
|
||||
simulate_data_stalls=false
|
||||
simulate_inst_stalls=false
|
||||
system=system
|
||||
tracer=system.cpu3.tracer
|
||||
width=1
|
||||
workload=system.cpu0.workload
|
||||
dcache_port=system.membus.port[7]
|
||||
icache_port=system.membus.port[6]
|
||||
|
||||
[system.cpu3.dtb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu3.itb]
|
||||
type=SparcTLB
|
||||
size=64
|
||||
|
||||
[system.cpu3.tracer]
|
||||
type=ExeTracer
|
||||
|
||||
[system.membus]
|
||||
type=Bus
|
||||
block_size=64
|
||||
bus_id=0
|
||||
clock=1000
|
||||
header_cycles=1
|
||||
responder_set=false
|
||||
width=64
|
||||
port=system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port system.cpu2.icache_port system.cpu2.dcache_port system.cpu3.icache_port system.cpu3.dcache_port system.physmem.port[0]
|
||||
|
||||
[system.physmem]
|
||||
type=RubyMemory
|
||||
clock=1
|
||||
config_file=
|
||||
config_options=
|
||||
debug=false
|
||||
debug_file=
|
||||
file=
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
num_cpus=4
|
||||
phase=0
|
||||
range=0:134217727
|
||||
stats_file=ruby.stats
|
||||
zero=false
|
||||
port=system.membus.port[8]
|
||||
|
||||
|
|
@ -1,930 +0,0 @@
|
|||
|
||||
================ Begin RubySystem Configuration Print ================
|
||||
|
||||
Ruby Configuration
|
||||
------------------
|
||||
protocol: MOSI_SMP_bcast
|
||||
compiled_at: 22:54:24, May 4 2009
|
||||
RUBY_DEBUG: false
|
||||
hostname: piton
|
||||
g_RANDOM_SEED: 1
|
||||
g_DEADLOCK_THRESHOLD: 500000
|
||||
RANDOMIZATION: false
|
||||
g_SYNTHETIC_DRIVER: false
|
||||
g_DETERMINISTIC_DRIVER: false
|
||||
g_FILTERING_ENABLED: false
|
||||
g_DISTRIBUTED_PERSISTENT_ENABLED: true
|
||||
g_DYNAMIC_TIMEOUT_ENABLED: true
|
||||
g_RETRY_THRESHOLD: 1
|
||||
g_FIXED_TIMEOUT_LATENCY: 300
|
||||
g_trace_warmup_length: 1000000
|
||||
g_bash_bandwidth_adaptive_threshold: 0.75
|
||||
g_tester_length: 0
|
||||
g_synthetic_locks: 2048
|
||||
g_deterministic_addrs: 1
|
||||
g_SpecifiedGenerator: DetermInvGenerator
|
||||
g_callback_counter: 0
|
||||
g_NUM_COMPLETIONS_BEFORE_PASS: 0
|
||||
g_NUM_SMT_THREADS: 1
|
||||
g_think_time: 5
|
||||
g_hold_time: 5
|
||||
g_wait_time: 5
|
||||
PROTOCOL_DEBUG_TRACE: true
|
||||
DEBUG_FILTER_STRING: none
|
||||
DEBUG_VERBOSITY_STRING: none
|
||||
DEBUG_START_TIME: 0
|
||||
DEBUG_OUTPUT_FILENAME: none
|
||||
SIMICS_RUBY_MULTIPLIER: 4
|
||||
OPAL_RUBY_MULTIPLIER: 1
|
||||
TRANSACTION_TRACE_ENABLED: false
|
||||
USER_MODE_DATA_ONLY: false
|
||||
PROFILE_HOT_LINES: false
|
||||
PROFILE_ALL_INSTRUCTIONS: false
|
||||
PRINT_INSTRUCTION_TRACE: false
|
||||
g_DEBUG_CYCLE: 0
|
||||
BLOCK_STC: false
|
||||
PERFECT_MEMORY_SYSTEM: false
|
||||
PERFECT_MEMORY_SYSTEM_LATENCY: 0
|
||||
DATA_BLOCK: false
|
||||
REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false
|
||||
L1_CACHE_ASSOC: 4
|
||||
L1_CACHE_NUM_SETS_BITS: 8
|
||||
L2_CACHE_ASSOC: 4
|
||||
L2_CACHE_NUM_SETS_BITS: 16
|
||||
g_MEMORY_SIZE_BYTES: 4294967296
|
||||
g_DATA_BLOCK_BYTES: 64
|
||||
g_PAGE_SIZE_BYTES: 4096
|
||||
g_REPLACEMENT_POLICY: PSEDUO_LRU
|
||||
g_NUM_PROCESSORS: 4
|
||||
g_NUM_L2_BANKS: 4
|
||||
g_NUM_MEMORIES: 4
|
||||
g_PROCS_PER_CHIP: 1
|
||||
g_NUM_CHIPS: 4
|
||||
g_NUM_CHIP_BITS: 2
|
||||
g_MEMORY_SIZE_BITS: 32
|
||||
g_DATA_BLOCK_BITS: 6
|
||||
g_PAGE_SIZE_BITS: 12
|
||||
g_NUM_PROCESSORS_BITS: 2
|
||||
g_PROCS_PER_CHIP_BITS: 0
|
||||
g_NUM_L2_BANKS_BITS: 2
|
||||
g_NUM_L2_BANKS_PER_CHIP_BITS: 0
|
||||
g_NUM_L2_BANKS_PER_CHIP: 1
|
||||
g_NUM_MEMORIES_BITS: 2
|
||||
g_NUM_MEMORIES_PER_CHIP: 1
|
||||
g_MEMORY_MODULE_BITS: 24
|
||||
g_MEMORY_MODULE_BLOCKS: 16777216
|
||||
MAP_L2BANKS_TO_LOWEST_BITS: false
|
||||
DIRECTORY_CACHE_LATENCY: 6
|
||||
NULL_LATENCY: 1
|
||||
ISSUE_LATENCY: 2
|
||||
CACHE_RESPONSE_LATENCY: 12
|
||||
L2_RESPONSE_LATENCY: 6
|
||||
L2_TAG_LATENCY: 6
|
||||
L1_RESPONSE_LATENCY: 3
|
||||
MEMORY_RESPONSE_LATENCY_MINUS_2: 158
|
||||
DIRECTORY_LATENCY: 80
|
||||
NETWORK_LINK_LATENCY: 1
|
||||
COPY_HEAD_LATENCY: 4
|
||||
ON_CHIP_LINK_LATENCY: 1
|
||||
RECYCLE_LATENCY: 10
|
||||
L2_RECYCLE_LATENCY: 5
|
||||
TIMER_LATENCY: 10000
|
||||
TBE_RESPONSE_LATENCY: 1
|
||||
PERIODIC_TIMER_WAKEUPS: true
|
||||
PROFILE_EXCEPTIONS: false
|
||||
PROFILE_XACT: true
|
||||
PROFILE_NONXACT: false
|
||||
XACT_DEBUG: true
|
||||
XACT_DEBUG_LEVEL: 1
|
||||
XACT_MEMORY: false
|
||||
XACT_ENABLE_TOURMALINE: false
|
||||
XACT_NUM_CURRENT: 0
|
||||
XACT_LAST_UPDATE: 0
|
||||
XACT_ISOLATION_CHECK: false
|
||||
PERFECT_FILTER: true
|
||||
READ_WRITE_FILTER: Perfect_
|
||||
PERFECT_VIRTUAL_FILTER: true
|
||||
VIRTUAL_READ_WRITE_FILTER: Perfect_
|
||||
PERFECT_SUMMARY_FILTER: true
|
||||
SUMMARY_READ_WRITE_FILTER: Perfect_
|
||||
XACT_EAGER_CD: true
|
||||
XACT_LAZY_VM: false
|
||||
XACT_CONFLICT_RES: BASE
|
||||
XACT_VISUALIZER: false
|
||||
XACT_COMMIT_TOKEN_LATENCY: 0
|
||||
XACT_NO_BACKOFF: false
|
||||
XACT_LOG_BUFFER_SIZE: 0
|
||||
XACT_STORE_PREDICTOR_HISTORY: 256
|
||||
XACT_STORE_PREDICTOR_ENTRIES: 256
|
||||
XACT_STORE_PREDICTOR_THRESHOLD: 4
|
||||
XACT_FIRST_ACCESS_COST: 0
|
||||
XACT_FIRST_PAGE_ACCESS_COST: 0
|
||||
ENABLE_MAGIC_WAITING: false
|
||||
ENABLE_WATCHPOINT: false
|
||||
XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false
|
||||
ATMTP_ENABLED: false
|
||||
ATMTP_ABORT_ON_NON_XACT_INST: false
|
||||
ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false
|
||||
ATMTP_XACT_MAX_STORES: 32
|
||||
ATMTP_DEBUG_LEVEL: 0
|
||||
L1_REQUEST_LATENCY: 2
|
||||
L2_REQUEST_LATENCY: 4
|
||||
SINGLE_ACCESS_L2_BANKS: true
|
||||
SEQUENCER_TO_CONTROLLER_LATENCY: 4
|
||||
L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
|
||||
L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32
|
||||
DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32
|
||||
g_SEQUENCER_OUTSTANDING_REQUESTS: 16
|
||||
NUMBER_OF_TBES: 128
|
||||
NUMBER_OF_L1_TBES: 32
|
||||
NUMBER_OF_L2_TBES: 32
|
||||
FINITE_BUFFERING: false
|
||||
FINITE_BUFFER_SIZE: 3
|
||||
PROCESSOR_BUFFER_SIZE: 10
|
||||
PROTOCOL_BUFFER_SIZE: 32
|
||||
TSO: false
|
||||
g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH
|
||||
g_CACHE_DESIGN: NUCA
|
||||
g_endpoint_bandwidth: 10000
|
||||
g_adaptive_routing: true
|
||||
NUMBER_OF_VIRTUAL_NETWORKS: 4
|
||||
FAN_OUT_DEGREE: 4
|
||||
g_PRINT_TOPOLOGY: true
|
||||
XACT_LENGTH: 0
|
||||
XACT_SIZE: 0
|
||||
ABORT_RETRY_TIME: 0
|
||||
g_GARNET_NETWORK: false
|
||||
g_DETAIL_NETWORK: false
|
||||
g_NETWORK_TESTING: false
|
||||
g_FLIT_SIZE: 16
|
||||
g_NUM_PIPE_STAGES: 4
|
||||
g_VCS_PER_CLASS: 4
|
||||
g_BUFFER_SIZE: 4
|
||||
MEM_BUS_CYCLE_MULTIPLIER: 10
|
||||
BANKS_PER_RANK: 8
|
||||
RANKS_PER_DIMM: 2
|
||||
DIMMS_PER_CHANNEL: 2
|
||||
BANK_BIT_0: 8
|
||||
RANK_BIT_0: 11
|
||||
DIMM_BIT_0: 12
|
||||
BANK_QUEUE_SIZE: 12
|
||||
BANK_BUSY_TIME: 11
|
||||
RANK_RANK_DELAY: 1
|
||||
READ_WRITE_DELAY: 2
|
||||
BASIC_BUS_BUSY_TIME: 2
|
||||
MEM_CTL_LATENCY: 12
|
||||
REFRESH_PERIOD: 1560
|
||||
TFAW: 0
|
||||
MEM_RANDOM_ARBITRATE: 0
|
||||
MEM_FIXED_DELAY: 0
|
||||
|
||||
Chip Config
|
||||
-----------
|
||||
Total_Chips: 4
|
||||
|
||||
L1Cache_TBEs numberPerChip: 1
|
||||
TBEs_per_TBETable: 128
|
||||
|
||||
L1Cache_L1IcacheMemory numberPerChip: 1
|
||||
Cache config: L1Cache_0_L1I
|
||||
cache_associativity: 4
|
||||
num_cache_sets_bits: 8
|
||||
num_cache_sets: 256
|
||||
cache_set_size_bytes: 16384
|
||||
cache_set_size_Kbytes: 16
|
||||
cache_set_size_Mbytes: 0.015625
|
||||
cache_size_bytes: 65536
|
||||
cache_size_Kbytes: 64
|
||||
cache_size_Mbytes: 0.0625
|
||||
|
||||
L1Cache_L1DcacheMemory numberPerChip: 1
|
||||
Cache config: L1Cache_0_L1D
|
||||
cache_associativity: 4
|
||||
num_cache_sets_bits: 8
|
||||
num_cache_sets: 256
|
||||
cache_set_size_bytes: 16384
|
||||
cache_set_size_Kbytes: 16
|
||||
cache_set_size_Mbytes: 0.015625
|
||||
cache_size_bytes: 65536
|
||||
cache_size_Kbytes: 64
|
||||
cache_size_Mbytes: 0.0625
|
||||
|
||||
L1Cache_L2cacheMemory numberPerChip: 1
|
||||
Cache config: L1Cache_0_L2
|
||||
cache_associativity: 4
|
||||
num_cache_sets_bits: 16
|
||||
num_cache_sets: 65536
|
||||
cache_set_size_bytes: 4194304
|
||||
cache_set_size_Kbytes: 4096
|
||||
cache_set_size_Mbytes: 4
|
||||
cache_size_bytes: 16777216
|
||||
cache_size_Kbytes: 16384
|
||||
cache_size_Mbytes: 16
|
||||
|
||||
L1Cache_mandatoryQueue numberPerChip: 1
|
||||
|
||||
L1Cache_sequencer numberPerChip: 1
|
||||
sequencer: Sequencer - SC
|
||||
max_outstanding_requests: 16
|
||||
|
||||
L1Cache_storeBuffer numberPerChip: 1
|
||||
Store buffer entries: 128 (Only valid if TSO is enabled)
|
||||
|
||||
Directory_directory numberPerChip: 1
|
||||
Memory config:
|
||||
memory_bits: 32
|
||||
memory_size_bytes: 4294967296
|
||||
memory_size_Kbytes: 4.1943e+06
|
||||
memory_size_Mbytes: 4096
|
||||
memory_size_Gbytes: 4
|
||||
module_bits: 24
|
||||
module_size_lines: 16777216
|
||||
module_size_bytes: 1073741824
|
||||
module_size_Kbytes: 1.04858e+06
|
||||
module_size_Mbytes: 1024
|
||||
|
||||
|
||||
Network Configuration
|
||||
---------------------
|
||||
network: SIMPLE_NETWORK
|
||||
topology: HIERARCHICAL_SWITCH
|
||||
|
||||
virtual_net_0: active, ordered
|
||||
virtual_net_1: active, unordered
|
||||
virtual_net_2: inactive
|
||||
virtual_net_3: inactive
|
||||
|
||||
--- Begin Topology Print ---
|
||||
|
||||
Topology print ONLY indicates the _NETWORK_ latency between two machines
|
||||
It does NOT include the latency within the machines
|
||||
|
||||
L1Cache-0 Network Latencies
|
||||
L1Cache-0 -> L1Cache-1 net_lat: 9
|
||||
L1Cache-0 -> L1Cache-2 net_lat: 9
|
||||
L1Cache-0 -> L1Cache-3 net_lat: 9
|
||||
L1Cache-0 -> Directory-0 net_lat: 9
|
||||
L1Cache-0 -> Directory-1 net_lat: 9
|
||||
L1Cache-0 -> Directory-2 net_lat: 9
|
||||
L1Cache-0 -> Directory-3 net_lat: 9
|
||||
|
||||
L1Cache-1 Network Latencies
|
||||
L1Cache-1 -> L1Cache-0 net_lat: 9
|
||||
L1Cache-1 -> L1Cache-2 net_lat: 9
|
||||
L1Cache-1 -> L1Cache-3 net_lat: 9
|
||||
L1Cache-1 -> Directory-0 net_lat: 9
|
||||
L1Cache-1 -> Directory-1 net_lat: 9
|
||||
L1Cache-1 -> Directory-2 net_lat: 9
|
||||
L1Cache-1 -> Directory-3 net_lat: 9
|
||||
|
||||
L1Cache-2 Network Latencies
|
||||
L1Cache-2 -> L1Cache-0 net_lat: 9
|
||||
L1Cache-2 -> L1Cache-1 net_lat: 9
|
||||
L1Cache-2 -> L1Cache-3 net_lat: 9
|
||||
L1Cache-2 -> Directory-0 net_lat: 9
|
||||
L1Cache-2 -> Directory-1 net_lat: 9
|
||||
L1Cache-2 -> Directory-2 net_lat: 9
|
||||
L1Cache-2 -> Directory-3 net_lat: 9
|
||||
|
||||
L1Cache-3 Network Latencies
|
||||
L1Cache-3 -> L1Cache-0 net_lat: 9
|
||||
L1Cache-3 -> L1Cache-1 net_lat: 9
|
||||
L1Cache-3 -> L1Cache-2 net_lat: 9
|
||||
L1Cache-3 -> Directory-0 net_lat: 9
|
||||
L1Cache-3 -> Directory-1 net_lat: 9
|
||||
L1Cache-3 -> Directory-2 net_lat: 9
|
||||
L1Cache-3 -> Directory-3 net_lat: 9
|
||||
|
||||
Directory-0 Network Latencies
|
||||
Directory-0 -> L1Cache-0 net_lat: 9
|
||||
Directory-0 -> L1Cache-1 net_lat: 9
|
||||
Directory-0 -> L1Cache-2 net_lat: 9
|
||||
Directory-0 -> L1Cache-3 net_lat: 9
|
||||
Directory-0 -> Directory-1 net_lat: 9
|
||||
Directory-0 -> Directory-2 net_lat: 9
|
||||
Directory-0 -> Directory-3 net_lat: 9
|
||||
|
||||
Directory-1 Network Latencies
|
||||
Directory-1 -> L1Cache-0 net_lat: 9
|
||||
Directory-1 -> L1Cache-1 net_lat: 9
|
||||
Directory-1 -> L1Cache-2 net_lat: 9
|
||||
Directory-1 -> L1Cache-3 net_lat: 9
|
||||
Directory-1 -> Directory-0 net_lat: 9
|
||||
Directory-1 -> Directory-2 net_lat: 9
|
||||
Directory-1 -> Directory-3 net_lat: 9
|
||||
|
||||
Directory-2 Network Latencies
|
||||
Directory-2 -> L1Cache-0 net_lat: 9
|
||||
Directory-2 -> L1Cache-1 net_lat: 9
|
||||
Directory-2 -> L1Cache-2 net_lat: 9
|
||||
Directory-2 -> L1Cache-3 net_lat: 9
|
||||
Directory-2 -> Directory-0 net_lat: 9
|
||||
Directory-2 -> Directory-1 net_lat: 9
|
||||
Directory-2 -> Directory-3 net_lat: 9
|
||||
|
||||
Directory-3 Network Latencies
|
||||
Directory-3 -> L1Cache-0 net_lat: 9
|
||||
Directory-3 -> L1Cache-1 net_lat: 9
|
||||
Directory-3 -> L1Cache-2 net_lat: 9
|
||||
Directory-3 -> L1Cache-3 net_lat: 9
|
||||
Directory-3 -> Directory-0 net_lat: 9
|
||||
Directory-3 -> Directory-1 net_lat: 9
|
||||
Directory-3 -> Directory-2 net_lat: 9
|
||||
|
||||
--- End Topology Print ---
|
||||
|
||||
Profiler Configuration
|
||||
----------------------
|
||||
periodic_stats_period: 1000000
|
||||
|
||||
================ End RubySystem Configuration Print ================
|
||||
|
||||
|
||||
Real time: May/05/2009 07:34:05
|
||||
|
||||
Profiler Stats
|
||||
--------------
|
||||
Elapsed_time_in_seconds: 3
|
||||
Elapsed_time_in_minutes: 0.05
|
||||
Elapsed_time_in_hours: 0.000833333
|
||||
Elapsed_time_in_days: 3.47222e-05
|
||||
|
||||
Virtual_time_in_seconds: 1.88
|
||||
Virtual_time_in_minutes: 0.0313333
|
||||
Virtual_time_in_hours: 0.000522222
|
||||
Virtual_time_in_days: 0.000522222
|
||||
|
||||
Ruby_current_time: 87713501
|
||||
Ruby_start_time: 1
|
||||
Ruby_cycles: 87713500
|
||||
|
||||
mbytes_resident: 90.4062
|
||||
mbytes_total: 251.832
|
||||
resident_ratio: 0.35901
|
||||
|
||||
Total_misses: 0
|
||||
total_misses: 0 [ 0 0 0 0 ]
|
||||
user_misses: 0 [ 0 0 0 0 ]
|
||||
supervisor_misses: 0 [ 0 0 0 0 ]
|
||||
|
||||
instruction_executed: 4 [ 1 1 1 1 ]
|
||||
cycles_executed: 4 [ 1 1 1 1 ]
|
||||
cycles_per_instruction: 8.77135e+07 [ 8.77135e+07 8.77135e+07 8.77135e+07 8.77135e+07 ]
|
||||
misses_per_thousand_instructions: 0 [ 0 0 0 0 ]
|
||||
|
||||
transactions_started: 0 [ 0 0 0 0 ]
|
||||
transactions_ended: 0 [ 0 0 0 0 ]
|
||||
instructions_per_transaction: 0 [ 0 0 0 0 ]
|
||||
cycles_per_transaction: 0 [ 0 0 0 0 ]
|
||||
misses_per_transaction: 0 [ 0 0 0 0 ]
|
||||
|
||||
L1D_cache cache stats:
|
||||
L1D_cache_total_misses: 0
|
||||
L1D_cache_total_demand_misses: 0
|
||||
L1D_cache_total_prefetches: 0
|
||||
L1D_cache_total_sw_prefetches: 0
|
||||
L1D_cache_total_hw_prefetches: 0
|
||||
L1D_cache_misses_per_transaction: 0
|
||||
L1D_cache_misses_per_instruction: 0
|
||||
L1D_cache_instructions_per_misses: NaN
|
||||
|
||||
L1D_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
L1I_cache cache stats:
|
||||
L1I_cache_total_misses: 0
|
||||
L1I_cache_total_demand_misses: 0
|
||||
L1I_cache_total_prefetches: 0
|
||||
L1I_cache_total_sw_prefetches: 0
|
||||
L1I_cache_total_hw_prefetches: 0
|
||||
L1I_cache_misses_per_transaction: 0
|
||||
L1I_cache_misses_per_instruction: 0
|
||||
L1I_cache_instructions_per_misses: NaN
|
||||
|
||||
L1I_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
L2_cache cache stats:
|
||||
L2_cache_total_misses: 0
|
||||
L2_cache_total_demand_misses: 0
|
||||
L2_cache_total_prefetches: 0
|
||||
L2_cache_total_sw_prefetches: 0
|
||||
L2_cache_total_hw_prefetches: 0
|
||||
L2_cache_misses_per_transaction: 0
|
||||
L2_cache_misses_per_instruction: 0
|
||||
L2_cache_instructions_per_misses: NaN
|
||||
|
||||
L2_cache_request_size: [binsize: log2 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
|
||||
Busy Controller Counts:
|
||||
L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0
|
||||
Directory-0:0 Directory-1:0 Directory-2:0 Directory-3:0
|
||||
|
||||
Busy Bank Count:0
|
||||
|
||||
L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
L2TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
sequencer_requests_outstanding: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
All Non-Zero Cycle Demand Cache Accesses
|
||||
----------------------------------------
|
||||
miss_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
All Non-Zero Cycle SW Prefetch Requests
|
||||
------------------------------------
|
||||
prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Request vs. RubySystem State Profile
|
||||
--------------------------------
|
||||
|
||||
|
||||
filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Message Delayed Cycles
|
||||
----------------------
|
||||
Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
|
||||
|
||||
Resource Usage
|
||||
--------------
|
||||
page_size: 4096
|
||||
user_time: 1
|
||||
system_time: 0
|
||||
page_reclaims: 23338
|
||||
page_faults: 0
|
||||
swaps: 0
|
||||
block_inputs: 0
|
||||
block_outputs: 640
|
||||
MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
|
||||
MessageBuffer: [Chip 1 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
|
||||
MessageBuffer: [Chip 2 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
|
||||
MessageBuffer: [Chip 3 0, L1Cache, mandatoryQueue_in] stats - msgs:0 full:0
|
||||
|
||||
Network Stats
|
||||
-------------
|
||||
|
||||
switch_0_inlinks: 1
|
||||
switch_0_outlinks: 1
|
||||
links_utilized_percent_switch_0: 0
|
||||
links_utilized_percent_switch_0_link_0: 0 bw: 10000 base_latency: 1
|
||||
|
||||
|
||||
switch_1_inlinks: 1
|
||||
switch_1_outlinks: 1
|
||||
links_utilized_percent_switch_1: 0
|
||||
links_utilized_percent_switch_1_link_0: 0 bw: 10000 base_latency: 1
|
||||
|
||||
|
||||
switch_2_inlinks: 1
|
||||
switch_2_outlinks: 1
|
||||
links_utilized_percent_switch_2: 0
|
||||
links_utilized_percent_switch_2_link_0: 0 bw: 10000 base_latency: 1
|
||||
|
||||
|
||||
switch_3_inlinks: 1
|
||||
switch_3_outlinks: 1
|
||||
links_utilized_percent_switch_3: 0
|
||||
links_utilized_percent_switch_3_link_0: 0 bw: 10000 base_latency: 1
|
||||
|
||||
|
||||
switch_4_inlinks: 1
|
||||
switch_4_outlinks: 1
|
||||
links_utilized_percent_switch_4: 0
|
||||
links_utilized_percent_switch_4_link_0: 0 bw: 10000 base_latency: 1
|
||||
|
||||
|
||||
switch_5_inlinks: 1
|
||||
switch_5_outlinks: 1
|
||||
links_utilized_percent_switch_5: 0
|
||||
links_utilized_percent_switch_5_link_0: 0 bw: 10000 base_latency: 1
|
||||
|
||||
|
||||
switch_6_inlinks: 1
|
||||
switch_6_outlinks: 1
|
||||
links_utilized_percent_switch_6: 0
|
||||
links_utilized_percent_switch_6_link_0: 0 bw: 10000 base_latency: 1
|
||||
|
||||
|
||||
switch_7_inlinks: 1
|
||||
switch_7_outlinks: 1
|
||||
links_utilized_percent_switch_7: 0
|
||||
links_utilized_percent_switch_7_link_0: 0 bw: 10000 base_latency: 1
|
||||
|
||||
|
||||
switch_8_inlinks: 4
|
||||
switch_8_outlinks: 1
|
||||
links_utilized_percent_switch_8: 0
|
||||
links_utilized_percent_switch_8_link_0: 0 bw: 10000 base_latency: 1
|
||||
|
||||
|
||||
switch_9_inlinks: 4
|
||||
switch_9_outlinks: 1
|
||||
links_utilized_percent_switch_9: 0
|
||||
links_utilized_percent_switch_9_link_0: 0 bw: 10000 base_latency: 1
|
||||
|
||||
|
||||
switch_10_inlinks: 2
|
||||
switch_10_outlinks: 2
|
||||
links_utilized_percent_switch_10: 0
|
||||
links_utilized_percent_switch_10_link_0: 0 bw: 10000 base_latency: 1
|
||||
links_utilized_percent_switch_10_link_1: 0 bw: 10000 base_latency: 1
|
||||
|
||||
|
||||
switch_11_inlinks: 1
|
||||
switch_11_outlinks: 4
|
||||
links_utilized_percent_switch_11: 0
|
||||
links_utilized_percent_switch_11_link_0: 0 bw: 10000 base_latency: 1
|
||||
links_utilized_percent_switch_11_link_1: 0 bw: 10000 base_latency: 1
|
||||
links_utilized_percent_switch_11_link_2: 0 bw: 10000 base_latency: 1
|
||||
links_utilized_percent_switch_11_link_3: 0 bw: 10000 base_latency: 1
|
||||
|
||||
|
||||
switch_12_inlinks: 1
|
||||
switch_12_outlinks: 4
|
||||
links_utilized_percent_switch_12: 0
|
||||
links_utilized_percent_switch_12_link_0: 0 bw: 10000 base_latency: 1
|
||||
links_utilized_percent_switch_12_link_1: 0 bw: 10000 base_latency: 1
|
||||
links_utilized_percent_switch_12_link_2: 0 bw: 10000 base_latency: 1
|
||||
links_utilized_percent_switch_12_link_3: 0 bw: 10000 base_latency: 1
|
||||
|
||||
|
||||
|
||||
Chip Stats
|
||||
----------
|
||||
|
||||
--- L1Cache ---
|
||||
- Event Counts -
|
||||
Load 0
|
||||
Ifetch 0
|
||||
Store 0
|
||||
L1_to_L2 0
|
||||
L2_to_L1D 0
|
||||
L2_to_L1I 0
|
||||
L2_Replacement 0
|
||||
Own_GETS 0
|
||||
Own_GET_INSTR 0
|
||||
Own_GETX 0
|
||||
Own_PUTX 0
|
||||
Other_GETS 0
|
||||
Other_GET_INSTR 0
|
||||
Other_GETX 0
|
||||
Other_PUTX 0
|
||||
Data 0
|
||||
|
||||
- Transitions -
|
||||
NP Load 0 <--
|
||||
NP Ifetch 0 <--
|
||||
NP Store 0 <--
|
||||
NP Other_GETS 0 <--
|
||||
NP Other_GET_INSTR 0 <--
|
||||
NP Other_GETX 0 <--
|
||||
NP Other_PUTX 0 <--
|
||||
|
||||
I Load 0 <--
|
||||
I Ifetch 0 <--
|
||||
I Store 0 <--
|
||||
I L1_to_L2 0 <--
|
||||
I L2_to_L1D 0 <--
|
||||
I L2_to_L1I 0 <--
|
||||
I L2_Replacement 0 <--
|
||||
I Other_GETS 0 <--
|
||||
I Other_GET_INSTR 0 <--
|
||||
I Other_GETX 0 <--
|
||||
I Other_PUTX 0 <--
|
||||
|
||||
S Load 0 <--
|
||||
S Ifetch 0 <--
|
||||
S Store 0 <--
|
||||
S L1_to_L2 0 <--
|
||||
S L2_to_L1D 0 <--
|
||||
S L2_to_L1I 0 <--
|
||||
S L2_Replacement 0 <--
|
||||
S Other_GETS 0 <--
|
||||
S Other_GET_INSTR 0 <--
|
||||
S Other_GETX 0 <--
|
||||
S Other_PUTX 0 <--
|
||||
|
||||
O Load 0 <--
|
||||
O Ifetch 0 <--
|
||||
O Store 0 <--
|
||||
O L1_to_L2 0 <--
|
||||
O L2_to_L1D 0 <--
|
||||
O L2_to_L1I 0 <--
|
||||
O L2_Replacement 0 <--
|
||||
O Other_GETS 0 <--
|
||||
O Other_GET_INSTR 0 <--
|
||||
O Other_GETX 0 <--
|
||||
O Other_PUTX 0 <--
|
||||
|
||||
M Load 0 <--
|
||||
M Ifetch 0 <--
|
||||
M Store 0 <--
|
||||
M L1_to_L2 0 <--
|
||||
M L2_to_L1D 0 <--
|
||||
M L2_to_L1I 0 <--
|
||||
M L2_Replacement 0 <--
|
||||
M Other_GETS 0 <--
|
||||
M Other_GET_INSTR 0 <--
|
||||
M Other_GETX 0 <--
|
||||
M Other_PUTX 0 <--
|
||||
|
||||
IS_AD Load 0 <--
|
||||
IS_AD Ifetch 0 <--
|
||||
IS_AD Store 0 <--
|
||||
IS_AD L1_to_L2 0 <--
|
||||
IS_AD L2_to_L1D 0 <--
|
||||
IS_AD L2_to_L1I 0 <--
|
||||
IS_AD L2_Replacement 0 <--
|
||||
IS_AD Own_GETS 0 <--
|
||||
IS_AD Own_GET_INSTR 0 <--
|
||||
IS_AD Other_GETS 0 <--
|
||||
IS_AD Other_GET_INSTR 0 <--
|
||||
IS_AD Other_GETX 0 <--
|
||||
IS_AD Other_PUTX 0 <--
|
||||
IS_AD Data 0 <--
|
||||
|
||||
IM_AD Load 0 <--
|
||||
IM_AD Ifetch 0 <--
|
||||
IM_AD Store 0 <--
|
||||
IM_AD L1_to_L2 0 <--
|
||||
IM_AD L2_to_L1D 0 <--
|
||||
IM_AD L2_to_L1I 0 <--
|
||||
IM_AD L2_Replacement 0 <--
|
||||
IM_AD Own_GETX 0 <--
|
||||
IM_AD Other_GETS 0 <--
|
||||
IM_AD Other_GET_INSTR 0 <--
|
||||
IM_AD Other_GETX 0 <--
|
||||
IM_AD Other_PUTX 0 <--
|
||||
IM_AD Data 0 <--
|
||||
|
||||
SM_AD Load 0 <--
|
||||
SM_AD Ifetch 0 <--
|
||||
SM_AD Store 0 <--
|
||||
SM_AD L1_to_L2 0 <--
|
||||
SM_AD L2_to_L1D 0 <--
|
||||
SM_AD L2_to_L1I 0 <--
|
||||
SM_AD L2_Replacement 0 <--
|
||||
SM_AD Own_GETX 0 <--
|
||||
SM_AD Other_GETS 0 <--
|
||||
SM_AD Other_GET_INSTR 0 <--
|
||||
SM_AD Other_GETX 0 <--
|
||||
SM_AD Other_PUTX 0 <--
|
||||
SM_AD Data 0 <--
|
||||
|
||||
OM_A Load 0 <--
|
||||
OM_A Ifetch 0 <--
|
||||
OM_A Store 0 <--
|
||||
OM_A L1_to_L2 0 <--
|
||||
OM_A L2_to_L1D 0 <--
|
||||
OM_A L2_to_L1I 0 <--
|
||||
OM_A L2_Replacement 0 <--
|
||||
OM_A Own_GETX 0 <--
|
||||
OM_A Other_GETS 0 <--
|
||||
OM_A Other_GET_INSTR 0 <--
|
||||
OM_A Other_GETX 0 <--
|
||||
OM_A Other_PUTX 0 <--
|
||||
OM_A Data 0 <--
|
||||
|
||||
IS_A Load 0 <--
|
||||
IS_A Ifetch 0 <--
|
||||
IS_A Store 0 <--
|
||||
IS_A L1_to_L2 0 <--
|
||||
IS_A L2_to_L1D 0 <--
|
||||
IS_A L2_to_L1I 0 <--
|
||||
IS_A L2_Replacement 0 <--
|
||||
IS_A Own_GETS 0 <--
|
||||
IS_A Own_GET_INSTR 0 <--
|
||||
IS_A Other_GETS 0 <--
|
||||
IS_A Other_GET_INSTR 0 <--
|
||||
IS_A Other_GETX 0 <--
|
||||
IS_A Other_PUTX 0 <--
|
||||
|
||||
IM_A Load 0 <--
|
||||
IM_A Ifetch 0 <--
|
||||
IM_A Store 0 <--
|
||||
IM_A L1_to_L2 0 <--
|
||||
IM_A L2_to_L1D 0 <--
|
||||
IM_A L2_to_L1I 0 <--
|
||||
IM_A L2_Replacement 0 <--
|
||||
IM_A Own_GETX 0 <--
|
||||
IM_A Other_GETS 0 <--
|
||||
IM_A Other_GET_INSTR 0 <--
|
||||
IM_A Other_GETX 0 <--
|
||||
IM_A Other_PUTX 0 <--
|
||||
|
||||
SM_A Load 0 <--
|
||||
SM_A Ifetch 0 <--
|
||||
SM_A Store 0 <--
|
||||
SM_A L1_to_L2 0 <--
|
||||
SM_A L2_to_L1D 0 <--
|
||||
SM_A L2_to_L1I 0 <--
|
||||
SM_A L2_Replacement 0 <--
|
||||
SM_A Own_GETX 0 <--
|
||||
SM_A Other_GETS 0 <--
|
||||
SM_A Other_GET_INSTR 0 <--
|
||||
SM_A Other_GETX 0 <--
|
||||
SM_A Other_PUTX 0 <--
|
||||
|
||||
MI_A Load 0 <--
|
||||
MI_A Ifetch 0 <--
|
||||
MI_A Store 0 <--
|
||||
MI_A L1_to_L2 0 <--
|
||||
MI_A L2_to_L1D 0 <--
|
||||
MI_A L2_to_L1I 0 <--
|
||||
MI_A L2_Replacement 0 <--
|
||||
MI_A Own_PUTX 0 <--
|
||||
MI_A Other_GETS 0 <--
|
||||
MI_A Other_GET_INSTR 0 <--
|
||||
MI_A Other_GETX 0 <--
|
||||
MI_A Other_PUTX 0 <--
|
||||
|
||||
OI_A Load 0 <--
|
||||
OI_A Ifetch 0 <--
|
||||
OI_A Store 0 <--
|
||||
OI_A L1_to_L2 0 <--
|
||||
OI_A L2_to_L1D 0 <--
|
||||
OI_A L2_to_L1I 0 <--
|
||||
OI_A L2_Replacement 0 <--
|
||||
OI_A Own_PUTX 0 <--
|
||||
OI_A Other_GETS 0 <--
|
||||
OI_A Other_GET_INSTR 0 <--
|
||||
OI_A Other_GETX 0 <--
|
||||
OI_A Other_PUTX 0 <--
|
||||
|
||||
II_A Load 0 <--
|
||||
II_A Ifetch 0 <--
|
||||
II_A Store 0 <--
|
||||
II_A L1_to_L2 0 <--
|
||||
II_A L2_to_L1D 0 <--
|
||||
II_A L2_to_L1I 0 <--
|
||||
II_A L2_Replacement 0 <--
|
||||
II_A Own_PUTX 0 <--
|
||||
II_A Other_GETS 0 <--
|
||||
II_A Other_GET_INSTR 0 <--
|
||||
II_A Other_GETX 0 <--
|
||||
II_A Other_PUTX 0 <--
|
||||
|
||||
IS_D Load 0 <--
|
||||
IS_D Ifetch 0 <--
|
||||
IS_D Store 0 <--
|
||||
IS_D L1_to_L2 0 <--
|
||||
IS_D L2_to_L1D 0 <--
|
||||
IS_D L2_to_L1I 0 <--
|
||||
IS_D L2_Replacement 0 <--
|
||||
IS_D Other_GETS 0 <--
|
||||
IS_D Other_GET_INSTR 0 <--
|
||||
IS_D Other_GETX 0 <--
|
||||
IS_D Other_PUTX 0 <--
|
||||
IS_D Data 0 <--
|
||||
|
||||
IS_D_I Load 0 <--
|
||||
IS_D_I Ifetch 0 <--
|
||||
IS_D_I Store 0 <--
|
||||
IS_D_I L1_to_L2 0 <--
|
||||
IS_D_I L2_to_L1D 0 <--
|
||||
IS_D_I L2_to_L1I 0 <--
|
||||
IS_D_I L2_Replacement 0 <--
|
||||
IS_D_I Other_GETS 0 <--
|
||||
IS_D_I Other_GET_INSTR 0 <--
|
||||
IS_D_I Other_GETX 0 <--
|
||||
IS_D_I Other_PUTX 0 <--
|
||||
IS_D_I Data 0 <--
|
||||
|
||||
IM_D Load 0 <--
|
||||
IM_D Ifetch 0 <--
|
||||
IM_D Store 0 <--
|
||||
IM_D L1_to_L2 0 <--
|
||||
IM_D L2_to_L1D 0 <--
|
||||
IM_D L2_to_L1I 0 <--
|
||||
IM_D L2_Replacement 0 <--
|
||||
IM_D Other_GETS 0 <--
|
||||
IM_D Other_GET_INSTR 0 <--
|
||||
IM_D Other_GETX 0 <--
|
||||
IM_D Other_PUTX 0 <--
|
||||
IM_D Data 0 <--
|
||||
|
||||
IM_D_O Load 0 <--
|
||||
IM_D_O Ifetch 0 <--
|
||||
IM_D_O Store 0 <--
|
||||
IM_D_O L1_to_L2 0 <--
|
||||
IM_D_O L2_to_L1D 0 <--
|
||||
IM_D_O L2_to_L1I 0 <--
|
||||
IM_D_O L2_Replacement 0 <--
|
||||
IM_D_O Other_GETS 0 <--
|
||||
IM_D_O Other_GET_INSTR 0 <--
|
||||
IM_D_O Other_GETX 0 <--
|
||||
IM_D_O Other_PUTX 0 <--
|
||||
IM_D_O Data 0 <--
|
||||
|
||||
IM_D_I Load 0 <--
|
||||
IM_D_I Ifetch 0 <--
|
||||
IM_D_I Store 0 <--
|
||||
IM_D_I L1_to_L2 0 <--
|
||||
IM_D_I L2_to_L1D 0 <--
|
||||
IM_D_I L2_to_L1I 0 <--
|
||||
IM_D_I L2_Replacement 0 <--
|
||||
IM_D_I Other_GETS 0 <--
|
||||
IM_D_I Other_GET_INSTR 0 <--
|
||||
IM_D_I Other_GETX 0 <--
|
||||
IM_D_I Other_PUTX 0 <--
|
||||
IM_D_I Data 0 <--
|
||||
|
||||
IM_D_OI Load 0 <--
|
||||
IM_D_OI Ifetch 0 <--
|
||||
IM_D_OI Store 0 <--
|
||||
IM_D_OI L1_to_L2 0 <--
|
||||
IM_D_OI L2_to_L1D 0 <--
|
||||
IM_D_OI L2_to_L1I 0 <--
|
||||
IM_D_OI L2_Replacement 0 <--
|
||||
IM_D_OI Other_GETS 0 <--
|
||||
IM_D_OI Other_GET_INSTR 0 <--
|
||||
IM_D_OI Other_GETX 0 <--
|
||||
IM_D_OI Other_PUTX 0 <--
|
||||
IM_D_OI Data 0 <--
|
||||
|
||||
SM_D Load 0 <--
|
||||
SM_D Ifetch 0 <--
|
||||
SM_D Store 0 <--
|
||||
SM_D L1_to_L2 0 <--
|
||||
SM_D L2_to_L1D 0 <--
|
||||
SM_D L2_to_L1I 0 <--
|
||||
SM_D L2_Replacement 0 <--
|
||||
SM_D Other_GETS 0 <--
|
||||
SM_D Other_GET_INSTR 0 <--
|
||||
SM_D Other_GETX 0 <--
|
||||
SM_D Other_PUTX 0 <--
|
||||
SM_D Data 0 <--
|
||||
|
||||
SM_D_O Load 0 <--
|
||||
SM_D_O Ifetch 0 <--
|
||||
SM_D_O Store 0 <--
|
||||
SM_D_O L1_to_L2 0 <--
|
||||
SM_D_O L2_to_L1D 0 <--
|
||||
SM_D_O L2_to_L1I 0 <--
|
||||
SM_D_O L2_Replacement 0 <--
|
||||
SM_D_O Other_GETS 0 <--
|
||||
SM_D_O Other_GET_INSTR 0 <--
|
||||
SM_D_O Other_GETX 0 <--
|
||||
SM_D_O Other_PUTX 0 <--
|
||||
SM_D_O Data 0 <--
|
||||
|
||||
--- Directory ---
|
||||
- Event Counts -
|
||||
OtherAddress 0
|
||||
GETS 0
|
||||
GET_INSTR 0
|
||||
GETX 0
|
||||
PUTX_Owner 0
|
||||
PUTX_NotOwner 0
|
||||
|
||||
- Transitions -
|
||||
C OtherAddress 0 <--
|
||||
C GETS 0 <--
|
||||
C GET_INSTR 0 <--
|
||||
C GETX 0 <--
|
||||
|
||||
I GETS 0 <--
|
||||
I GET_INSTR 0 <--
|
||||
I GETX 0 <--
|
||||
I PUTX_NotOwner 0 <--
|
||||
|
||||
S GETS 0 <--
|
||||
S GET_INSTR 0 <--
|
||||
S GETX 0 <--
|
||||
S PUTX_NotOwner 0 <--
|
||||
|
||||
SS GETS 0 <--
|
||||
SS GET_INSTR 0 <--
|
||||
SS GETX 0 <--
|
||||
SS PUTX_NotOwner 0 <--
|
||||
|
||||
OS GETS 0 <--
|
||||
OS GET_INSTR 0 <--
|
||||
OS GETX 0 <--
|
||||
OS PUTX_Owner 0 <--
|
||||
OS PUTX_NotOwner 0 <--
|
||||
|
||||
OSS GETS 0 <--
|
||||
OSS GET_INSTR 0 <--
|
||||
OSS GETX 0 <--
|
||||
OSS PUTX_Owner 0 <--
|
||||
OSS PUTX_NotOwner 0 <--
|
||||
|
||||
M GETS 0 <--
|
||||
M GET_INSTR 0 <--
|
||||
M GETX 0 <--
|
||||
M PUTX_Owner 0 <--
|
||||
M PUTX_NotOwner 0 <--
|
||||
|
||||
|
|
@ -1,41 +0,0 @@
|
|||
["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "4", "-m", "1", "-s", "1024"]
|
||||
print config: 1
|
||||
Creating new MessageBuffer for 0 0
|
||||
Creating new MessageBuffer for 0 1
|
||||
Creating new MessageBuffer for 0 2
|
||||
Creating new MessageBuffer for 0 3
|
||||
Creating new MessageBuffer for 0 4
|
||||
Creating new MessageBuffer for 0 5
|
||||
Creating new MessageBuffer for 1 0
|
||||
Creating new MessageBuffer for 1 1
|
||||
Creating new MessageBuffer for 1 2
|
||||
Creating new MessageBuffer for 1 3
|
||||
Creating new MessageBuffer for 1 4
|
||||
Creating new MessageBuffer for 1 5
|
||||
Creating new MessageBuffer for 2 0
|
||||
Creating new MessageBuffer for 2 1
|
||||
Creating new MessageBuffer for 2 2
|
||||
Creating new MessageBuffer for 2 3
|
||||
Creating new MessageBuffer for 2 4
|
||||
Creating new MessageBuffer for 2 5
|
||||
Creating new MessageBuffer for 3 0
|
||||
Creating new MessageBuffer for 3 1
|
||||
Creating new MessageBuffer for 3 2
|
||||
Creating new MessageBuffer for 3 3
|
||||
Creating new MessageBuffer for 3 4
|
||||
Creating new MessageBuffer for 3 5
|
||||
Creating new MessageBuffer for 4 0
|
||||
Creating new MessageBuffer for 4 1
|
||||
Creating new MessageBuffer for 4 2
|
||||
Creating new MessageBuffer for 4 3
|
||||
Creating new MessageBuffer for 4 4
|
||||
Creating new MessageBuffer for 4 5
|
||||
Creating new MessageBuffer for 5 0
|
||||
Creating new MessageBuffer for 5 1
|
||||
Creating new MessageBuffer for 5 2
|
||||
Creating new MessageBuffer for 5 3
|
||||
Creating new MessageBuffer for 5 4
|
||||
Creating new MessageBuffer for 5 5
|
||||
warn: Sockets disabled, not accepting gdb connections
|
||||
For more information see: http://www.m5sim.org/warn/d946bea6
|
||||
hack: be nice to actually delete the event here
|
||||
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue