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types: add a type for thread IDs and try to use it everywhere

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This commit is contained in:
Nathan Binkert 2009-05-26 09:23:13 -07:00
parent d93392df28
commit 47877cf2db
107 changed files with 1595 additions and 1534 deletions
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8
src/arch/alpha/miscregfile.cc
View file

@ -65,7 +65,7 @@ MiscRegFile::MiscRegFile(BaseCPU *_cpu)
MiscReg
MiscRegFile::readRegNoEffect(int misc_reg, unsigned tid )
MiscRegFile::readRegNoEffect(int misc_reg, ThreadID tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
@ -85,7 +85,7 @@ MiscRegFile::readRegNoEffect(int misc_reg, unsigned tid )
}
MiscReg
MiscRegFile::readReg(int misc_reg, ThreadContext *tc, unsigned tid )
MiscRegFile::readReg(int misc_reg, ThreadContext *tc, ThreadID tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
@ -104,7 +104,7 @@ MiscRegFile::readReg(int misc_reg, ThreadContext *tc, unsigned tid )
}
void
MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid)
MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
@ -131,7 +131,7 @@ MiscRegFile::setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid)
void
MiscRegFile::setReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
unsigned tid)
ThreadID tid)
{
switch (misc_reg) {
case MISCREG_FPCR:

13
src/arch/alpha/miscregfile.hh
View file

@ -88,11 +88,12 @@ class MiscRegFile
int getInstAsid();
int getDataAsid();
MiscReg readRegNoEffect(int misc_reg, unsigned tid = 0);
MiscReg readReg(int misc_reg, ThreadContext *tc, unsigned tid = 0);
MiscReg readRegNoEffect(int misc_reg, ThreadID tid = 0);
MiscReg readReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
void setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0);
void setReg(int misc_reg, const MiscReg &val, ThreadContext *tc, unsigned tid = 0);
void setRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0);
void setReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
ThreadID tid = 0);
void
clear()
@ -107,12 +108,12 @@ class MiscRegFile
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
void reset(std::string core_name, unsigned num_threads,
void reset(std::string core_name, ThreadID num_threads,
unsigned num_vpes, BaseCPU *_cpu)
{ }
void expandForMultithreading(unsigned num_threads, unsigned num_vpes)
void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
{ }

6
src/arch/mips/mt.hh
View file

@ -109,7 +109,7 @@ forkThread(TC *tc, Fault &fault, int Rd_bits, int Rs, int Rt)
int num_threads = bits(tc->readMiscRegNoEffect(MVPConf0), MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
int success = 0;
for (int tid = 0; tid < num_threads && success == 0; tid++) {
for (ThreadID tid = 0; tid < num_threads && success == 0; tid++) {
unsigned tid_TCBind = tc->readRegOtherThread(MipsISA::TCBind + Ctrl_Base_DepTag,
tid);
unsigned tc_bind = tc->readMiscRegNoEffect(MipsISA::TCBind);
@ -181,7 +181,7 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
{
if (src_reg == 0) {
unsigned mvpconf0 = tc->readMiscRegNoEffect(MVPConf0);
int num_threads = bits(mvpconf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
ThreadID num_threads = bits(mvpconf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
int ok = 0;
@ -190,7 +190,7 @@ yieldThread(TC *tc, Fault &fault, int src_reg, uint32_t yield_mask)
unsigned cur_vpe = bits(tcbind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
unsigned cur_tc = bits(tcbind, TCB_CUR_TC_HI, TCB_CUR_TC_LO);
for (int tid = 0; tid < num_threads; tid++) {
for (ThreadID tid = 0; tid < num_threads; tid++) {
unsigned tid_TCStatus = tc->readRegOtherThread(MipsISA::TCStatus + Ctrl_Base_DepTag,
tid);
unsigned tid_TCHalt = tc->readRegOtherThread(MipsISA::TCHalt + Ctrl_Base_DepTag,

19
src/arch/mips/regfile.cc
View file

@ -54,7 +54,9 @@ void RegFile::clear()
miscRegFile.clear();
}
void RegFile::reset(std::string core_name, unsigned num_threads, unsigned num_vpes)
void
RegFile::reset(std::string core_name, ThreadID num_threads,
unsigned num_vpes)
{
bzero(&intRegFile, sizeof(intRegFile));
bzero(&floatRegFile, sizeof(floatRegFile));
@ -71,24 +73,27 @@ Fault RegFile::setIntReg(int intReg, const IntReg &val)
return intRegFile.setReg(intReg, val);
}
MiscReg RegFile::readMiscRegNoEffect(int miscReg, unsigned tid = 0)
MiscReg
RegFile::readMiscRegNoEffect(int miscReg, ThreadID tid = 0)
{
return miscRegFile.readRegNoEffect(miscReg, tid);
}
MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc,
unsigned tid = 0)
MiscReg
RegFile::readMiscReg(int miscReg, ThreadContext *tc, ThreadID tid = 0)
{
return miscRegFile.readReg(miscReg, tc, tid);
}
void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val, unsigned tid = 0)
void
RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val, ThreadID tid = 0)
{
miscRegFile.setRegNoEffect(miscReg, val, tid);
}
void RegFile::setMiscReg(int miscReg, const MiscReg &val,
ThreadContext * tc, unsigned tid = 0)
void
RegFile::setMiscReg(int miscReg, const MiscReg &val,
ThreadContext *tc, ThreadID tid = 0)
{
miscRegFile.setReg(miscReg, val, tc, tid);
}

13
src/arch/mips/regfile/float_regfile.cc
View file

@ -42,7 +42,7 @@ FloatRegFile::clear()
}
double
FloatRegFile::readReg(int floatReg, int width, unsigned tid)
FloatRegFile::readReg(int floatReg, int width, ThreadID tid)
{
switch(width)
{
@ -65,7 +65,7 @@ FloatRegFile::readReg(int floatReg, int width, unsigned tid)
}
FloatRegBits
FloatRegFile::readRegBits(int floatReg, int width, unsigned tid)
FloatRegFile::readRegBits(int floatReg, int width, ThreadID tid)
{
if (floatReg < NumFloatArchRegs - 1) {
switch(width)
@ -88,9 +88,9 @@ FloatRegFile::readRegBits(int floatReg, int width, unsigned tid)
}
Fault
FloatRegFile::setReg(int floatReg, const FloatRegVal &val, int width, unsigned tid)
FloatRegFile::setReg(int floatReg, const FloatRegVal &val, int width,
ThreadID tid)
{
using namespace std;
switch(width)
{
case SingleWidth:
@ -118,10 +118,9 @@ FloatRegFile::setReg(int floatReg, const FloatRegVal &val, int width, unsigned t
}
Fault
FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width, unsigned tid)
FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width,
ThreadID tid)
{
using namespace std;
switch(width)
{
case SingleWidth:

10
src/arch/mips/regfile/float_regfile.hh
View file

@ -88,10 +88,12 @@ namespace MipsISA
static const int regWidth = SingleWidth;
void clear();
double readReg(int floatReg, int width, unsigned tid = 0);
FloatRegBits readRegBits(int floatReg, int width, unsigned tid = 0);
Fault setReg(int floatReg, const FloatRegVal &val, int width, unsigned tid = 0);
Fault setRegBits(int floatReg, const FloatRegBits &val, int width, unsigned tid = 0);
double readReg(int floatReg, int width, ThreadID tid = 0);
FloatRegBits readRegBits(int floatReg, int width, ThreadID tid = 0);
Fault setReg(int floatReg, const FloatRegVal &val, int width,
ThreadID tid = 0);
Fault setRegBits(int floatReg, const FloatRegBits &val, int width,
ThreadID tid = 0);
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);

27
src/arch/mips/regfile/misc_regfile.cc
View file

@ -131,7 +131,7 @@ MiscRegFile::clear(unsigned tid_or_vpn)
}
void
MiscRegFile::expandForMultithreading(unsigned num_threads, unsigned num_vpes)
MiscRegFile::expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
{
// Initialize all Per-VPE regs
uint32_t per_vpe_regs[] = { VPEControl, VPEConf0, VPEConf1, YQMask,
@ -180,7 +180,7 @@ int MiscRegFile:: getDataAsid()
}
//@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H)
void
MiscRegFile::reset(std::string core_name, unsigned num_threads,
MiscRegFile::reset(std::string core_name, ThreadID num_threads,
unsigned num_vpes, BaseCPU *_cpu)
{
DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
@ -378,7 +378,7 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
setRegNoEffect(VPEConf0, vpe_conf0);
// TCBind
for (int tid = 0; tid < num_threads; tid++) {
for (ThreadID tid = 0; tid < num_threads; tid++) {
MiscReg tc_bind = readRegNoEffect(TCBind, tid);
replaceBits(tc_bind, TCB_CUR_TC_HI, TCB_CUR_TC_LO, tid);
setRegNoEffect(TCBind, tc_bind, tid);
@ -387,7 +387,7 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
MiscReg tc_halt = readRegNoEffect(TCHalt);
replaceBits(tc_halt, TCH_H, 0);
setRegNoEffect(TCHalt, tc_halt);
/*for (int tid = 1; tid < num_threads; tid++) {
/*for (ThreadID tid = 1; tid < num_threads; tid++) {
// Set TCHalt Halt bit to 1 for all other threads
tc_halt = readRegNoEffect(TCHalt, tid);
replaceBits(tc_halt, TCH_H, 1);
@ -401,7 +401,7 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
setRegNoEffect(TCStatus, tc_status);
// Set Dynamically Allocatable bit to 1 for all other threads
for (int tid = 1; tid < num_threads; tid++) {
for (ThreadID tid = 1; tid < num_threads; tid++) {
tc_status = readRegNoEffect(TCStatus, tid);
replaceBits(tc_status, TCSTATUS_DA, 1);
setRegNoEffect(TCStatus, tc_status, tid);
@ -439,14 +439,14 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
}
inline unsigned
MiscRegFile::getVPENum(unsigned tid)
MiscRegFile::getVPENum(ThreadID tid)
{
unsigned tc_bind = miscRegFile[TCBind - Ctrl_Base_DepTag][tid];
return bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO);
}
MiscReg
MiscRegFile::readRegNoEffect(int reg_idx, unsigned tid)
MiscRegFile::readRegNoEffect(int reg_idx, ThreadID tid)
{
int misc_reg = reg_idx - Ctrl_Base_DepTag;
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
@ -461,8 +461,7 @@ MiscRegFile::readRegNoEffect(int reg_idx, unsigned tid)
// Status to TCStatus depending on current thread
//template <class TC>
MiscReg
MiscRegFile::readReg(int reg_idx,
ThreadContext *tc, unsigned tid)
MiscRegFile::readReg(int reg_idx, ThreadContext *tc, ThreadID tid)
{
int misc_reg = reg_idx - Ctrl_Base_DepTag;
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
@ -481,7 +480,7 @@ MiscRegFile::readReg(int reg_idx,
}
void
MiscRegFile::setRegNoEffect(int reg_idx, const MiscReg &val, unsigned tid)
MiscRegFile::setRegNoEffect(int reg_idx, const MiscReg &val, ThreadID tid)
{
int misc_reg = reg_idx - Ctrl_Base_DepTag;
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
@ -494,7 +493,7 @@ MiscRegFile::setRegNoEffect(int reg_idx, const MiscReg &val, unsigned tid)
miscRegFile[misc_reg][reg_sel] = val;
}
void
MiscRegFile::setRegMask(int reg_idx, const MiscReg &val, unsigned tid)
MiscRegFile::setRegMask(int reg_idx, const MiscReg &val, ThreadID tid)
{
// return;
int misc_reg = reg_idx - Ctrl_Base_DepTag;
@ -513,7 +512,7 @@ MiscRegFile::setRegMask(int reg_idx, const MiscReg &val, unsigned tid)
//template <class TC>
void
MiscRegFile::setReg(int reg_idx, const MiscReg &val,
ThreadContext *tc, unsigned tid)
ThreadContext *tc, ThreadID tid)
{
int misc_reg = reg_idx - Ctrl_Base_DepTag;
int reg_sel = (bankType[misc_reg] == perThreadContext)
@ -575,9 +574,9 @@ MiscRegFile::updateCPU()
//
///////////////////////////////////////////////////////////////////
unsigned mvp_conf0 = readRegNoEffect(MVPConf0);
unsigned num_threads = bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
ThreadID num_threads = bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO) + 1;
for (int tid = 0; tid < num_threads; tid++) {
for (ThreadID tid = 0; tid < num_threads; tid++) {
MiscReg tc_status = readRegNoEffect(TCStatus, tid);
MiscReg tc_halt = readRegNoEffect(TCHalt, tid);

18
src/arch/mips/regfile/misc_regfile.hh
View file

@ -75,12 +75,12 @@ namespace MipsISA
void clear(unsigned tid_or_vpn = 0);
void reset(std::string core_name, unsigned num_threads,
void reset(std::string core_name, ThreadID num_threads,
unsigned num_vpes, BaseCPU *_cpu);
void expandForMultithreading(unsigned num_threads, unsigned num_vpes);
void expandForMultithreading(ThreadID num_threads, unsigned num_vpes);
inline unsigned getVPENum(unsigned tid);
unsigned getVPENum(ThreadID tid);
//////////////////////////////////////////////////////////
//
@ -90,21 +90,21 @@ namespace MipsISA
//////////////////////////////////////////////////////////
//@TODO: MIPS MT's register view automatically connects
// Status to TCStatus depending on current thread
void updateCP0ReadView(int misc_reg, unsigned tid) { }
MiscReg readRegNoEffect(int misc_reg, unsigned tid = 0);
void updateCP0ReadView(int misc_reg, ThreadID tid) { }
MiscReg readRegNoEffect(int misc_reg, ThreadID tid = 0);
//template <class TC>
MiscReg readReg(int misc_reg,
ThreadContext *tc, unsigned tid = 0);
ThreadContext *tc, ThreadID tid = 0);
MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val);
void setRegMask(int misc_reg, const MiscReg &val, unsigned tid = 0);
void setRegMask(int misc_reg, const MiscReg &val, ThreadID tid = 0);
void setRegNoEffect(int misc_reg, const MiscReg &val,
unsigned tid = 0);
ThreadID tid = 0);
//template <class TC>
void setReg(int misc_reg, const MiscReg &val,
ThreadContext *tc, unsigned tid = 0);
ThreadContext *tc, ThreadID tid = 0);
int getInstAsid();
int getDataAsid();

12
src/arch/mips/regfile/regfile.cc
View file

@ -46,7 +46,8 @@ RegFile::clear()
}
void
RegFile::reset(std::string core_name, unsigned num_threads, unsigned num_vpes, BaseCPU *_cpu)
RegFile::reset(std::string core_name, ThreadID num_threads, unsigned num_vpes,
BaseCPU *_cpu)
{
bzero(&intRegFile, sizeof(intRegFile));
bzero(&floatRegFile, sizeof(floatRegFile));
@ -66,27 +67,26 @@ RegFile::setIntReg(int intReg, const IntReg &val)
}
MiscReg
RegFile::readMiscRegNoEffect(int miscReg, unsigned tid)
RegFile::readMiscRegNoEffect(int miscReg, ThreadID tid)
{
return miscRegFile.readRegNoEffect(miscReg, tid);
}
MiscReg
RegFile::readMiscReg(int miscReg, ThreadContext *tc,
unsigned tid)
RegFile::readMiscReg(int miscReg, ThreadContext *tc, ThreadID tid)
{
return miscRegFile.readReg(miscReg, tc, tid);
}
void
RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val, unsigned tid)
RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val, ThreadID tid)
{
miscRegFile.setRegNoEffect(miscReg, val, tid);
}
void
RegFile::setMiscReg(int miscReg, const MiscReg &val,
ThreadContext * tc, unsigned tid)
ThreadContext *tc, ThreadID tid)
{
miscRegFile.setReg(miscReg, val, tc, tid);
}

12
src/arch/mips/regfile/regfile.hh
View file

@ -61,19 +61,21 @@ namespace MipsISA
public:
void clear();
void reset(std::string core_name, unsigned num_threads, unsigned num_vpes, BaseCPU *_cpu);
void reset(std::string core_name, ThreadID num_threads,
unsigned num_vpes, BaseCPU *_cpu);
MiscRegFile *getMiscRegFilePtr();
IntReg readIntReg(int intReg);
Fault setIntReg(int intReg, const IntReg &val);
MiscReg readMiscRegNoEffect(int miscReg, unsigned tid = 0);
MiscReg readMiscRegNoEffect(int miscReg, ThreadID tid = 0);
MiscReg readMiscReg(int miscReg, ThreadContext *tc,
unsigned tid = 0);
void setMiscRegNoEffect(int miscReg, const MiscReg &val, unsigned tid = 0);
ThreadID tid = 0);
void setMiscRegNoEffect(int miscReg, const MiscReg &val,
ThreadID tid = 0);
void setMiscReg(int miscReg, const MiscReg &val,
ThreadContext * tc, unsigned tid = 0);
ThreadContext *tc, ThreadID tid = 0);
FloatRegVal readFloatReg(int floatReg);
FloatRegVal readFloatReg(int floatReg, int width);

6
src/base/types.hh
View file

@ -68,4 +68,10 @@ typedef uint64_t Addr;
const Addr MaxAddr = (Addr)-1;
/**
* Thread index/ID type
*/
typedef int16_t ThreadID;
const ThreadID InvalidThreadID = (ThreadID)-1;
#endif // __BASE_TYPES_HH__

63
src/cpu/base.cc
View file

@ -100,12 +100,12 @@ CPUProgressEvent::description() const
BaseCPU::BaseCPU(Params *p)
: MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
interrupts(p->interrupts),
number_of_threads(p->numThreads), system(p->system),
numThreads(p->numThreads), system(p->system),
phase(p->phase)
#else
BaseCPU::BaseCPU(Params *p)
: MemObject(p), clock(p->clock), _cpuId(p->cpu_id),
number_of_threads(p->numThreads), system(p->system),
numThreads(p->numThreads), system(p->system),
phase(p->phase)
#endif
{
@ -121,22 +121,23 @@ BaseCPU::BaseCPU(Params *p)
DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId);
if (number_of_threads > maxThreadsPerCPU)
maxThreadsPerCPU = number_of_threads;
if (numThreads > maxThreadsPerCPU)
maxThreadsPerCPU = numThreads;
// allocate per-thread instruction-based event queues
comInstEventQueue = new EventQueue *[number_of_threads];
for (int i = 0; i < number_of_threads; ++i)
comInstEventQueue[i] = new EventQueue("instruction-based event queue");
comInstEventQueue = new EventQueue *[numThreads];
for (ThreadID tid = 0; tid < numThreads; ++tid)
comInstEventQueue[tid] =
new EventQueue("instruction-based event queue");
//
// set up instruction-count-based termination events, if any
//
if (p->max_insts_any_thread != 0) {
const char *cause = "a thread reached the max instruction count";
for (int i = 0; i < number_of_threads; ++i) {
for (ThreadID tid = 0; tid < numThreads; ++tid) {
Event *event = new SimLoopExitEvent(cause, 0);
comInstEventQueue[i]->schedule(event, p->max_insts_any_thread);
comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread);
}
}
@ -147,26 +148,26 @@ BaseCPU::BaseCPU(Params *p)
// decrement this when triggered; simulation will terminate
// when counter reaches 0
int *counter = new int;
*counter = number_of_threads;
for (int i = 0; i < number_of_threads; ++i) {
*counter = numThreads;
for (ThreadID tid = 0; tid < numThreads; ++tid) {
Event *event = new CountedExitEvent(cause, *counter);
comInstEventQueue[i]->schedule(event, p->max_insts_any_thread);
comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread);
}
}
// allocate per-thread load-based event queues
comLoadEventQueue = new EventQueue *[number_of_threads];
for (int i = 0; i < number_of_threads; ++i)
comLoadEventQueue[i] = new EventQueue("load-based event queue");
comLoadEventQueue = new EventQueue *[numThreads];
for (ThreadID tid = 0; tid < numThreads; ++tid)
comLoadEventQueue[tid] = new EventQueue("load-based event queue");
//
// set up instruction-count-based termination events, if any
//
if (p->max_loads_any_thread != 0) {
const char *cause = "a thread reached the max load count";
for (int i = 0; i < number_of_threads; ++i) {
for (ThreadID tid = 0; tid < numThreads; ++tid) {
Event *event = new SimLoopExitEvent(cause, 0);
comLoadEventQueue[i]->schedule(event, p->max_loads_any_thread);
comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread);
}
}
@ -176,10 +177,10 @@ BaseCPU::BaseCPU(Params *p)
// decrement this when triggered; simulation will terminate
// when counter reaches 0
int *counter = new int;
*counter = number_of_threads;
for (int i = 0; i < number_of_threads; ++i) {
*counter = numThreads;
for (ThreadID tid = 0; tid < numThreads; ++tid) {
Event *event = new CountedExitEvent(cause, *counter);
comLoadEventQueue[i]->schedule(event, p->max_loads_all_threads);
comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads);
}
}
@ -289,8 +290,9 @@ BaseCPU::nextCycle(Tick begin_tick)
void
BaseCPU::registerThreadContexts()
{
for (int i = 0; i < threadContexts.size(); ++i) {
ThreadContext *tc = threadContexts[i];
ThreadID size = threadContexts.size();
for (ThreadID tid = 0; tid < size; ++tid) {
ThreadContext *tc = threadContexts[tid];
/** This is so that contextId and cpuId match where there is a
* 1cpu:1context relationship. Otherwise, the order of registration
@ -299,7 +301,7 @@ BaseCPU::registerThreadContexts()
* cpu 0 has the lowest thread contexts and cpu N has the highest, but
* I'll just do this for now
*/
if (number_of_threads == 1)
if (numThreads == 1)
tc->setContextId(system->registerThreadContext(tc, _cpuId));
else
tc->setContextId(system->registerThreadContext(tc));
@ -313,9 +315,10 @@ BaseCPU::registerThreadContexts()
int
BaseCPU::findContext(ThreadContext *tc)
{
for (int i = 0; i < threadContexts.size(); ++i) {
if (tc == threadContexts[i])
return i;
ThreadID size = threadContexts.size();
for (ThreadID tid = 0; tid < size; ++tid) {
if (tc == threadContexts[tid])
return tid;
}
return 0;
}
@ -337,7 +340,8 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
_cpuId = oldCPU->cpuId();
for (int i = 0; i < threadContexts.size(); ++i) {
ThreadID size = threadContexts.size();
for (ThreadID i = 0; i < size; ++i) {
ThreadContext *newTC = threadContexts[i];
ThreadContext *oldTC = oldCPU->threadContexts[i];
@ -361,7 +365,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
interrupts = oldCPU->interrupts;
interrupts->setCPU(this);
for (int i = 0; i < threadContexts.size(); ++i)
for (ThreadID i = 0; i < size; ++i)
threadContexts[i]->profileClear();
if (profileEvent)
@ -393,7 +397,8 @@ BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
void
BaseCPU::ProfileEvent::process()
{
for (int i = 0, size = cpu->threadContexts.size(); i < size; ++i) {
ThreadID size = cpu->threadContexts.size();
for (ThreadID i = 0; i < size; ++i) {
ThreadContext *tc = cpu->threadContexts[i];
tc->profileSample();
}

4
src/cpu/base.hh
View file

@ -213,7 +213,7 @@ class BaseCPU : public MemObject
virtual void startup();
virtual void regStats();
virtual void activateWhenReady(int tid) {};
virtual void activateWhenReady(ThreadID tid) {};
void registerThreadContexts();
@ -229,7 +229,7 @@ class BaseCPU : public MemObject
* Number of threads we're actually simulating (<= SMT_MAX_THREADS).
* This is a constant for the duration of the simulation.
*/
int number_of_threads;
ThreadID numThreads;
TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core

4
src/cpu/base_dyn_inst.hh
View file

@ -168,7 +168,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
std::bitset<NumStatus> status;
/** The thread this instruction is from. */
short threadNumber;
ThreadID threadNumber;
/** data address space ID, for loads & stores. */
short asid;
@ -778,7 +778,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
void setASID(short addr_space_id) { asid = addr_space_id; }
/** Sets the thread id. */
void setTid(unsigned tid) { threadNumber = tid; }
void setTid(ThreadID tid) { threadNumber = tid; }
/** Sets the pointer to the thread state. */
void setThreadState(ImplState *state) { thread = state; }

6
src/cpu/btb.cc
View file

@ -82,7 +82,7 @@ DefaultBTB::getTag(const Addr &inst_PC)
}
bool
DefaultBTB::valid(const Addr &inst_PC, unsigned tid)
DefaultBTB::valid(const Addr &inst_PC, ThreadID tid)
{
unsigned btb_idx = getIndex(inst_PC);
@ -103,7 +103,7 @@ DefaultBTB::valid(const Addr &inst_PC, unsigned tid)
// address is valid, and also the address. For now will just use addr = 0 to
// represent invalid entry.
Addr
DefaultBTB::lookup(const Addr &inst_PC, unsigned tid)
DefaultBTB::lookup(const Addr &inst_PC, ThreadID tid)
{
unsigned btb_idx = getIndex(inst_PC);
@ -121,7 +121,7 @@ DefaultBTB::lookup(const Addr &inst_PC, unsigned tid)
}
void
DefaultBTB::update(const Addr &inst_PC, const Addr &target, unsigned tid)
DefaultBTB::update(const Addr &inst_PC, const Addr &target, ThreadID tid)
{
unsigned btb_idx = getIndex(inst_PC);

193
src/cpu/inorder/cpu.cc
View file

@ -29,9 +29,10 @@
*
*/
#include "config/full_system.hh"
#include <algorithm>
#include "arch/utility.hh"
#include "config/full_system.hh"
#include "cpu/exetrace.hh"
#include "cpu/activity.hh"
#include "cpu/simple_thread.hh"
@ -49,7 +50,6 @@
#include "mem/translating_port.hh"
#include "sim/process.hh"
#include "sim/stat_control.hh"
#include <algorithm>
using namespace std;
using namespace TheISA;
@ -74,7 +74,7 @@ InOrderCPU::TickEvent::description()
}
InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
Fault fault, unsigned _tid, unsigned _vpe)
Fault fault, ThreadID _tid, unsigned _vpe)
: Event(CPU_Tick_Pri), cpu(_cpu)
{
setEvent(e_type, fault, _tid, _vpe);
@ -175,7 +175,6 @@ InOrderCPU::InOrderCPU(Params *params)
switchCount(0),
deferRegistration(false/*params->deferRegistration*/),
stageTracing(params->stageTracing),
numThreads(params->numThreads),
numVirtProcs(1)
{
cpu_params = params;
@ -204,28 +203,28 @@ InOrderCPU::InOrderCPU(Params *params)
fatal("Unable to find port for data.\n");
}
for (int i = 0; i < numThreads; ++i) {
if (i < params->workload.size()) {
for (ThreadID tid = 0; tid < numThreads; ++tid) {
if (tid < params->workload.size()) {
DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
i, this->thread[i]);
this->thread[i] = new Thread(this, i, params->workload[i],
i);
tid, this->thread[tid]);
this->thread[tid] =
new Thread(this, tid, params->workload[tid], tid);
} else {
//Allocate Empty thread so M5 can use later
//when scheduling threads to CPU
Process* dummy_proc = params->workload[0];
this->thread[i] = new Thread(this, i, dummy_proc, i);
this->thread[tid] = new Thread(this, tid, dummy_proc, tid);
}
// Setup the TC that will serve as the interface to the threads/CPU.
InOrderThreadContext *tc = new InOrderThreadContext;
tc->cpu = this;
tc->thread = this->thread[i];
tc->thread = thread[tid];
// Give the thread the TC.
thread[i]->tc = tc;
thread[i]->setFuncExeInst(0);
globalSeqNum[i] = 1;
thread[tid]->tc = tc;
thread[tid]->setFuncExeInst(0);
globalSeqNum[tid] = 1;
// Add the TC to the CPU's list of TC's.
this->threadContexts.push_back(tc);
@ -257,7 +256,7 @@ InOrderCPU::InOrderCPU(Params *params)
}
// Initialize thread specific variables
for (int tid=0; tid < numThreads; tid++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
archRegDepMap[tid].setCPU(this);
nonSpecInstActive[tid] = false;
@ -434,19 +433,19 @@ InOrderCPU::init()
// Set inSyscall so that the CPU doesn't squash when initially
// setting up registers.
for (int i = 0; i < number_of_threads; ++i)
thread[i]->inSyscall = true;
for (ThreadID tid = 0; tid < numThreads; ++tid)
thread[tid]->inSyscall = true;
#if FULL_SYSTEM
for (int tid=0; tid < number_of_threads; tid++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
ThreadContext *src_tc = threadContexts[tid];
TheISA::initCPU(src_tc, src_tc->contextId());
}
#endif
// Clear inSyscall.
for (int i = 0; i < number_of_threads; ++i)
thread[i]->inSyscall = false;
for (ThreadID tid = 0; tid < numThreads; ++tid)
thread[tid]->inSyscall = false;
// Call Initializiation Routine for Resource Pool
resPool->init();
@ -472,21 +471,21 @@ InOrderCPU::getPort(const std::string &if_name, int idx)
}
void
InOrderCPU::trap(Fault fault, unsigned tid, int delay)
InOrderCPU::trap(Fault fault, ThreadID tid, int delay)
{
//@ Squash Pipeline during TRAP
scheduleCpuEvent(Trap, fault, tid, 0/*vpe*/, delay);
}
void
InOrderCPU::trapCPU(Fault fault, unsigned tid)
InOrderCPU::trapCPU(Fault fault, ThreadID tid)
{
fault->invoke(tcBase(tid));
}
void
InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
unsigned tid, unsigned vpe, unsigned delay)
ThreadID tid, unsigned vpe, unsigned delay)
{
CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, vpe);
@ -500,26 +499,27 @@ InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
}
// Broadcast event to the Resource Pool
DynInstPtr dummy_inst = new InOrderDynInst(this, NULL, getNextEventNum(), tid);
DynInstPtr dummy_inst =
new InOrderDynInst(this, NULL, getNextEventNum(), tid);
resPool->scheduleEvent(c_event, dummy_inst, 0, 0, tid);
}
inline bool
InOrderCPU::isThreadActive(unsigned tid)
InOrderCPU::isThreadActive(ThreadID tid)
{
list<unsigned>::iterator isActive = std::find(
activeThreads.begin(), activeThreads.end(), tid);
list<ThreadID>::iterator isActive =
std::find(activeThreads.begin(), activeThreads.end(), tid);
return (isActive != activeThreads.end());
}
void
InOrderCPU::activateThread(unsigned tid)
InOrderCPU::activateThread(ThreadID tid)
{
if (!isThreadActive(tid)) {
DPRINTF(InOrderCPU, "Adding Thread %i to active threads list in CPU.\n",
tid);
DPRINTF(InOrderCPU,
"Adding Thread %i to active threads list in CPU.\n", tid);
activeThreads.push_back(tid);
wakeCPU();
@ -527,15 +527,15 @@ InOrderCPU::activateThread(unsigned tid)
}
void
InOrderCPU::deactivateThread(unsigned tid)
InOrderCPU::deactivateThread(ThreadID tid)
{
DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
if (isThreadActive(tid)) {
DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
tid);
list<unsigned>::iterator thread_it = std::find(activeThreads.begin(),
activeThreads.end(), tid);
list<ThreadID>::iterator thread_it =
std::find(activeThreads.begin(), activeThreads.end(), tid);
removePipelineStalls(*thread_it);
@ -546,7 +546,7 @@ InOrderCPU::deactivateThread(unsigned tid)
}
void
InOrderCPU::removePipelineStalls(unsigned tid)
InOrderCPU::removePipelineStalls(ThreadID tid)
{
DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
tid);
@ -557,16 +557,16 @@ InOrderCPU::removePipelineStalls(unsigned tid)
}
bool
InOrderCPU::isThreadInCPU(unsigned tid)
InOrderCPU::isThreadInCPU(ThreadID tid)
{
list<unsigned>::iterator isCurrent = std::find(
currentThreads.begin(), currentThreads.end(), tid);
list<ThreadID>::iterator isCurrent =
std::find(currentThreads.begin(), currentThreads.end(), tid);
return (isCurrent != currentThreads.end());
}
void
InOrderCPU::addToCurrentThreads(unsigned tid)
InOrderCPU::addToCurrentThreads(ThreadID tid)
{
if (!isThreadInCPU(tid)) {
DPRINTF(InOrderCPU, "Adding Thread %i to current threads list in CPU.\n",
@ -576,22 +576,22 @@ InOrderCPU::addToCurrentThreads(unsigned tid)
}
void
InOrderCPU::removeFromCurrentThreads(unsigned tid)
InOrderCPU::removeFromCurrentThreads(ThreadID tid)
{
if (isThreadInCPU(tid)) {
DPRINTF(InOrderCPU, "Adding Thread %i to current threads list in CPU.\n",
tid);
list<unsigned>::iterator isCurrent = std::find(
currentThreads.begin(), currentThreads.end(), tid);
DPRINTF(InOrderCPU,
"Adding Thread %i to current threads list in CPU.\n", tid);
list<ThreadID>::iterator isCurrent =
std::find(currentThreads.begin(), currentThreads.end(), tid);
currentThreads.erase(isCurrent);
}
}
bool
InOrderCPU::isThreadSuspended(unsigned tid)
InOrderCPU::isThreadSuspended(ThreadID tid)
{
list<unsigned>::iterator isSuspended = std::find(
suspendedThreads.begin(), suspendedThreads.end(), tid);
list<ThreadID>::iterator isSuspended =
std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
return (isSuspended!= suspendedThreads.end());
}
@ -612,7 +612,7 @@ InOrderCPU::enableVPEs(unsigned vpe)
DPRINTF(InOrderCPU, "[vpe:%i]: Enabling Concurrent Execution "
"virtual processors %i", vpe);
list<unsigned>::iterator thread_it = currentThreads.begin();
list<ThreadID>::iterator thread_it = currentThreads.begin();
while (thread_it != currentThreads.end()) {
if (!isThreadSuspended(*thread_it)) {
@ -623,7 +623,7 @@ InOrderCPU::enableVPEs(unsigned vpe)
}
void
InOrderCPU::disableVirtProcElement(unsigned tid, unsigned vpe)
InOrderCPU::disableVirtProcElement(ThreadID tid, unsigned vpe)
{
DPRINTF(InOrderCPU, "[vpe:%i]: Scheduling "
"Disabling of concurrent virtual processor execution",
@ -633,16 +633,16 @@ InOrderCPU::disableVirtProcElement(unsigned tid, unsigned vpe)
}
void
InOrderCPU::disableVPEs(unsigned tid, unsigned vpe)
InOrderCPU::disableVPEs(ThreadID tid, unsigned vpe)
{
DPRINTF(InOrderCPU, "[vpe:%i]: Disabling Concurrent Execution of "
"virtual processors %i", vpe);
unsigned base_vpe = TheISA::getVirtProcNum(tcBase(tid));
list<unsigned>::iterator thread_it = activeThreads.begin();
list<ThreadID>::iterator thread_it = activeThreads.begin();
std::vector<list<unsigned>::iterator> removeList;
vector<list<ThreadID>::iterator> removeList;
while (thread_it != activeThreads.end()) {
if (base_vpe != vpe) {
@ -672,7 +672,7 @@ InOrderCPU::enableThreads(unsigned vpe)
DPRINTF(InOrderCPU, "[vpe:%i]: Enabling Multithreading on "
"virtual processor %i", vpe);
list<unsigned>::iterator thread_it = currentThreads.begin();
list<ThreadID>::iterator thread_it = currentThreads.begin();
while (thread_it != currentThreads.end()) {
if (TheISA::getVirtProcNum(tcBase(*thread_it)) == vpe) {
@ -684,7 +684,7 @@ InOrderCPU::enableThreads(unsigned vpe)
}
}
void
InOrderCPU::disableMultiThreading(unsigned tid, unsigned vpe)
InOrderCPU::disableMultiThreading(ThreadID tid, unsigned vpe)
{
// Schedule event to take place at end of cycle
DPRINTF(InOrderCPU, "[tid:%i]: Scheduling Disable Multithreading on "
@ -694,14 +694,14 @@ InOrderCPU::disableMultiThreading(unsigned tid, unsigned vpe)
}
void
InOrderCPU::disableThreads(unsigned tid, unsigned vpe)
InOrderCPU::disableThreads(ThreadID tid, unsigned vpe)
{
DPRINTF(InOrderCPU, "[tid:%i]: Disabling Multithreading on "
"virtual processor %i", tid, vpe);
list<unsigned>::iterator thread_it = activeThreads.begin();
list<ThreadID>::iterator thread_it = activeThreads.begin();
std::vector<list<unsigned>::iterator> removeList;
vector<list<ThreadID>::iterator> removeList;
while (thread_it != activeThreads.end()) {
if (TheISA::getVirtProcNum(tcBase(*thread_it)) == vpe) {
@ -722,8 +722,8 @@ InOrderCPU::updateThreadPriority()
{
//DEFAULT TO ROUND ROBIN SCHEME
//e.g. Move highest priority to end of thread list
list<unsigned>::iterator list_begin = activeThreads.begin();
list<unsigned>::iterator list_end = activeThreads.end();
list<ThreadID>::iterator list_begin = activeThreads.begin();
list<ThreadID>::iterator list_end = activeThreads.end();
unsigned high_thread = *list_begin;
@ -737,7 +737,7 @@ inline void
InOrderCPU::tickThreadStats()
{
/** Keep track of cycles that each thread is active */
list<unsigned>::iterator thread_it = activeThreads.begin();
list<ThreadID>::iterator thread_it = activeThreads.begin();
while (thread_it != activeThreads.end()) {
threadCycles[*thread_it]++;
thread_it++;
@ -750,7 +750,7 @@ InOrderCPU::tickThreadStats()
}
void
InOrderCPU::activateContext(unsigned tid, int delay)
InOrderCPU::activateContext(ThreadID tid, int delay)
{
DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
@ -765,27 +765,27 @@ InOrderCPU::activateContext(unsigned tid, int delay)
void
InOrderCPU::suspendContext(unsigned tid, int delay)
InOrderCPU::suspendContext(ThreadID tid, int delay)
{
scheduleCpuEvent(SuspendThread, NoFault, tid, 0/*vpe*/, delay);
//_status = Idle;
}
void
InOrderCPU::suspendThread(unsigned tid)
InOrderCPU::suspendThread(ThreadID tid)
{
DPRINTF(InOrderCPU,"[tid: %i]: Suspended ...\n", tid);
deactivateThread(tid);
}
void
InOrderCPU::deallocateContext(unsigned tid, int delay)
InOrderCPU::deallocateContext(ThreadID tid, int delay)
{
scheduleCpuEvent(DeallocateThread, NoFault, tid, 0/*vpe*/, delay);
}
void
InOrderCPU::deallocateThread(unsigned tid)
InOrderCPU::deallocateThread(ThreadID tid)
{
DPRINTF(InOrderCPU,"[tid:%i]: Deallocating ...", tid);
@ -797,7 +797,7 @@ InOrderCPU::deallocateThread(unsigned tid)
}
void
InOrderCPU::squashThreadInPipeline(unsigned tid)
InOrderCPU::squashThreadInPipeline(ThreadID tid)
{
//Squash all instructions in each stage
for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
@ -806,7 +806,7 @@ InOrderCPU::squashThreadInPipeline(unsigned tid)
}
void
InOrderCPU::haltContext(unsigned tid, int delay)
InOrderCPU::haltContext(ThreadID tid, int delay)
{
DPRINTF(InOrderCPU, "[tid:%i]: Halt context called.\n", tid);
@ -817,13 +817,13 @@ InOrderCPU::haltContext(unsigned tid, int delay)
}
void
InOrderCPU::insertThread(unsigned tid)
InOrderCPU::insertThread(ThreadID tid)
{
panic("Unimplemented Function\n.");
}
void
InOrderCPU::removeThread(unsigned tid)
InOrderCPU::removeThread(ThreadID tid)
{
DPRINTF(InOrderCPU, "Removing Thread %i from CPU.\n", tid);
@ -838,97 +838,98 @@ InOrderCPU::getPipeStage(int stage_num)
void
InOrderCPU::activateWhenReady(int tid)
InOrderCPU::activateWhenReady(ThreadID tid)
{
panic("Unimplemented Function\n.");
}
uint64_t
InOrderCPU::readPC(unsigned tid)
InOrderCPU::readPC(ThreadID tid)
{
return PC[tid];
}
void
InOrderCPU::setPC(Addr new_PC, unsigned tid)
InOrderCPU::setPC(Addr new_PC, ThreadID tid)
{
PC[tid] = new_PC;
}
uint64_t
InOrderCPU::readNextPC(unsigned tid)
InOrderCPU::readNextPC(ThreadID tid)
{
return nextPC[tid];
}
void
InOrderCPU::setNextPC(uint64_t new_NPC, unsigned tid)
InOrderCPU::setNextPC(uint64_t new_NPC, ThreadID tid)
{
nextPC[tid] = new_NPC;
}
uint64_t
InOrderCPU::readNextNPC(unsigned tid)
InOrderCPU::readNextNPC(ThreadID tid)
{
return nextNPC[tid];
}
void
InOrderCPU::setNextNPC(uint64_t new_NNPC, unsigned tid)
InOrderCPU::setNextNPC(uint64_t new_NNPC, ThreadID tid)
{
nextNPC[tid] = new_NNPC;
}
uint64_t
InOrderCPU::readIntReg(int reg_idx, unsigned tid)
InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
{
return intRegFile[tid].readReg(reg_idx);
}
FloatReg
InOrderCPU::readFloatReg(int reg_idx, unsigned tid, int width)
InOrderCPU::readFloatReg(int reg_idx, ThreadID tid, int width)
{
return floatRegFile[tid].readReg(reg_idx, width);
}
FloatRegBits
InOrderCPU::readFloatRegBits(int reg_idx, unsigned tid, int width)
InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid, int width)
{;
return floatRegFile[tid].readRegBits(reg_idx, width);
}
void
InOrderCPU::setIntReg(int reg_idx, uint64_t val, unsigned tid)
InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
{
intRegFile[tid].setReg(reg_idx, val);
}
void
InOrderCPU::setFloatReg(int reg_idx, FloatReg val, unsigned tid, int width)
InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid, int width)
{
floatRegFile[tid].setReg(reg_idx, val, width);
}
void
InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, unsigned tid, int width)
InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid,
int width)
{
floatRegFile[tid].setRegBits(reg_idx, val, width);
}
uint64_t
InOrderCPU::readRegOtherThread(unsigned reg_idx, unsigned tid)
InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
{
// If Default value is set, then retrieve target thread
if (tid == -1) {
if (tid == InvalidThreadID) {
tid = TheISA::getTargetThread(tcBase(tid));
}
@ -943,10 +944,11 @@ InOrderCPU::readRegOtherThread(unsigned reg_idx, unsigned tid)
}
}
void
InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val, unsigned tid)
InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
ThreadID tid)
{
// If Default value is set, then retrieve target thread
if (tid == -1) {
if (tid == InvalidThreadID) {
tid = TheISA::getTargetThread(tcBase(tid));
}
@ -962,25 +964,25 @@ InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val, unsigned tid
}
MiscReg
InOrderCPU::readMiscRegNoEffect(int misc_reg, unsigned tid)
InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
{
return miscRegFile.readRegNoEffect(misc_reg, tid);
}
MiscReg
InOrderCPU::readMiscReg(int misc_reg, unsigned tid)
InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
{
return miscRegFile.readReg(misc_reg, tcBase(tid), tid);
}
void
InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid)
InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
{
miscRegFile.setRegNoEffect(misc_reg, val, tid);
}
void
InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
{
miscRegFile.setReg(misc_reg, val, tcBase(tid), tid);
}
@ -989,7 +991,7 @@ InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
InOrderCPU::ListIt
InOrderCPU::addInst(DynInstPtr &inst)
{
int tid = inst->readTid();
ThreadID tid = inst->readTid();
instList[tid].push_back(inst);
@ -997,7 +999,7 @@ InOrderCPU::addInst(DynInstPtr &inst)
}
void
InOrderCPU::instDone(DynInstPtr inst, unsigned tid)
InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
{
// Set the CPU's PCs - This contributes to the precise state of the CPU which can be used
// when restoring a thread to the CPU after a fork or after an exception
@ -1069,8 +1071,7 @@ InOrderCPU::removeInst(DynInstPtr &inst)
}
void
InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num,
unsigned tid)
InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
{
//assert(!instList[tid].empty());
@ -1099,7 +1100,7 @@ InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num,
inline void
InOrderCPU::squashInstIt(const ListIt &instIt, const unsigned &tid)
InOrderCPU::squashInstIt(const ListIt &instIt, ThreadID tid)
{
if ((*instIt)->threadNumber == tid) {
DPRINTF(InOrderCPU, "Squashing instruction, "
@ -1126,7 +1127,7 @@ InOrderCPU::cleanUpRemovedInsts()
(*removeList.front())->readPC());
DynInstPtr inst = *removeList.front();
int tid = inst->threadNumber;
ThreadID tid = inst->threadNumber;
// Make Sure Resource Schedule Is Emptied Out
ThePipeline::ResSchedule *inst_sched = &inst->resSched;
@ -1234,7 +1235,7 @@ InOrderCPU::wakeCPU()
}
void
InOrderCPU::syscall(int64_t callnum, int tid)
InOrderCPU::syscall(int64_t callnum, ThreadID tid)
{
DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);

138
src/cpu/inorder/cpu.hh
View file

@ -41,6 +41,7 @@
#include "arch/isa_traits.hh"
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "base/types.hh"
#include "config/full_system.hh"
#include "cpu/activity.hh"
#include "cpu/base.hh"
@ -185,17 +186,18 @@ class InOrderCPU : public BaseCPU
public:
CPUEventType cpuEventType;
unsigned tid;
ThreadID tid;
unsigned vpe;
Fault fault;
public:
/** Constructs a CPU event. */
CPUEvent(InOrderCPU *_cpu, CPUEventType e_type, Fault fault,
unsigned _tid, unsigned _vpe);
ThreadID _tid, unsigned _vpe);
/** Set Type of Event To Be Scheduled */
void setEvent(CPUEventType e_type, Fault _fault, unsigned _tid, unsigned _vpe)
void setEvent(CPUEventType e_type, Fault _fault, ThreadID _tid,
unsigned _vpe)
{
fault = _fault;
cpuEventType = e_type;
@ -217,7 +219,7 @@ class InOrderCPU : public BaseCPU
};
/** Schedule a CPU Event */
void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, unsigned tid,
void scheduleCpuEvent(CPUEventType cpu_event, Fault fault, ThreadID tid,
unsigned vpe, unsigned delay = 0);
public:
@ -293,29 +295,29 @@ class InOrderCPU : public BaseCPU
/** trap() - sets up a trap event on the cpuTraps to handle given fault.
* trapCPU() - Traps to handle given fault
*/
void trap(Fault fault, unsigned tid, int delay = 0);
void trapCPU(Fault fault, unsigned tid);
void trap(Fault fault, ThreadID tid, int delay = 0);
void trapCPU(Fault fault, ThreadID tid);
/** Setup CPU to insert a thread's context */
void insertThread(unsigned tid);
void insertThread(ThreadID tid);
/** Remove all of a thread's context from CPU */
void removeThread(unsigned tid);
void removeThread(ThreadID tid);
/** Add Thread to Active Threads List. */
void activateContext(unsigned tid, int delay = 0);
void activateThread(unsigned tid);
void activateContext(ThreadID tid, int delay = 0);
void activateThread(ThreadID tid);
/** Remove Thread from Active Threads List */
void suspendContext(unsigned tid, int delay = 0);
void suspendThread(unsigned tid);
void suspendContext(ThreadID tid, int delay = 0);
void suspendThread(ThreadID tid);
/** Remove Thread from Active Threads List &&
* Remove Thread Context from CPU.
*/
void deallocateContext(unsigned tid, int delay = 0);
void deallocateThread(unsigned tid);
void deactivateThread(unsigned tid);
void deallocateContext(ThreadID tid, int delay = 0);
void deallocateThread(ThreadID tid);
void deactivateThread(ThreadID tid);
PipelineStage* getPipeStage(int stage_num);
@ -329,30 +331,30 @@ class InOrderCPU : public BaseCPU
/** Remove Thread from Active Threads List &&
* Remove Thread Context from CPU.
*/
void haltContext(unsigned tid, int delay = 0);
void haltContext(ThreadID tid, int delay = 0);
void removePipelineStalls(unsigned tid);
void removePipelineStalls(ThreadID tid);
void squashThreadInPipeline(unsigned tid);
void squashThreadInPipeline(ThreadID tid);
/// Notify the CPU to enable a virtual processor element.
virtual void enableVirtProcElement(unsigned vpe);
void enableVPEs(unsigned vpe);
/// Notify the CPU to disable a virtual processor element.
virtual void disableVirtProcElement(unsigned tid, unsigned vpe);
void disableVPEs(unsigned tid, unsigned vpe);
virtual void disableVirtProcElement(ThreadID tid, unsigned vpe);
void disableVPEs(ThreadID tid, unsigned vpe);
/// Notify the CPU that multithreading is enabled.
virtual void enableMultiThreading(unsigned vpe);
void enableThreads(unsigned vpe);
/// Notify the CPU that multithreading is disabled.
virtual void disableMultiThreading(unsigned tid, unsigned vpe);
void disableThreads(unsigned tid, unsigned vpe);
virtual void disableMultiThreading(ThreadID tid, unsigned vpe);
void disableThreads(ThreadID tid, unsigned vpe);
/** Activate a Thread When CPU Resources are Available. */
void activateWhenReady(int tid);
void activateWhenReady(ThreadID tid);
/** Add or Remove a Thread Context in the CPU. */
void doContextSwitch();
@ -365,19 +367,19 @@ class InOrderCPU : public BaseCPU
{ /*pipelineStage[stage_idx]->switchToActive();*/ }
/** Get the current instruction sequence number, and increment it. */
InstSeqNum getAndIncrementInstSeq(unsigned tid)
InstSeqNum getAndIncrementInstSeq(ThreadID tid)
{ return globalSeqNum[tid]++; }
/** Get the current instruction sequence number, and increment it. */
InstSeqNum nextInstSeqNum(unsigned tid)
InstSeqNum nextInstSeqNum(ThreadID tid)
{ return globalSeqNum[tid]; }
/** Increment Instruction Sequence Number */
void incrInstSeqNum(unsigned tid)
void incrInstSeqNum(ThreadID tid)
{ globalSeqNum[tid]++; }
/** Set Instruction Sequence Number */
void setInstSeqNum(unsigned tid, InstSeqNum seq_num)
void setInstSeqNum(ThreadID tid, InstSeqNum seq_num)
{
globalSeqNum[tid] = seq_num;
}
@ -389,73 +391,76 @@ class InOrderCPU : public BaseCPU
}
/** Get instruction asid. */
int getInstAsid(unsigned tid)
int getInstAsid(ThreadID tid)
{ return thread[tid]->getInstAsid(); }
/** Get data asid. */
int getDataAsid(unsigned tid)
int getDataAsid(ThreadID tid)
{ return thread[tid]->getDataAsid(); }
/** Register file accessors */
uint64_t readIntReg(int reg_idx, unsigned tid);
uint64_t readIntReg(int reg_idx, ThreadID tid);
FloatReg readFloatReg(int reg_idx, unsigned tid,
FloatReg readFloatReg(int reg_idx, ThreadID tid,
int width = TheISA::SingleWidth);
FloatRegBits readFloatRegBits(int reg_idx, unsigned tid,
FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid,
int width = TheISA::SingleWidth);
void setIntReg(int reg_idx, uint64_t val, unsigned tid);
void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
void setFloatReg(int reg_idx, FloatReg val, unsigned tid,
void setFloatReg(int reg_idx, FloatReg val, ThreadID tid,
int width = TheISA::SingleWidth);
void setFloatRegBits(int reg_idx, FloatRegBits val, unsigned tid,
void setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid,
int width = TheISA::SingleWidth);
/** Reads a miscellaneous register. */
MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0);
MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
/** Reads a misc. register, including any side effects the read
* might have as defined by the architecture.
*/
MiscReg readMiscReg(int misc_reg, unsigned tid = 0);
MiscReg readMiscReg(int misc_reg, ThreadID tid = 0);
/** Sets a miscellaneous register. */
void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0);
void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
ThreadID tid = 0);
/** Sets a misc. register, including any side effects the write
* might have as defined by the architecture.
*/
void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0);
void setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0);
/** Reads a int/fp/misc reg. from another thread depending on ISA-defined
* target thread
*/
uint64_t readRegOtherThread(unsigned misc_reg, unsigned tid = -1);
uint64_t readRegOtherThread(unsigned misc_reg,
ThreadID tid = InvalidThreadID);
/** Sets a int/fp/misc reg. from another thread depending on an ISA-defined
* target thread
*/
void setRegOtherThread(unsigned misc_reg, const MiscReg &val, unsigned tid);
void setRegOtherThread(unsigned misc_reg, const MiscReg &val,
ThreadID tid);
/** Reads the commit PC of a specific thread. */
uint64_t readPC(unsigned tid);
uint64_t readPC(ThreadID tid);
/** Sets the commit PC of a specific thread. */
void setPC(Addr new_PC, unsigned tid);
void setPC(Addr new_PC, ThreadID tid);
/** Reads the next PC of a specific thread. */
uint64_t readNextPC(unsigned tid);
uint64_t readNextPC(ThreadID tid);
/** Sets the next PC of a specific thread. */
void setNextPC(uint64_t val, unsigned tid);
void setNextPC(uint64_t val, ThreadID tid);
/** Reads the next NPC of a specific thread. */
uint64_t readNextNPC(unsigned tid);
uint64_t readNextNPC(ThreadID tid);
/** Sets the next NPC of a specific thread. */
void setNextNPC(uint64_t val, unsigned tid);
void setNextNPC(uint64_t val, ThreadID tid);
/** Function to add instruction onto the head of the list of the
* instructions. Used when new instructions are fetched.
@ -463,7 +468,7 @@ class InOrderCPU : public BaseCPU
ListIt addInst(DynInstPtr &inst);
/** Function to tell the CPU that an instruction has completed. */
void instDone(DynInstPtr inst, unsigned tid);
void instDone(DynInstPtr inst, ThreadID tid);
/** Add Instructions to the CPU Remove List*/
void addToRemoveList(DynInstPtr &inst);
@ -472,10 +477,10 @@ class InOrderCPU : public BaseCPU
void removeInst(DynInstPtr &inst);
/** Remove all instructions younger than the given sequence number. */
void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
/** Removes the instruction pointed to by the iterator. */
inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
inline void squashInstIt(const ListIt &instIt, ThreadID tid);
/** Cleans up all instructions on the instruction remove list. */
void cleanUpRemovedInsts();
@ -513,7 +518,7 @@ class InOrderCPU : public BaseCPU
void writeHint(DynInstPtr inst);
/** Executes a syscall.*/
void syscall(int64_t callnum, int tid);
void syscall(int64_t callnum, ThreadID tid);
public:
/** Per-Thread List of all the instructions in flight. */
@ -553,24 +558,24 @@ class InOrderCPU : public BaseCPU
/** Last Cycle that the CPU squashed instruction end. */
Tick lastSquashCycle[ThePipeline::MaxThreads];
std::list<unsigned> fetchPriorityList;
std::list<ThreadID> fetchPriorityList;
protected:
/** Active Threads List */
std::list<unsigned> activeThreads;
std::list<ThreadID> activeThreads;
/** Current Threads List */
std::list<unsigned> currentThreads;
std::list<ThreadID> currentThreads;
/** Suspended Threads List */
std::list<unsigned> suspendedThreads;
std::list<ThreadID> suspendedThreads;
/** Thread Status Functions (Unused Currently) */
bool isThreadInCPU(unsigned tid);
bool isThreadActive(unsigned tid);
bool isThreadSuspended(unsigned tid);
void addToCurrentThreads(unsigned tid);
void removeFromCurrentThreads(unsigned tid);
bool isThreadInCPU(ThreadID tid);
bool isThreadActive(ThreadID tid);
bool isThreadSuspended(ThreadID tid);
void addToCurrentThreads(ThreadID tid);
void removeFromCurrentThreads(ThreadID tid);
private:
/** The activity recorder; used to tell if the CPU has any
@ -583,7 +588,7 @@ class InOrderCPU : public BaseCPU
void readFunctional(Addr addr, uint32_t &buffer);
/** Number of Active Threads in the CPU */
int numActiveThreads() { return activeThreads.size(); }
ThreadID numActiveThreads() { return activeThreads.size(); }
/** Records that there was time buffer activity this cycle. */
void activityThisCycle() { activityRec.activity(); }
@ -600,7 +605,7 @@ class InOrderCPU : public BaseCPU
void wakeCPU();
/** Gets a free thread id. Use if thread ids change across system. */
int getFreeTid();
ThreadID getFreeTid();
// LL/SC debug functionality
unsigned stCondFails;
@ -608,7 +613,7 @@ class InOrderCPU : public BaseCPU
unsigned setStCondFailures(unsigned st_fails) { return stCondFails = st_fails; }
/** Returns a pointer to a thread context. */
ThreadContext *tcBase(unsigned tid = 0)
ThreadContext *tcBase(ThreadID tid = 0)
{
return thread[tid]->getTC();
}
@ -618,8 +623,8 @@ class InOrderCPU : public BaseCPU
{
Counter total(0);
for (int i=0; i < thread.size(); i++)
total += thread[i]->numInst;
for (ThreadID tid = 0; tid < thread.size(); tid++)
total += thread[tid]->numInst;
return total;
}
@ -657,9 +662,6 @@ class InOrderCPU : public BaseCPU
/** The cycle that the CPU was last running, used for statistics. */
Tick lastRunningCycle;
/** Number of Threads the CPU can process */
unsigned numThreads;
/** Number of Virtual Processors the CPU can process */
unsigned numVirtProcs;

36
src/cpu/inorder/first_stage.cc
View file

@ -43,7 +43,7 @@ FirstStage::FirstStage(Params *params, unsigned stage_num)
: PipelineStage(params, stage_num), numFetchingThreads(1),
fetchPolicy(FirstStage::RoundRobin)
{
for(int tid=0; tid < this->numThreads; tid++) {
for(ThreadID tid = 0; tid < this->numThreads; tid++) {
stageStatus[tid] = Running;
}
}
@ -60,7 +60,7 @@ FirstStage::setCPU(InOrderCPU *cpu_ptr)
void
FirstStage::squash(InstSeqNum squash_seq_num, unsigned tid)
FirstStage::squash(InstSeqNum squash_seq_num, ThreadID tid)
{
// Set status to squashing.
//stageStatus[tid] = Squashing;
@ -96,17 +96,17 @@ FirstStage::squash(InstSeqNum squash_seq_num, unsigned tid)
void
FirstStage::processStage(bool &status_change)
{
list<unsigned>::iterator threads = (*activeThreads).begin();
list<ThreadID>::iterator threads = activeThreads->begin();
//Check stall and squash signals.
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
while (threads != activeThreads->end()) {
ThreadID tid = *threads++;
status_change = checkSignalsAndUpdate(tid) || status_change;
}
for (int threadFetched = 0; threadFetched < numFetchingThreads;
threadFetched++) {
int tid = getFetchingThread(fetchPolicy);
ThreadID tid = getFetchingThread(fetchPolicy);
if (tid >= 0) {
DPRINTF(InOrderStage, "Processing [tid:%i]\n",tid);
@ -120,7 +120,7 @@ FirstStage::processStage(bool &status_change)
//@TODO: Note in documentation, that when you make a pipeline stage change, then
//make sure you change the first stage too
void
FirstStage::processInsts(unsigned tid)
FirstStage::processInsts(ThreadID tid)
{
bool all_reqs_completed = true;
@ -194,7 +194,7 @@ FirstStage::processInsts(unsigned tid)
}
}
int
ThreadID
FirstStage::getFetchingThread(FetchPriority &fetch_priority)
{
if (numThreads > 1) {
@ -207,28 +207,28 @@ FirstStage::getFetchingThread(FetchPriority &fetch_priority)
return roundRobin();
default:
return -1;
return InvalidThreadID;
}
} else {
int tid = *((*activeThreads).begin());
ThreadID tid = *activeThreads->begin();
if (stageStatus[tid] == Running ||
stageStatus[tid] == Idle) {
return tid;
} else {
return -1;
return InvalidThreadID;
}
}
}
int
ThreadID
FirstStage::roundRobin()
{
list<unsigned>::iterator pri_iter = (*fetchPriorityList).begin();
list<unsigned>::iterator end = (*fetchPriorityList).end();
list<ThreadID>::iterator pri_iter = fetchPriorityList->begin();
list<ThreadID>::iterator end = fetchPriorityList->end();
int high_pri;
ThreadID high_pri;
while (pri_iter != end) {
high_pri = *pri_iter;
@ -238,8 +238,8 @@ FirstStage::roundRobin()
if (stageStatus[high_pri] == Running ||
stageStatus[high_pri] == Idle) {
(*fetchPriorityList).erase(pri_iter);
(*fetchPriorityList).push_back(high_pri);
fetchPriorityList->erase(pri_iter);
fetchPriorityList->push_back(high_pri);
return high_pri;
}
@ -247,5 +247,5 @@ FirstStage::roundRobin()
pri_iter++;
}
return -1;
return InvalidThreadID;
}

14
src/cpu/inorder/first_stage.hh
View file

@ -56,10 +56,10 @@ class FirstStage : public PipelineStage {
void processStage(bool &status_change);
/** Process All Instructions Available */
void processInsts(unsigned tid);
void processInsts(ThreadID tid);
/** Squash Instructions Above a Seq. Num */
void squash(InstSeqNum squash_seq_num, unsigned tid);
void squash(InstSeqNum squash_seq_num, ThreadID tid);
/** There are no insts. coming from previous stages, so there is
* no need to sort insts here
@ -69,7 +69,7 @@ class FirstStage : public PipelineStage {
/** There are no skidBuffers for the first stage. So
* just use an empty function.
*/
void skidInsert(unsigned tid) { }
void skidInsert(ThreadID tid) { }
/** The number of fetching threads in the CPU */
int numFetchingThreads;
@ -85,13 +85,13 @@ class FirstStage : public PipelineStage {
FetchPriority fetchPolicy;
/** List that has the threads organized by priority. */
std::list<unsigned> *fetchPriorityList;
std::list<ThreadID> *fetchPriorityList;
/** Return the next fetching thread */
int getFetchingThread(FetchPriority &fetch_priority);
ThreadID getFetchingThread(FetchPriority &fetch_priority);
/** Return next thred given Round Robin Policy for Thread Fetching */
int roundRobin();
/** Return next thread given Round Robin Policy for Thread Fetching */
ThreadID roundRobin();
};
#endif // __CPU_INORDER_FIRST_STAGE_HH__

2
src/cpu/inorder/inorder_cpu_builder.cc
View file

@ -42,7 +42,7 @@
InOrderCPU *
InOrderCPUParams::create()
{
int actual_num_threads =
ThreadID actual_num_threads =
(numThreads >= workload.size()) ? numThreads : workload.size();
if (workload.size() == 0) {

11
src/cpu/inorder/inorder_dyn_inst.cc
View file

@ -66,7 +66,7 @@ InOrderDynInst::InOrderDynInst(TheISA::ExtMachInst machInst, Addr inst_PC,
InOrderDynInst::InOrderDynInst(InOrderCPU *cpu,
InOrderThreadState *state,
InstSeqNum seq_num,
unsigned tid,
ThreadID tid,
unsigned _asid)
: traceData(NULL), cpu(cpu)
{
@ -385,7 +385,7 @@ InOrderDynInst::setFloatRegBitsSrc(int idx, uint64_t val)
/** Reads a integer register. */
IntReg
InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, unsigned tid)
InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, ThreadID tid)
{
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Source Value %i read as %#x.\n",
threadNumber, seqNum, idx, instSrc[idx].integer);
@ -479,7 +479,7 @@ InOrderDynInst::setMiscRegOperand(const StaticInst *si, int idx,
}
MiscReg
InOrderDynInst::readRegOtherThread(unsigned reg_idx, int tid)
InOrderDynInst::readRegOtherThread(unsigned reg_idx, ThreadID tid)
{
if (tid == -1) {
tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
@ -553,9 +553,10 @@ InOrderDynInst::setMiscReg(int misc_reg, const MiscReg &val)
}
void
InOrderDynInst::setRegOtherThread(unsigned reg_idx, const MiscReg &val, int tid)
InOrderDynInst::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
ThreadID tid)
{
if (tid == -1) {
if (tid == InvalidThreadID) {
tid = TheISA::getTargetThread(this->cpu->tcBase(threadNumber));
}

14
src/cpu/inorder/inorder_dyn_inst.hh
View file

@ -112,8 +112,8 @@ class InOrderDynInst : public FastAlloc, public RefCounted
* @param cpu Pointer to the instruction's CPU.
* NOTE: Must set Binary Instrution through Member Function
*/
InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state, InstSeqNum seq_num,
unsigned tid, unsigned asid = 0);
InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state,
InstSeqNum seq_num, ThreadID tid, unsigned asid = 0);
/** BaseDynInst constructor given a StaticInst pointer.
* @param _staticInst The StaticInst for this BaseDynInst.
@ -347,7 +347,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
short readTid() { return threadNumber; }
/** Sets the thread id. */
void setTid(unsigned tid) { threadNumber = tid; }
void setTid(ThreadID tid) { threadNumber = tid; }
void setVpn(int id) { virtProcNumber = id; }
@ -829,7 +829,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
* language (which is why the name isnt readIntSrc(...)) Note: That
* the source reg. value is set using the setSrcReg() function.
*/
IntReg readIntRegOperand(const StaticInst *si, int idx, unsigned tid=0);
IntReg readIntRegOperand(const StaticInst *si, int idx, ThreadID tid = 0);
FloatReg readFloatRegOperand(const StaticInst *si, int idx,
int width = TheISA::SingleWidth);
TheISA::FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
@ -881,8 +881,10 @@ class InOrderDynInst : public FastAlloc, public RefCounted
void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val);
void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val);
virtual uint64_t readRegOtherThread(unsigned idx, int tid = -1);
virtual void setRegOtherThread(unsigned idx, const uint64_t &val, int tid = -1);
virtual uint64_t readRegOtherThread(unsigned idx,
ThreadID tid = InvalidThreadID);
virtual void setRegOtherThread(unsigned idx, const uint64_t &val,
ThreadID tid = InvalidThreadID);
/** Sets the number of consecutive store conditional failures. */
void setStCondFailures(unsigned sc_failures)

84
src/cpu/inorder/pipeline_stage.cc
View file

@ -49,7 +49,7 @@ PipelineStage::PipelineStage(Params *params, unsigned stage_num)
void
PipelineStage::init(Params *params)
{
for(int tid=0; tid < numThreads; tid++) {
for(ThreadID tid = 0; tid < numThreads; tid++) {
stageStatus[tid] = Idle;
for (int stNum = 0; stNum < NumStages; stNum++) {
@ -162,7 +162,7 @@ PipelineStage::setNextStageQueue(TimeBuffer<InterStageStruct> *next_stage_ptr)
void
PipelineStage::setActiveThreads(list<unsigned> *at_ptr)
PipelineStage::setActiveThreads(list<ThreadID> *at_ptr)
{
DPRINTF(InOrderStage, "Setting active threads list pointer.\n");
activeThreads = at_ptr;
@ -194,20 +194,20 @@ PipelineStage::takeOverFrom()
_status = Inactive;
// Be sure to reset state and clear out any old instructions.
for (int i = 0; i < numThreads; ++i) {
stageStatus[i] = Idle;
for (ThreadID tid = 0; tid < numThreads; ++tid) {
stageStatus[tid] = Idle;
for (int stNum = 0; stNum < NumStages; stNum++) {
stalls[i].stage[stNum] = false;
stalls[tid].stage[stNum] = false;
}
stalls[i].resources.clear();
stalls[tid].resources.clear();
while (!insts[i].empty())
insts[i].pop();
while (!insts[tid].empty())
insts[tid].pop();
while (!skidBuffer[i].empty())
skidBuffer[i].pop();
while (!skidBuffer[tid].empty())
skidBuffer[tid].pop();
}
wroteToTimeBuffer = false;
}
@ -215,7 +215,7 @@ PipelineStage::takeOverFrom()
bool
PipelineStage::checkStall(unsigned tid) const
PipelineStage::checkStall(ThreadID tid) const
{
bool ret_val = false;
@ -243,7 +243,7 @@ PipelineStage::checkStall(unsigned tid) const
void
PipelineStage::removeStalls(unsigned tid)
PipelineStage::removeStalls(ThreadID tid)
{
for (int stNum = 0; stNum < NumStages; stNum++) {
stalls[tid].stage[stNum] = false;
@ -258,13 +258,13 @@ PipelineStage::prevStageInstsValid()
}
bool
PipelineStage::isBlocked(unsigned tid)
PipelineStage::isBlocked(ThreadID tid)
{
return stageStatus[tid] == Blocked;
}
bool
PipelineStage::block(unsigned tid)
PipelineStage::block(ThreadID tid)
{
DPRINTF(InOrderStage, "[tid:%d]: Blocking, sending block signal back to previous stages.\n", tid);
@ -293,7 +293,7 @@ PipelineStage::block(unsigned tid)
}
void
PipelineStage::blockDueToBuffer(unsigned tid)
PipelineStage::blockDueToBuffer(ThreadID tid)
{
DPRINTF(InOrderStage, "[tid:%d]: Blocking instructions from passing to next stage.\n", tid);
@ -308,7 +308,7 @@ PipelineStage::blockDueToBuffer(unsigned tid)
}
bool
PipelineStage::unblock(unsigned tid)
PipelineStage::unblock(ThreadID tid)
{
// Stage is done unblocking only if the skid buffer is empty.
if (skidBuffer[tid].empty()) {
@ -329,7 +329,7 @@ PipelineStage::unblock(unsigned tid)
}
void
PipelineStage::squashDueToBranch(DynInstPtr &inst, unsigned tid)
PipelineStage::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
{
if (cpu->squashSeqNum[tid] < inst->seqNum &&
cpu->lastSquashCycle[tid] == curTick){
@ -367,8 +367,7 @@ PipelineStage::squashDueToBranch(DynInstPtr &inst, unsigned tid)
}
void
PipelineStage::squashPrevStageInsts(InstSeqNum squash_seq_num,
unsigned tid)
PipelineStage::squashPrevStageInsts(InstSeqNum squash_seq_num, ThreadID tid)
{
DPRINTF(InOrderStage, "[tid:%i]: Removing instructions from "
"incoming stage queue.\n", tid);
@ -387,7 +386,7 @@ PipelineStage::squashPrevStageInsts(InstSeqNum squash_seq_num,
}
void
PipelineStage::squash(InstSeqNum squash_seq_num, unsigned tid)
PipelineStage::squash(InstSeqNum squash_seq_num, ThreadID tid)
{
// Set status to squashing.
stageStatus[tid] = Squashing;
@ -450,7 +449,7 @@ PipelineStage::canSendInstToStage(unsigned stage_num)
}
void
PipelineStage::skidInsert(unsigned tid)
PipelineStage::skidInsert(ThreadID tid)
{
DynInstPtr inst = NULL;
@ -484,9 +483,9 @@ PipelineStage::skidSize()
bool
PipelineStage::skidsEmpty()
{
list<unsigned>::iterator threads = (*activeThreads).begin();
list<ThreadID>::iterator threads = activeThreads->begin();
while (threads != (*activeThreads).end()) {
while (threads != activeThreads->end()) {
if (!skidBuffer[*threads++].empty())
return false;
}
@ -501,12 +500,10 @@ PipelineStage::updateStatus()
{
bool any_unblocking = false;
list<unsigned>::iterator threads = (*activeThreads).begin();
list<ThreadID>::iterator threads = activeThreads->begin();
threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
while (threads != activeThreads->end()) {
ThreadID tid = *threads++;
if (stageStatus[tid] == Unblocking) {
any_unblocking = true;
@ -561,7 +558,7 @@ PipelineStage::sortInsts()
prevStage->insts[i]->readTid(),
prevStage->insts[i]->seqNum);
int tid = prevStage->insts[i]->threadNumber;
ThreadID tid = prevStage->insts[i]->threadNumber;
DynInstPtr inst = prevStage->insts[i];
@ -576,7 +573,7 @@ PipelineStage::sortInsts()
void
PipelineStage::readStallSignals(unsigned tid)
PipelineStage::readStallSignals(ThreadID tid)
{
for (int stage_idx = stageNum+1; stage_idx <= lastStallingStage[tid];
stage_idx++) {
@ -597,7 +594,7 @@ PipelineStage::readStallSignals(unsigned tid)
bool
PipelineStage::checkSignalsAndUpdate(unsigned tid)
PipelineStage::checkSignalsAndUpdate(ThreadID tid)
{
// Check if there's a squash signal, squash if there is.
// Check stall signals, block if necessary.
@ -691,14 +688,14 @@ PipelineStage::tick()
}
void
PipelineStage::setResStall(ResReqPtr res_req, unsigned tid)
PipelineStage::setResStall(ResReqPtr res_req, ThreadID tid)
{
DPRINTF(InOrderStage, "Inserting stall from %s.\n", res_req->res->name());
stalls[tid].resources.push_back(res_req);
}
void
PipelineStage::unsetResStall(ResReqPtr res_req, unsigned tid)
PipelineStage::unsetResStall(ResReqPtr res_req, ThreadID tid)
{
// Search through stalls to find stalling request and then
// remove it
@ -731,11 +728,11 @@ PipelineStage::unsetResStall(ResReqPtr res_req, unsigned tid)
void
PipelineStage::processStage(bool &status_change)
{
list<unsigned>::iterator threads = (*activeThreads).begin();
list<ThreadID>::iterator threads = activeThreads->begin();
//Check stall and squash signals.
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
while (threads != activeThreads->end()) {
ThreadID tid = *threads++;
DPRINTF(InOrderStage,"Processing [tid:%i]\n",tid);
status_change = checkSignalsAndUpdate(tid) || status_change;
@ -756,7 +753,7 @@ PipelineStage::processStage(bool &status_change)
}
void
PipelineStage::processThread(bool &status_change, unsigned tid)
PipelineStage::processThread(bool &status_change, ThreadID tid)
{
// If status is Running or idle,
// call stageInsts()
@ -801,7 +798,7 @@ PipelineStage::processThread(bool &status_change, unsigned tid)
void
PipelineStage::processInsts(unsigned tid)
PipelineStage::processInsts(ThreadID tid)
{
// Instructions can come either from the skid buffer or the list of
// instructions coming from fetch, depending on stage's status.
@ -888,9 +885,9 @@ bool
PipelineStage::processInstSchedule(DynInstPtr inst)
{
bool last_req_completed = true;
int tid;
tid = inst->readTid();
#if TRACING_ON
ThreadID tid = inst->readTid();
#endif
if (inst->nextResStage() == stageNum) {
int res_stage_num = inst->nextResStage();
@ -951,7 +948,7 @@ PipelineStage::sendInstToNextStage(DynInstPtr inst)
inst->nextStage++;
bool success = false;
int tid = inst->readTid();
ThreadID tid = inst->readTid();
int next_stage = inst->nextStage;
int prev_stage = next_stage - 1;
@ -1012,8 +1009,7 @@ PipelineStage::dumpInsts()
{
cprintf("Insts in Stage %i skidbuffers\n",stageNum);
for (int tid=0; tid < ThePipeline::MaxThreads; tid++) {
for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
std::queue<DynInstPtr> copy_buff(skidBuffer[tid]);
while (!copy_buff.empty()) {

40
src/cpu/inorder/pipeline_stage.hh
View file

@ -80,7 +80,7 @@ class PipelineStage
unsigned stageWidth;
/** Number of Threads*/
unsigned numThreads;
ThreadID numThreads;
/** Stage status. */
StageStatus _status;
@ -108,7 +108,7 @@ class PipelineStage
/** Sets CPU pointer. */
virtual void setCPU(InOrderCPU *cpu_ptr);
virtual void scheduleStageStart(int delay, int tid) { }
virtual void scheduleStageStart(int delay, ThreadID tid) { }
/** Sets the main backwards communication time buffer pointer. */
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
@ -120,11 +120,11 @@ class PipelineStage
void setNextStageQueue(TimeBuffer<InterStageStruct> *next_stage_ptr);
/** Sets pointer to list of active threads. */
void setActiveThreads(std::list<unsigned> *at_ptr);
void setActiveThreads(std::list<ThreadID> *at_ptr);
bool nextStageQueueValid(int stage_num);
bool isBlocked(unsigned tid);
bool isBlocked(ThreadID tid);
/** Changes the status of this stage to active, and indicates this
* to the CPU.
@ -148,13 +148,13 @@ class PipelineStage
virtual void tick();
/** Set a resource stall in the pipeline-stage */
void setResStall(ResReqPtr res_req, unsigned tid);
void setResStall(ResReqPtr res_req, ThreadID tid);
/** Unset a resource stall in the pipeline-stage */
void unsetResStall(ResReqPtr res_req, unsigned tid);
void unsetResStall(ResReqPtr res_req, ThreadID tid);
/** Remove all stall signals for a particular thread; */
virtual void removeStalls(unsigned tid);
virtual void removeStalls(ThreadID tid);
/** Is there room in the stage buffer? */
int stageBufferAvail();
@ -168,14 +168,14 @@ class PipelineStage
* change (ie switching from from blocking to unblocking).
* @param tid Thread id to stage instructions from.
*/
virtual void processThread(bool &status_change, unsigned tid);
virtual void processThread(bool &status_change, ThreadID tid);
/** Processes instructions from fetch and passes them on to rename.
* Decoding of instructions actually happens when they are created in
* fetch, so this function mostly checks if PC-relative branches are
* correct.
*/
virtual void processInsts(unsigned tid);
virtual void processInsts(ThreadID tid);
/** Process all resources on an instruction's resource schedule */
virtual bool processInstSchedule(DynInstPtr inst);
@ -189,7 +189,7 @@ class PipelineStage
/** Inserts a thread's instructions into the skid buffer, to be staged
* once stage unblocks.
*/
virtual void skidInsert(unsigned tid);
virtual void skidInsert(ThreadID tid);
/** Total size of all skid buffers */
int skidSize();
@ -206,13 +206,13 @@ class PipelineStage
void sortInsts();
/** Reads all stall signals from the backwards communication timebuffer. */
virtual void readStallSignals(unsigned tid);
virtual void readStallSignals(ThreadID tid);
/** Checks all input signals and updates stage's status appropriately. */
virtual bool checkSignalsAndUpdate(unsigned tid);
virtual bool checkSignalsAndUpdate(ThreadID tid);
/** Checks all stall signals, and returns if any are true. */
virtual bool checkStall(unsigned tid) const;
virtual bool checkStall(ThreadID tid) const;
/** Returns if there any instructions from the previous stage
* on this cycle.
@ -223,30 +223,30 @@ class PipelineStage
* become blocked.
* @return Returns true if there is a status change.
*/
virtual bool block(unsigned tid);
virtual bool block(ThreadID tid);
void blockDueToBuffer(unsigned tid);
void blockDueToBuffer(ThreadID tid);
/** Switches stage to unblocking if the skid buffer is empty, and
* signals back that stage has unblocked.
* @return Returns true if there is a status change.
*/
virtual bool unblock(unsigned tid);
virtual bool unblock(ThreadID tid);
public:
/** Squashes if there is a PC-relative branch that was predicted
* incorrectly. Sends squash information back to fetch.
*/
virtual void squashDueToBranch(DynInstPtr &inst, unsigned tid);
virtual void squashDueToBranch(DynInstPtr &inst, ThreadID tid);
/** Squash instructions from stage buffer */
virtual void squashPrevStageInsts(InstSeqNum squash_seq_num, unsigned tid);
virtual void squashPrevStageInsts(InstSeqNum squash_seq_num, ThreadID tid);
/** Squashes due to commit signalling a squash. Changes status to
* squashing and clears block/unblock signals as needed.
*/
virtual void squash(InstSeqNum squash_num, unsigned tid);
virtual void squash(InstSeqNum squash_num, ThreadID tid);
void dumpInsts();
@ -257,7 +257,7 @@ class PipelineStage
Trace::InOrderTrace *tracer;
/** List of active thread ids */
std::list<unsigned> *activeThreads;
std::list<ThreadID> *activeThreads;
/** Queue of all instructions coming from previous stage on this cycle. */
std::queue<DynInstPtr> insts[ThePipeline::MaxThreads];

5
src/cpu/inorder/resource.cc
View file

@ -283,7 +283,7 @@ Resource::execute(int slot_idx)
}
void
Resource::deactivateThread(unsigned tid)
Resource::deactivateThread(ThreadID tid)
{
// In the most basic case, deactivation means squashing everything
// from a particular thread
@ -292,7 +292,8 @@ Resource::deactivateThread(unsigned tid)
}
void
Resource::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid)
Resource::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
ThreadID tid)
{
std::vector<int> slot_remove_list;

15
src/cpu/inorder/resource.hh
View file

@ -84,17 +84,17 @@ class Resource {
virtual void regStats();
/** Resources that care about thread activation override this. */
virtual void activateThread(unsigned tid) { }
virtual void activateThread(ThreadID tid) { }
/** Deactivate Thread. Default action is to squash all instructions
* from deactivated thread.
*/
virtual void deactivateThread(unsigned tid);
virtual void deactivateThread(ThreadID tid);
/** Resources that care when an instruction has been graduated
* can override this
*/
virtual void instGraduated(InstSeqNum seq_num,unsigned tid) { }
virtual void instGraduated(InstSeqNum seq_num, ThreadID tid) { }
/** Request usage of this resource. Returns a ResourceRequest object
* with all the necessary resource information
@ -151,7 +151,8 @@ class Resource {
{ panic("writeHint undefined for %s", name()); }
/** Squash All Requests After This Seq Num */
virtual void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid);
virtual void squash(DynInstPtr inst, int stage_num,
InstSeqNum squash_seq_num, ThreadID tid);
/** The number of instructions available that this resource can
* can still process
@ -347,8 +348,8 @@ class ResourceRequest
int getStageNum() { return stageNum; }
/** Set/Get Thread Ids */
void setTid(unsigned _tid) { tid = _tid; }
int getTid() { return tid; }
void setTid(ThreadID _tid) { tid = _tid; }
ThreadID getTid() { return tid; }
/** Instruction this request is for */
DynInstPtr getInst() { return inst; }
@ -393,7 +394,7 @@ class ResourceRequest
protected:
/** Resource Identification */
int tid;
ThreadID tid;
int stageNum;
int resIdx;
int slotNum;

14
src/cpu/inorder/resource_pool.9stage.cc
View file

@ -146,7 +146,8 @@ ResourcePool::request(int res_idx, DynInstPtr inst)
}
void
ResourcePool::squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num, int tid)
ResourcePool::squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num,
ThreadID tid)
{
resources[res_idx]->squash(inst, ThePipeline::NumStages-1, done_seq_num, tid);
}
@ -165,7 +166,7 @@ ResourcePool::slotsInUse(int res_idx)
void
ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
int delay, int res_idx, int tid)
int delay, int res_idx, ThreadID tid)
{
assert(delay >= 0);
@ -246,7 +247,8 @@ ResourcePool::unscheduleEvent(int res_idx, DynInstPtr inst)
}
void
ResourcePool::squashAll(DynInstPtr inst, int stage_num, InstSeqNum done_seq_num, unsigned tid)
ResourcePool::squashAll(DynInstPtr inst, int stage_num,
InstSeqNum done_seq_num, ThreadID tid)
{
DPRINTF(Resource, "[tid:%i] Stage %i squashing all instructions above [sn:%i].\n",
stage_num, tid, done_seq_num);
@ -259,7 +261,7 @@ ResourcePool::squashAll(DynInstPtr inst, int stage_num, InstSeqNum done_seq_num,
}
void
ResourcePool::activateAll(unsigned tid)
ResourcePool::activateAll(ThreadID tid)
{
DPRINTF(Resource, "[tid:%i] Broadcasting Thread Activation to all resources.\n",
tid);
@ -272,7 +274,7 @@ ResourcePool::activateAll(unsigned tid)
}
void
ResourcePool::deactivateAll(unsigned tid)
ResourcePool::deactivateAll(ThreadID tid)
{
DPRINTF(Resource, "[tid:%i] Broadcasting Thread Deactivation to all resources.\n",
tid);
@ -285,7 +287,7 @@ ResourcePool::deactivateAll(unsigned tid)
}
void
ResourcePool::instGraduated(InstSeqNum seq_num,unsigned tid)
ResourcePool::instGraduated(InstSeqNum seq_num, ThreadID tid)
{
DPRINTF(Resource, "[tid:%i] Broadcasting [sn:%i] graduation to all resources.\n",
tid, seq_num);

16
src/cpu/inorder/resource_pool.cc
View file

@ -164,7 +164,8 @@ ResourcePool::request(int res_idx, DynInstPtr inst)
}
void
ResourcePool::squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num, int tid)
ResourcePool::squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num,
ThreadID tid)
{
resources[res_idx]->squash(inst, ThePipeline::NumStages-1, done_seq_num, tid);
}
@ -183,7 +184,7 @@ ResourcePool::slotsInUse(int res_idx)
void
ResourcePool::scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst,
int delay, int res_idx, int tid)
int delay, int res_idx, ThreadID tid)
{
assert(delay >= 0);
@ -261,7 +262,8 @@ ResourcePool::unscheduleEvent(int res_idx, DynInstPtr inst)
}
void
ResourcePool::squashAll(DynInstPtr inst, int stage_num, InstSeqNum done_seq_num, unsigned tid)
ResourcePool::squashAll(DynInstPtr inst, int stage_num,
InstSeqNum done_seq_num, ThreadID tid)
{
DPRINTF(Resource, "[tid:%i] Stage %i squashing all instructions above [sn:%i].\n",
stage_num, tid, done_seq_num);
@ -274,7 +276,7 @@ ResourcePool::squashAll(DynInstPtr inst, int stage_num, InstSeqNum done_seq_num,
}
void
ResourcePool::activateAll(unsigned tid)
ResourcePool::activateAll(ThreadID tid)
{
DPRINTF(Resource, "[tid:%i] Broadcasting Thread Activation to all resources.\n",
tid);
@ -287,7 +289,7 @@ ResourcePool::activateAll(unsigned tid)
}
void
ResourcePool::deactivateAll(unsigned tid)
ResourcePool::deactivateAll(ThreadID tid)
{
DPRINTF(Resource, "[tid:%i] Broadcasting Thread Deactivation to all resources.\n",
tid);
@ -300,7 +302,7 @@ ResourcePool::deactivateAll(unsigned tid)
}
void
ResourcePool::instGraduated(InstSeqNum seq_num,unsigned tid)
ResourcePool::instGraduated(InstSeqNum seq_num, ThreadID tid)
{
DPRINTF(Resource, "[tid:%i] Broadcasting [sn:%i] graduation to all resources.\n",
tid, seq_num);
@ -322,7 +324,7 @@ ResourcePool::ResPoolEvent::ResPoolEvent(ResourcePool *_resPool,
DynInstPtr _inst,
int stage_num,
InstSeqNum seq_num,
unsigned _tid)
ThreadID _tid)
: Event(CPU_Tick_Pri), resPool(_resPool),
eventType(e_type), inst(_inst), seqNum(seq_num),
stageNum(stage_num), tid(_tid)

19
src/cpu/inorder/resource_pool.hh
View file

@ -81,7 +81,7 @@ class ResourcePool {
int stageNum;
unsigned tid;
ThreadID tid;
public:
/** Constructs a resource event. */
@ -93,14 +93,14 @@ class ResourcePool {
DynInstPtr _inst,
int stage_num,
InstSeqNum seq_num,
unsigned _tid);
ThreadID _tid);
/** Set Type of Event To Be Scheduled */
void setEvent(InOrderCPU::CPUEventType e_type,
DynInstPtr _inst,
int stage_num,
InstSeqNum seq_num,
unsigned _tid)
ThreadID _tid)
{
eventType = e_type;
inst = _inst;
@ -153,20 +153,21 @@ class ResourcePool {
ResReqPtr request(int res_idx, DynInstPtr inst);
/** Squash The Resource */
void squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num, int tid);
void squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num,
ThreadID tid);
/** Squash All Resources in Pool after Done Seq. Num */
void squashAll(DynInstPtr inst, int stage_num,
InstSeqNum done_seq_num, unsigned tid);
InstSeqNum done_seq_num, ThreadID tid);
/** Activate Thread in all resources */
void activateAll(unsigned tid);
void activateAll(ThreadID tid);
/** De-Activate Thread in all resources */
void deactivateAll(unsigned tid);
void deactivateAll(ThreadID tid);
/** Broadcast graduation to all resources */
void instGraduated(InstSeqNum seq_num,unsigned tid);
void instGraduated(InstSeqNum seq_num, ThreadID tid);
/** The number of instructions available that a resource can
* can still process.
@ -178,7 +179,7 @@ class ResourcePool {
/** Schedule resource event, regardless of its current state. */
void scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst = NULL,
int delay = 0, int res_idx = 0, int tid = 0);
int delay = 0, int res_idx = 0, ThreadID tid = 0);
/** UnSchedule resource event, regardless of its current state. */
void unscheduleEvent(int res_idx, DynInstPtr inst);

22
src/cpu/inorder/resources/agen_unit.cc
View file

@ -42,10 +42,11 @@ AGENUnit::execute(int slot_num)
ResourceRequest* agen_req = reqMap[slot_num];
DynInstPtr inst = reqMap[slot_num]->inst;
Fault fault = reqMap[slot_num]->fault;
int tid;
#if TRACING_ON
ThreadID tid = inst->readTid();
#endif
int seq_num = inst->seqNum;
tid = inst->readTid();
agen_req->fault = NoFault;
switch (agen_req->cmd)
@ -54,22 +55,27 @@ AGENUnit::execute(int slot_num)
{
// Load/Store Instruction
if (inst->isMemRef()) {
DPRINTF(InOrderAGEN, "[tid:%i] Generating Address for [sn:%i] (%s).\n",
tid, inst->seqNum, inst->staticInst->getName());
DPRINTF(InOrderAGEN,
"[tid:%i] Generating Address for [sn:%i] (%s).\n",
tid, seq_num, inst->staticInst->getName());
fault = inst->calcEA();
inst->setMemAddr(inst->getEA());
DPRINTF(InOrderAGEN, "[tid:%i] [sn:%i] Effective address calculated to be: "
"%#x.\n", tid, inst->seqNum, inst->getEA());
DPRINTF(InOrderAGEN,
"[tid:%i] [sn:%i] Effective address calculated as: %#x\n",
tid, seq_num, inst->getEA());
if (fault == NoFault) {
agen_req->done();
} else {
fatal("%s encountered while calculating address for [sn:%i]",fault->name(), seq_num);
fatal("%s encountered while calculating address [sn:%i]",
fault->name(), seq_num);
}
} else {
DPRINTF(InOrderAGEN, "[tid:] Ignoring non-memory instruction [sn:%i].\n", tid, seq_num);
DPRINTF(InOrderAGEN,
"[tid:] Ignoring non-memory instruction [sn:%i]\n",
tid, seq_num);
agen_req->done();
}
}

10
src/cpu/inorder/resources/bpred_unit.cc
View file

@ -142,7 +142,7 @@ BPredUnit::takeOverFrom()
bool
BPredUnit::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
BPredUnit::predict(DynInstPtr &inst, Addr &PC, ThreadID tid)
{
// See if branch predictor predicts taken.
// If so, get its target addr either from the BTB or the RAS.
@ -268,7 +268,7 @@ BPredUnit::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
void
BPredUnit::update(const InstSeqNum &done_sn, unsigned tid)
BPredUnit::update(const InstSeqNum &done_sn, ThreadID tid)
{
DPRINTF(Resource, "BranchPred: [tid:%i]: Commiting branches until sequence"
"number %lli.\n", tid, done_sn);
@ -286,7 +286,7 @@ BPredUnit::update(const InstSeqNum &done_sn, unsigned tid)
void
BPredUnit::squash(const InstSeqNum &squashed_sn, unsigned tid)
BPredUnit::squash(const InstSeqNum &squashed_sn, ThreadID tid)
{
History &pred_hist = predHist[tid];
@ -321,8 +321,8 @@ BPredUnit::squash(const InstSeqNum &squashed_sn, unsigned tid)
void
BPredUnit::squash(const InstSeqNum &squashed_sn,
const Addr &corr_target,
const bool actually_taken,
unsigned tid)
bool actually_taken,
ThreadID tid)
{
// Now that we know that a branch was mispredicted, we need to undo
// all the branches that have been seen up until this branch and

14
src/cpu/inorder/resources/bpred_unit.hh
View file

@ -87,7 +87,7 @@ class BPredUnit
* @param tid The thread id.
* @return Returns if the branch is taken or not.
*/
bool predict(ThePipeline::DynInstPtr &inst, Addr &PC, unsigned tid);
bool predict(ThePipeline::DynInstPtr &inst, Addr &PC, ThreadID tid);
// @todo: Rename this function.
void BPUncond(void * &bp_history);
@ -98,7 +98,7 @@ class BPredUnit
* @param done_sn The sequence number to commit any older updates up until.
* @param tid The thread id.
*/
void update(const InstSeqNum &done_sn, unsigned tid);
void update(const InstSeqNum &done_sn, ThreadID tid);
/**
* Squashes all outstanding updates until a given sequence number.
@ -106,7 +106,7 @@ class BPredUnit
* until.
* @param tid The thread id.
*/
void squash(const InstSeqNum &squashed_sn, unsigned tid);
void squash(const InstSeqNum &squashed_sn, ThreadID tid);
/**
* Squashes all outstanding updates until a given sequence number, and
@ -118,7 +118,7 @@ class BPredUnit
* @param tid The thread id.
*/
void squash(const InstSeqNum &squashed_sn, const Addr &corr_target,
bool actually_taken, unsigned tid);
bool actually_taken, ThreadID tid);
/**
* @param bp_history Pointer to the history object. The predictor
@ -178,8 +178,8 @@ class BPredUnit
* information needed to update the predictor, BTB, and RAS.
*/
PredictorHistory(const InstSeqNum &seq_num, const Addr &inst_PC,
const bool pred_taken, void *bp_history,
const unsigned _tid)
bool pred_taken, void *bp_history,
ThreadID _tid)
: seqNum(seq_num), PC(inst_PC), RASTarget(0),
RASIndex(0), tid(_tid), predTaken(pred_taken), usedRAS(0),
wasCall(0), bpHistory(bp_history)
@ -198,7 +198,7 @@ class BPredUnit
unsigned RASIndex;
/** The thread id. */
unsigned tid;
ThreadID tid;
/** Whether or not it was predicted taken. */
bool predTaken;

6
src/cpu/inorder/resources/branch_predictor.cc
View file

@ -65,7 +65,7 @@ BranchPredictor::execute(int slot_num)
ResourceRequest* bpred_req = reqMap[slot_num];
DynInstPtr inst = bpred_req->inst;
int tid = inst->readTid();
ThreadID tid = inst->readTid();
int seq_num = inst->seqNum;
//int stage_num = bpred_req->getStageNum();
@ -136,14 +136,14 @@ BranchPredictor::execute(int slot_num)
void
BranchPredictor::squash(DynInstPtr inst, int squash_stage,
InstSeqNum squash_seq_num, unsigned tid)
InstSeqNum squash_seq_num, ThreadID tid)
{
DPRINTF(InOrderBPred, "Squashing...\n");
branchPred.squash(squash_seq_num, tid);
}
void
BranchPredictor::instGraduated(InstSeqNum seq_num,unsigned tid)
BranchPredictor::instGraduated(InstSeqNum seq_num, ThreadID tid)
{
branchPred.update(seq_num, tid);
}

4
src/cpu/inorder/resources/branch_predictor.hh
View file

@ -61,9 +61,9 @@ class BranchPredictor : public Resource {
virtual void execute(int slot_num);
virtual void squash(DynInstPtr inst, int stage_num,
InstSeqNum squash_seq_num, unsigned tid);
InstSeqNum squash_seq_num, ThreadID tid);
virtual void instGraduated(InstSeqNum seq_num,unsigned tid);
virtual void instGraduated(InstSeqNum seq_num, ThreadID tid);
protected:
/** List of instructions this resource is currently

46
src/cpu/inorder/resources/cache_unit.cc
View file

@ -258,17 +258,10 @@ Fault
CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
int flags, TheISA::TLB::Mode tlb_mode)
{
int tid;
int seq_num;
Addr aligned_addr;
unsigned stage_num;
unsigned slot_idx;
tid = inst->readTid();
seq_num = inst->seqNum;
aligned_addr = inst->getMemAddr();
stage_num = cache_req->getStageNum();
slot_idx = cache_req->getSlot();
ThreadID tid = inst->readTid();
Addr aligned_addr = inst->getMemAddr();
unsigned stage_num = cache_req->getStageNum();
unsigned slot_idx = cache_req->getSlot();
if (tlb_mode == TheISA::TLB::Execute) {
inst->fetchMemReq = new Request(inst->readTid(), aligned_addr,
@ -290,7 +283,7 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
if (cache_req->fault != NoFault) {
DPRINTF(InOrderTLB, "[tid:%i]: %s encountered while translating "
"addr:%08p for [sn:%i].\n", tid, cache_req->fault->name(),
cache_req->memReq->getVaddr(), seq_num);
cache_req->memReq->getVaddr(), inst->seqNum);
cpu->pipelineStage[stage_num]->setResStall(cache_req, tid);
@ -303,7 +296,7 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
cpu->trap(cache_req->fault, tid);
} else {
DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i] virt. addr %08p translated "
"to phys. addr:%08p.\n", tid, seq_num,
"to phys. addr:%08p.\n", tid, inst->seqNum,
cache_req->memReq->getVaddr(),
cache_req->memReq->getPaddr());
}
@ -361,11 +354,11 @@ CacheUnit::execute(int slot_num)
assert(cache_req);
DynInstPtr inst = cache_req->inst;
int tid;
int seq_num;
#if TRACING_ON
ThreadID tid = inst->readTid();
int seq_num = inst->seqNum;
#endif
tid = inst->readTid();
seq_num = inst->seqNum;
cache_req->fault = NoFault;
switch (cache_req->cmd)
@ -381,8 +374,8 @@ CacheUnit::execute(int slot_num)
if (cache_req->fault == NoFault) {
DPRINTF(InOrderCachePort,
"[tid:%u]: Initiating fetch access to %s for addr. %08p\n",
tid, name(), cache_req->inst->getMemAddr());
"[tid:%u]: Initiating fetch access to %s for addr. %08p\n",
tid, name(), cache_req->inst->getMemAddr());
cache_req->reqData = new uint8_t[acc_size];
@ -499,9 +492,9 @@ Fault
CacheUnit::doCacheAccess(DynInstPtr inst, uint64_t *write_res)
{
Fault fault = NoFault;
int tid = 0;
tid = inst->readTid();
#if TRACING_ON
ThreadID tid = inst->readTid();
#endif
CacheReqPtr cache_req
= dynamic_cast<CacheReqPtr>(reqMap[inst->getCurResSlot()]);
@ -627,10 +620,7 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
// Get resource request info
unsigned stage_num = cache_req->getStageNum();
DynInstPtr inst = cache_req->inst;
unsigned tid;
tid = cache_req->inst->readTid();
ThreadID tid = cache_req->inst->readTid();
if (!cache_req->isSquashed()) {
if (inst->resSched.top()->cmd == CompleteFetch) {
@ -752,7 +742,7 @@ CacheUnitEvent::process()
{
DynInstPtr inst = resource->reqMap[slotIdx]->inst;
int stage_num = resource->reqMap[slotIdx]->getStageNum();
int tid = inst->threadNumber;
ThreadID tid = inst->threadNumber;
CacheReqPtr req_ptr = dynamic_cast<CacheReqPtr>(resource->reqMap[slotIdx]);
DPRINTF(InOrderTLB, "Waking up from TLB Miss caused by [sn:%i].\n",
@ -774,7 +764,7 @@ CacheUnitEvent::process()
void
CacheUnit::squash(DynInstPtr inst, int stage_num,
InstSeqNum squash_seq_num, unsigned tid)
InstSeqNum squash_seq_num, ThreadID tid)
{
vector<int> slot_remove_list;

2
src/cpu/inorder/resources/cache_unit.hh
View file

@ -144,7 +144,7 @@ class CacheUnit : public Resource
void execute(int slot_num);
void squash(DynInstPtr inst, int stage_num,
InstSeqNum squash_seq_num, unsigned tid);
InstSeqNum squash_seq_num, ThreadID tid);
/** Processes cache completion event. */
void processCacheCompletion(PacketPtr pkt);

24
src/cpu/inorder/resources/decode_unit.cc
View file

@ -39,7 +39,7 @@ DecodeUnit::DecodeUnit(std::string res_name, int res_id, int res_width,
int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
: Resource(res_name, res_id, res_width, res_latency, _cpu)
{
for (int tid = 0; tid < MaxThreads; tid++) {
for (ThreadID tid = 0; tid < MaxThreads; tid++) {
regDepMap[tid] = &cpu->archRegDepMap[tid];
}
}
@ -50,10 +50,8 @@ DecodeUnit::execute(int slot_num)
ResourceRequest* decode_req = reqMap[slot_num];
DynInstPtr inst = reqMap[slot_num]->inst;
Fault fault = reqMap[slot_num]->fault;
int tid, seq_num;
ThreadID tid = inst->readTid();
tid = inst->readTid();
seq_num = inst->seqNum;
decode_req->fault = NoFault;
switch (decode_req->cmd)
@ -63,13 +61,17 @@ DecodeUnit::execute(int slot_num)
bool done_sked = ThePipeline::createBackEndSchedule(inst);
if (done_sked) {
DPRINTF(InOrderDecode, "[tid:%i]: Setting Destination Register(s) for [sn:%i].\n",
tid, seq_num);
DPRINTF(InOrderDecode,
"[tid:%i]: Setting Destination Register(s) for [sn:%i].\n",
tid, inst->seqNum);
regDepMap[tid]->insert(inst);
decode_req->done();
} else {
DPRINTF(Resource,"[tid:%i] Static Inst not available to decode. Unable to create "
"schedule for instruction [sn:%i] \n", tid, inst->seqNum);
DPRINTF(Resource,
"[tid:%i] Static Inst not available to decode.\n", tid);
DPRINTF(Resource,
"Unable to create schedule for instruction [sn:%i] \n",
inst->seqNum);
DPRINTF(InOrderStall, "STALL: \n");
decode_req->done(false);
}
@ -83,9 +85,11 @@ DecodeUnit::execute(int slot_num)
void
DecodeUnit::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid)
DecodeUnit::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
ThreadID tid)
{
DPRINTF(InOrderDecode, "[tid:%i]: Updating due to squash from stage %i after [sn:%i].\n",
DPRINTF(InOrderDecode,
"[tid:%i]: Updating due to squash from stage %i after [sn:%i].\n",
tid, stage_num, squash_seq_num);
//cpu->removeInstsUntil(squash_seq_num, tid);

3
src/cpu/inorder/resources/decode_unit.hh
View file

@ -57,7 +57,8 @@ class DecodeUnit : public Resource {
virtual void execute(int slot_num);
void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid);
void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
ThreadID tid);
RegDepMap *regDepMap[ThePipeline::MaxThreads];

4
src/cpu/inorder/resources/execution_unit.cc
View file

@ -63,7 +63,7 @@ ExecutionUnit::execute(int slot_num)
ResourceRequest* exec_req = reqMap[slot_num];
DynInstPtr inst = reqMap[slot_num]->inst;
Fault fault = reqMap[slot_num]->fault;
int tid = inst->readTid();
ThreadID tid = inst->readTid();
int seq_num = inst->seqNum;
exec_req->fault = NoFault;
@ -89,7 +89,7 @@ ExecutionUnit::execute(int slot_num)
// that got squashed.
if (inst->mispredicted()) {
int stage_num = exec_req->getStageNum();
int tid = inst->readTid();
ThreadID tid = inst->readTid();
// If it's a branch ...
if (inst->isDirectCtrl()) {

14
src/cpu/inorder/resources/fetch_seq_unit.cc
View file

@ -41,7 +41,7 @@ FetchSeqUnit::FetchSeqUnit(std::string res_name, int res_id, int res_width,
: Resource(res_name, res_id, res_width, res_latency, _cpu),
instSize(sizeof(MachInst))
{
for (int tid = 0; tid < ThePipeline::MaxThreads; tid++) {
for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
delaySlotInfo[tid].numInsts = 0;
delaySlotInfo[tid].targetReady = false;
@ -68,7 +68,7 @@ FetchSeqUnit::execute(int slot_num)
// for performance considerations
ResourceRequest* fs_req = reqMap[slot_num];
DynInstPtr inst = fs_req->inst;
int tid = inst->readTid();
ThreadID tid = inst->readTid();
int stage_num = fs_req->getStageNum();
int seq_num = inst->seqNum;
@ -202,7 +202,7 @@ FetchSeqUnit::execute(int slot_num)
}
inline void
FetchSeqUnit::squashAfterInst(DynInstPtr inst, int stage_num, unsigned tid)
FetchSeqUnit::squashAfterInst(DynInstPtr inst, int stage_num, ThreadID tid)
{
// Squash In Pipeline Stage
cpu->pipelineStage[stage_num]->squashDueToBranch(inst, tid);
@ -216,7 +216,7 @@ FetchSeqUnit::squashAfterInst(DynInstPtr inst, int stage_num, unsigned tid)
}
void
FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
InstSeqNum squash_seq_num, unsigned tid)
InstSeqNum squash_seq_num, ThreadID tid)
{
DPRINTF(InOrderFetchSeq, "[tid:%i]: Updating due to squash from stage %i.\n",
tid, squash_stage);
@ -302,7 +302,7 @@ FetchSeqUnit::FetchSeqEvent::process()
void
FetchSeqUnit::activateThread(unsigned tid)
FetchSeqUnit::activateThread(ThreadID tid)
{
pcValid[tid] = true;
@ -317,7 +317,7 @@ FetchSeqUnit::activateThread(unsigned tid)
}
void
FetchSeqUnit::deactivateThread(unsigned tid)
FetchSeqUnit::deactivateThread(ThreadID tid)
{
delaySlotInfo[tid].numInsts = 0;
delaySlotInfo[tid].targetReady = false;
@ -328,7 +328,7 @@ FetchSeqUnit::deactivateThread(unsigned tid)
squashSeqNum[tid] = (InstSeqNum)-1;
lastSquashCycle[tid] = 0;
std::list<unsigned>::iterator thread_it = find(cpu->fetchPriorityList.begin(),
list<ThreadID>::iterator thread_it = find(cpu->fetchPriorityList.begin(),
cpu->fetchPriorityList.end(),
tid);

8
src/cpu/inorder/resources/fetch_seq_unit.hh
View file

@ -56,8 +56,8 @@ class FetchSeqUnit : public Resource {
virtual ~FetchSeqUnit() {}
virtual void init();
virtual void activateThread(unsigned tid);
virtual void deactivateThread(unsigned tid);
virtual void activateThread(ThreadID tid);
virtual void deactivateThread(ThreadID tid);
virtual void execute(int slot_num);
/** Override default Resource squash sequence. This actually,
@ -65,10 +65,10 @@ class FetchSeqUnit : public Resource {
* info
*/
virtual void squash(DynInstPtr inst, int squash_stage,
InstSeqNum squash_seq_num, unsigned tid);
InstSeqNum squash_seq_num, ThreadID tid);
inline void squashAfterInst(DynInstPtr inst, int stage_num, unsigned tid);
inline void squashAfterInst(DynInstPtr inst, int stage_num, ThreadID tid);
protected:
unsigned instSize;

20
src/cpu/inorder/resources/graduation_unit.cc
View file

@ -39,7 +39,7 @@ GraduationUnit::GraduationUnit(std::string res_name, int res_id, int res_width,
lastCycleGrad(0), numCycleGrad(0)
{
for (int tid = 0; tid < ThePipeline::MaxThreads; tid++) {
for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
nonSpecInstActive[tid] = &cpu->nonSpecInstActive[tid];
nonSpecSeqNum[tid] = &cpu->nonSpecSeqNum[tid];
}
@ -51,10 +51,7 @@ GraduationUnit::execute(int slot_num)
ResourceRequest* grad_req = reqMap[slot_num];
DynInstPtr inst = reqMap[slot_num]->inst;
Fault fault = reqMap[slot_num]->fault;
int tid, seq_num;
tid = inst->readTid();
seq_num = inst->seqNum;
ThreadID tid = inst->readTid();
int stage_num = inst->resSched.top()->stageNum;
grad_req->fault = NoFault;
@ -70,15 +67,17 @@ GraduationUnit::execute(int slot_num)
lastCycleGrad = curTick;
numCycleGrad = 0;
} else if (numCycleGrad > width) {
DPRINTF(InOrderGraduation, "Graduation bandwidth reached for this cycle.\n");
DPRINTF(InOrderGraduation,
"Graduation bandwidth reached for this cycle.\n");
return;
}
// Make sure this is the last thing on the resource schedule
assert(inst->resSched.size() == 1);
DPRINTF(InOrderGraduation, "[tid:%i] Graduating instruction [sn:%i].\n",
tid, seq_num);
DPRINTF(InOrderGraduation,
"[tid:%i] Graduating instruction [sn:%i].\n",
tid, inst->seqNum);
DPRINTF(RefCount, "Refcount = %i.\n", 0/*inst->curCount()*/);
@ -87,8 +86,9 @@ GraduationUnit::execute(int slot_num)
// @TODO: Fix this functionality. Probably too conservative.
if (inst->isNonSpeculative()) {
*nonSpecInstActive[tid] = false;
DPRINTF(InOrderGraduation, "[tid:%i] Non-speculative instruction [sn:%i] has graduated.\n",
tid, seq_num);
DPRINTF(InOrderGraduation,
"[tid:%i] Non-speculative inst [sn:%i] graduated\n",
tid, inst->seqNum);
}
if (inst->traceData) {

18
src/cpu/inorder/resources/inst_buffer.cc
View file

@ -60,11 +60,9 @@ InstBuffer::execute(int slot_idx)
{
ResReqPtr ib_req = reqMap[slot_idx];
DynInstPtr inst = ib_req->inst;
int tid, seq_num, stage_num;
ThreadID tid = inst->readTid();
int stage_num = ib_req->getStageNum();
tid = inst->readTid();
seq_num = inst->seqNum;
stage_num = ib_req->getStageNum();
ib_req->fault = NoFault;
switch (ib_req->cmd)
@ -121,12 +119,12 @@ InstBuffer::execute(int slot_idx)
if (instList.size() < width) {
DPRINTF(InOrderInstBuffer, "[tid:%i]: Inserting [sn:%i] into buffer.\n",
tid, seq_num);
tid, inst->seqNum);
insert(inst);
inserted = true;
} else {
DPRINTF(InOrderInstBuffer, "[tid:%i]: Denying [sn:%i] request because "
"buffer is full.\n", tid, seq_num);
"buffer is full.\n", tid, inst->seqNum);
std::list<DynInstPtr>::iterator list_it = instList.begin();
@ -145,7 +143,7 @@ InstBuffer::execute(int slot_idx)
case RemoveInst:
{
DPRINTF(InOrderInstBuffer, "[tid:%i]: Removing [sn:%i] from buffer.\n",
tid, seq_num);
tid, inst->seqNum);
remove(inst);
ib_req->done();
}
@ -180,20 +178,20 @@ InstBuffer::remove(DynInstPtr inst)
}
void
InstBuffer::pop(unsigned tid)
InstBuffer::pop(ThreadID tid)
{
instList.pop_front();
}
ThePipeline::DynInstPtr
InstBuffer::top(unsigned tid)
InstBuffer::top(ThreadID tid)
{
return instList.front();
}
void
InstBuffer::squash(DynInstPtr inst, int stage_num,
InstSeqNum squash_seq_num, unsigned tid)
InstSeqNum squash_seq_num, ThreadID tid)
{
queue<list<DynInstPtr>::iterator> remove_list;
list<DynInstPtr>::iterator list_it = instList.begin();

6
src/cpu/inorder/resources/inst_buffer.hh
View file

@ -67,12 +67,12 @@ class InstBuffer : public Resource {
virtual void remove(DynInstPtr inst);
virtual void pop(unsigned tid);
virtual void pop(ThreadID tid);
virtual DynInstPtr top(unsigned tid);
virtual DynInstPtr top(ThreadID tid);
virtual void squash(DynInstPtr inst, int stage_num,
InstSeqNum squash_seq_num, unsigned tid);
InstSeqNum squash_seq_num, ThreadID tid);
protected:
/** List of instructions this resource is currently
* processing.

4
src/cpu/inorder/resources/inst_buffer_new.cc
View file

@ -67,7 +67,7 @@ InstBuffer::execute(int slot_idx)
assert(ib_req);
DynInstPtr inst = ib_req->inst;
int tid = inst->readTid();
ThreadID tid = inst->readTid();
int seq_num = inst->seqNum;
ib_req->fault = NoFault;
@ -128,7 +128,7 @@ InstBuffer::top()
{ return instList.front(); }
void
InstBuffer::squash(InstSeqNum squash_seq_num, unsigned tid)
InstBuffer::squash(InstSeqNum squash_seq_num, ThreadID tid)
{
list<DynInstPtr>::iterator list_it = instList.begin();
list<DynInstPtr>::iterator list_end = instList.end();

2
src/cpu/inorder/resources/inst_buffer_new.hh
View file

@ -71,7 +71,7 @@ class InstBuffer : public Resource {
virtual DynInstPtr top();
virtual void squash(InstSeqNum squash_seq_num, unsigned tid);
virtual void squash(InstSeqNum squash_seq_num, ThreadID tid);
protected:
/** List of instructions this resource is currently

4
src/cpu/inorder/resources/mult_div_unit.cc
View file

@ -174,7 +174,7 @@ MultDivUnit::execute(int slot_num)
DynInstPtr inst = reqMap[slot_num]->inst;
Fault fault = reqMap[slot_num]->fault;
//int tid = inst->readTid();
//ThreadID tid = inst->readTid();
//int seq_num = inst->seqNum;
switch (mult_div_req->cmd)
@ -248,7 +248,7 @@ MultDivUnit::exeMulDiv(int slot_num)
ResourceRequest* mult_div_req = reqMap[slot_num];
DynInstPtr inst = reqMap[slot_num]->inst;
Fault fault = reqMap[slot_num]->fault;
int tid = inst->readTid();
ThreadID tid = inst->readTid();
int seq_num = inst->seqNum;
fault = inst->execute();

12
src/cpu/inorder/resources/tlb_unit.cc
View file

@ -101,11 +101,9 @@ TLBUnit::execute(int slot_idx)
assert(tlb_req != 0x0);
DynInstPtr inst = tlb_req->inst;
int tid, seq_num, stage_num;
tid = inst->readTid();
seq_num = inst->seqNum;
stage_num = tlb_req->getStageNum();
ThreadID tid = inst->readTid();
int seq_num = inst->seqNum;
int stage_num = tlb_req->getStageNum();
tlb_req->fault = NoFault;
@ -202,7 +200,7 @@ TLBUnitEvent::process()
{
DynInstPtr inst = resource->reqMap[slotIdx]->inst;
int stage_num = resource->reqMap[slotIdx]->getStageNum();
int tid = inst->threadNumber;
ThreadID tid = inst->threadNumber;
DPRINTF(InOrderTLB, "Waking up from TLB Miss caused by [sn:%i].\n",
inst->seqNum);
@ -224,7 +222,7 @@ TLBUnitEvent::process()
void
TLBUnit::squash(DynInstPtr inst, int stage_num,
InstSeqNum squash_seq_num, unsigned tid)
InstSeqNum squash_seq_num, ThreadID tid)
{
//@TODO: Figure out a way to consolidate common parts
// of this squash code

3
src/cpu/inorder/resources/tlb_unit.hh
View file

@ -67,7 +67,8 @@ class TLBUnit : public Resource
virtual void execute(int slot_num);
void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid);
void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
ThreadID tid);
bool tlbBlocked[ThePipeline::MaxThreads];

7
src/cpu/inorder/resources/use_def.cc
View file

@ -45,7 +45,7 @@ UseDefUnit::UseDefUnit(string res_name, int res_id, int res_width,
: Resource(res_name, res_id, res_width, res_latency, _cpu),
maxSeqNum((InstSeqNum)-1)
{
for (int tid = 0; tid < ThePipeline::MaxThreads; tid++) {
for (ThreadID tid = 0; tid < ThePipeline::MaxThreads; tid++) {
nonSpecInstActive[tid] = &cpu->nonSpecInstActive[tid];
nonSpecSeqNum[tid] = &cpu->nonSpecSeqNum[tid];
@ -99,7 +99,7 @@ UseDefUnit::execute(int slot_idx)
assert(ud_req);
DynInstPtr inst = ud_req->inst;
int tid = inst->readTid();
ThreadID tid = inst->readTid();
int seq_num = inst->seqNum;
int ud_idx = ud_req->useDefIdx;
@ -306,7 +306,8 @@ UseDefUnit::execute(int slot_idx)
}
void
UseDefUnit::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid)
UseDefUnit::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
ThreadID tid)
{
DPRINTF(InOrderUseDef, "[tid:%i]: Updating Due To Squash After [sn:%i].\n",
tid, squash_seq_num);

3
src/cpu/inorder/resources/use_def.hh
View file

@ -65,7 +65,8 @@ class UseDefUnit : public Resource {
virtual void execute(int slot_num);
virtual void squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num, unsigned tid);
virtual void squash(DynInstPtr inst, int stage_num,
InstSeqNum squash_seq_num, ThreadID tid);
const InstSeqNum maxSeqNum;

5
src/cpu/inorder/thread_context.cc
View file

@ -175,7 +175,7 @@ InOrderThreadContext::readFloatRegBits(int reg_idx)
}
uint64_t
InOrderThreadContext::readRegOtherThread(int reg_idx, unsigned tid)
InOrderThreadContext::readRegOtherThread(int reg_idx, ThreadID tid)
{
return cpu->readRegOtherThread(reg_idx, tid);
}
@ -212,7 +212,8 @@ InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val)
}
void
InOrderThreadContext::setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid)
InOrderThreadContext::setRegOtherThread(int misc_reg, const MiscReg &val,
ThreadID tid)
{
cpu->setRegOtherThread(misc_reg, val, tid);
}

5
src/cpu/inorder/thread_context.hh
View file

@ -160,7 +160,7 @@ class InOrderThreadContext : public ThreadContext
virtual FloatRegBits readFloatRegBits(int reg_idx);
virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid);
virtual uint64_t readRegOtherThread(int misc_reg, ThreadID tid);
/** Sets an integer register to a value. */
virtual void setIntReg(int reg_idx, uint64_t val);
@ -173,7 +173,8 @@ class InOrderThreadContext : public ThreadContext
virtual void setFloatRegBits(int reg_idx, FloatRegBits val);
virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid);
virtual void setRegOtherThread(int misc_reg, const MiscReg &val,
ThreadID tid);
/** Reads this thread's PC. */
virtual uint64_t readPC()

6
src/cpu/inorder/thread_state.hh
View file

@ -67,8 +67,10 @@ class InOrderThreadState : public ThreadState {
bool trapPending;
InOrderThreadState(InOrderCPU *_cpu, int _thread_num, Process *_process, int _asid)
: ThreadState(reinterpret_cast<BaseCPU*>(_cpu), 0/*_thread_num*/, _process, 0/*_asid*/),
InOrderThreadState(InOrderCPU *_cpu, ThreadID _thread_num,
Process *_process, int _asid)
: ThreadState(reinterpret_cast<BaseCPU*>(_cpu), 0/*_thread_num*/,
_process, 0/*_asid*/),
cpu(_cpu), inSyscall(0), trapPending(0)
{ }

14
src/cpu/o3/bpred_unit.hh
View file

@ -88,7 +88,7 @@ class BPredUnit
* @param tid The thread id.
* @return Returns if the branch is taken or not.
*/
bool predict(DynInstPtr &inst, Addr &PC, unsigned tid);
bool predict(DynInstPtr &inst, Addr &PC, ThreadID tid);
// @todo: Rename this function.
void BPUncond(void * &bp_history);
@ -99,7 +99,7 @@ class BPredUnit
* @param done_sn The sequence number to commit any older updates up until.
* @param tid The thread id.
*/
void update(const InstSeqNum &done_sn, unsigned tid);
void update(const InstSeqNum &done_sn, ThreadID tid);
/**
* Squashes all outstanding updates until a given sequence number.
@ -107,7 +107,7 @@ class BPredUnit
* until.
* @param tid The thread id.
*/
void squash(const InstSeqNum &squashed_sn, unsigned tid);
void squash(const InstSeqNum &squashed_sn, ThreadID tid);
/**
* Squashes all outstanding updates until a given sequence number, and
@ -119,7 +119,7 @@ class BPredUnit
* @param tid The thread id.
*/
void squash(const InstSeqNum &squashed_sn, const Addr &corr_target,
bool actually_taken, unsigned tid);
bool actually_taken, ThreadID tid);
/**
* @param bp_history Pointer to the history object. The predictor
@ -179,8 +179,8 @@ class BPredUnit
* information needed to update the predictor, BTB, and RAS.
*/
PredictorHistory(const InstSeqNum &seq_num, const Addr &inst_PC,
const bool pred_taken, void *bp_history,
const unsigned _tid)
bool pred_taken, void *bp_history,
ThreadID _tid)
: seqNum(seq_num), PC(inst_PC), RASTarget(0),
RASIndex(0), tid(_tid), predTaken(pred_taken), usedRAS(0),
wasCall(0), bpHistory(bp_history)
@ -203,7 +203,7 @@ class BPredUnit
unsigned RASIndex;
/** The thread id. */
unsigned tid;
ThreadID tid;
/** Whether or not it was predicted taken. */
bool predTaken;

10
src/cpu/o3/bpred_unit_impl.hh
View file

@ -144,7 +144,7 @@ BPredUnit<Impl>::takeOverFrom()
template <class Impl>
bool
BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, ThreadID tid)
{
// See if branch predictor predicts taken.
// If so, get its target addr either from the BTB or the RAS.
@ -254,7 +254,7 @@ BPredUnit<Impl>::predict(DynInstPtr &inst, Addr &PC, unsigned tid)
template <class Impl>
void
BPredUnit<Impl>::update(const InstSeqNum &done_sn, unsigned tid)
BPredUnit<Impl>::update(const InstSeqNum &done_sn, ThreadID tid)
{
DPRINTF(Fetch, "BranchPred: [tid:%i]: Committing branches until "
"[sn:%lli].\n", tid, done_sn);
@ -272,7 +272,7 @@ BPredUnit<Impl>::update(const InstSeqNum &done_sn, unsigned tid)
template <class Impl>
void
BPredUnit<Impl>::squash(const InstSeqNum &squashed_sn, unsigned tid)
BPredUnit<Impl>::squash(const InstSeqNum &squashed_sn, ThreadID tid)
{
History &pred_hist = predHist[tid];
@ -311,8 +311,8 @@ template <class Impl>
void
BPredUnit<Impl>::squash(const InstSeqNum &squashed_sn,
const Addr &corr_target,
const bool actually_taken,
unsigned tid)
bool actually_taken,
ThreadID tid)
{
// Now that we know that a branch was mispredicted, we need to undo
// all the branches that have been seen up until this branch and

8
src/cpu/o3/btb.hh
View file

@ -51,7 +51,7 @@ class DefaultBTB
Addr target;
/** The entry's thread id. */
unsigned tid;
ThreadID tid;
/** Whether or not the entry is valid. */
bool valid;
@ -74,14 +74,14 @@ class DefaultBTB
* @param tid The thread id.
* @return Returns the target of the branch.
*/
Addr lookup(const Addr &inst_PC, unsigned tid);
Addr lookup(const Addr &inst_PC, ThreadID tid);
/** Checks if a branch is in the BTB.
* @param inst_PC The address of the branch to look up.
* @param tid The thread id.
* @return Whether or not the branch exists in the BTB.
*/
bool valid(const Addr &inst_PC, unsigned tid);
bool valid(const Addr &inst_PC, ThreadID tid);
/** Updates the BTB with the target of a branch.
* @param inst_PC The address of the branch being updated.
@ -89,7 +89,7 @@ class DefaultBTB
* @param tid The thread id.
*/
void update(const Addr &inst_PC, const Addr &target_PC,
unsigned tid);
ThreadID tid);
private:
/** Returns the index into the BTB, based on the branch's PC.

52
src/cpu/o3/commit.hh
View file

@ -92,10 +92,10 @@ class DefaultCommit
class TrapEvent : public Event {
private:
DefaultCommit<Impl> *commit;
unsigned tid;
ThreadID tid;
public:
TrapEvent(DefaultCommit<Impl> *_commit, unsigned _tid);
TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid);
void process();
const char *description() const;
@ -172,7 +172,7 @@ class DefaultCommit
IEW *iewStage;
/** Sets pointer to list of active threads. */
void setActiveThreads(std::list<unsigned> *at_ptr);
void setActiveThreads(std::list<ThreadID> *at_ptr);
/** Sets pointer to the commited state rename map. */
void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
@ -204,15 +204,15 @@ class DefaultCommit
void commit();
/** Returns the number of free ROB entries for a specific thread. */
unsigned numROBFreeEntries(unsigned tid);
size_t numROBFreeEntries(ThreadID tid);
/** Generates an event to schedule a squash due to a trap. */
void generateTrapEvent(unsigned tid);
void generateTrapEvent(ThreadID tid);
/** Records that commit needs to initiate a squash due to an
* external state update through the TC.
*/
void generateTCEvent(unsigned tid);
void generateTCEvent(ThreadID tid);
private:
/** Updates the overall status of commit with the nextStatus, and
@ -237,13 +237,13 @@ class DefaultCommit
bool changedROBEntries();
/** Squashes all in flight instructions. */
void squashAll(unsigned tid);
void squashAll(ThreadID tid);
/** Handles squashing due to a trap. */
void squashFromTrap(unsigned tid);
void squashFromTrap(ThreadID tid);
/** Handles squashing due to an TC write. */
void squashFromTC(unsigned tid);
void squashFromTC(ThreadID tid);
#if FULL_SYSTEM
/** Handles processing an interrupt. */
@ -268,13 +268,13 @@ class DefaultCommit
void markCompletedInsts();
/** Gets the thread to commit, based on the SMT policy. */
int getCommittingThread();
ThreadID getCommittingThread();
/** Returns the thread ID to use based on a round robin policy. */
int roundRobin();
ThreadID roundRobin();
/** Returns the thread ID to use based on an oldest instruction policy. */
int oldestReady();
ThreadID oldestReady();
public:
/** Returns the PC of the head instruction of the ROB.
@ -283,34 +283,34 @@ class DefaultCommit
Addr readPC() { return PC[0]; }
/** Returns the PC of a specific thread. */
Addr readPC(unsigned tid) { return PC[tid]; }
Addr readPC(ThreadID tid) { return PC[tid]; }
/** Sets the PC of a specific thread. */
void setPC(Addr val, unsigned tid) { PC[tid] = val; }
void setPC(Addr val, ThreadID tid) { PC[tid] = val; }
/** Reads the micro PC of a specific thread. */
Addr readMicroPC(unsigned tid) { return microPC[tid]; }
Addr readMicroPC(ThreadID tid) { return microPC[tid]; }
/** Sets the micro PC of a specific thread */
void setMicroPC(Addr val, unsigned tid) { microPC[tid] = val; }
void setMicroPC(Addr val, ThreadID tid) { microPC[tid] = val; }
/** Reads the next PC of a specific thread. */
Addr readNextPC(unsigned tid) { return nextPC[tid]; }
Addr readNextPC(ThreadID tid) { return nextPC[tid]; }
/** Sets the next PC of a specific thread. */
void setNextPC(Addr val, unsigned tid) { nextPC[tid] = val; }
void setNextPC(Addr val, ThreadID tid) { nextPC[tid] = val; }
/** Reads the next NPC of a specific thread. */
Addr readNextNPC(unsigned tid) { return nextNPC[tid]; }
Addr readNextNPC(ThreadID tid) { return nextNPC[tid]; }
/** Sets the next NPC of a specific thread. */
void setNextNPC(Addr val, unsigned tid) { nextNPC[tid] = val; }
void setNextNPC(Addr val, ThreadID tid) { nextNPC[tid] = val; }
/** Reads the micro PC of a specific thread. */
Addr readNextMicroPC(unsigned tid) { return nextMicroPC[tid]; }
Addr readNextMicroPC(ThreadID tid) { return nextMicroPC[tid]; }
/** Sets the micro PC of a specific thread */
void setNextMicroPC(Addr val, unsigned tid) { nextMicroPC[tid] = val; }
void setNextMicroPC(Addr val, ThreadID tid) { nextMicroPC[tid] = val; }
private:
/** Time buffer interface. */
@ -360,7 +360,7 @@ class DefaultCommit
bool changedROBNumEntries[Impl::MaxThreads];
/** A counter of how many threads are currently squashing. */
int squashCounter;
ThreadID squashCounter;
/** Records if a thread has to squash this cycle due to a trap. */
bool trapSquash[Impl::MaxThreads];
@ -369,7 +369,7 @@ class DefaultCommit
bool tcSquash[Impl::MaxThreads];
/** Priority List used for Commit Policy */
std::list<unsigned> priority_list;
std::list<ThreadID> priority_list;
/** IEW to Commit delay, in ticks. */
unsigned iewToCommitDelay;
@ -394,7 +394,7 @@ class DefaultCommit
unsigned numRobs;
/** Number of Active Threads */
unsigned numThreads;
ThreadID numThreads;
/** Is a drain pending. */
bool drainPending;
@ -443,7 +443,7 @@ class DefaultCommit
bool checkEmptyROB[Impl::MaxThreads];
/** Pointer to the list of active threads. */
std::list<unsigned> *activeThreads;
std::list<ThreadID> *activeThreads;
/** Rename map interface. */
RenameMap *renameMap[Impl::MaxThreads];

177
src/cpu/o3/commit_impl.hh
View file

@ -29,9 +29,6 @@
* Korey Sewell
*/
#include "config/full_system.hh"
#include "config/use_checker.hh"
#include <algorithm>
#include <string>
@ -39,19 +36,22 @@
#include "base/cp_annotate.hh"
#include "base/loader/symtab.hh"
#include "base/timebuf.hh"
#include "config/full_system.hh"
#include "config/use_checker.hh"
#include "cpu/exetrace.hh"
#include "cpu/o3/commit.hh"
#include "cpu/o3/thread_state.hh"
#include "params/DerivO3CPU.hh"
#if USE_CHECKER
#include "cpu/checker/cpu.hh"
#endif
#include "params/DerivO3CPU.hh"
using namespace std;
template <class Impl>
DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
unsigned _tid)
ThreadID _tid)
: Event(CPU_Tick_Pri), commit(_commit), tid(_tid)
{
this->setFlags(AutoDelete);
@ -105,7 +105,7 @@ DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
commitPolicy = RoundRobin;
//Set-Up Priority List
for (int tid=0; tid < numThreads; tid++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
priority_list.push_back(tid);
}
@ -119,15 +119,19 @@ DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
"RoundRobin,OldestReady}");
}
for (int i=0; i < numThreads; i++) {
commitStatus[i] = Idle;
changedROBNumEntries[i] = false;
checkEmptyROB[i] = false;
trapInFlight[i] = false;
committedStores[i] = false;
trapSquash[i] = false;
tcSquash[i] = false;
microPC[i] = nextMicroPC[i] = PC[i] = nextPC[i] = nextNPC[i] = 0;
for (ThreadID tid = 0; tid < numThreads; tid++) {
commitStatus[tid] = Idle;
changedROBNumEntries[tid] = false;
checkEmptyROB[tid] = false;
trapInFlight[tid] = false;
committedStores[tid] = false;
trapSquash[tid] = false;
tcSquash[tid] = false;
microPC[tid] = 0;
nextMicroPC[tid] = 0;
PC[tid] = 0;
nextPC[tid] = 0;
nextNPC[tid] = 0;
}
#if FULL_SYSTEM
interrupt = NoFault;
@ -175,49 +179,49 @@ DefaultCommit<Impl>::regStats()
;
statComInst
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:count")
.desc("Number of instructions committed")
.flags(total)
;
statComSwp
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:swp_count")
.desc("Number of s/w prefetches committed")
.flags(total)
;
statComRefs
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:refs")
.desc("Number of memory references committed")
.flags(total)
;
statComLoads
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:loads")
.desc("Number of loads committed")
.flags(total)
;
statComMembars
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:membars")
.desc("Number of memory barriers committed")
.flags(total)
;
statComBranches
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:branches")
.desc("Number of branches committed")
.flags(total)
;
commitEligible
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:bw_limited")
.desc("number of insts not committed due to BW limits")
.flags(total)
@ -288,7 +292,7 @@ DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
template<class Impl>
void
DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
{
activeThreads = at_ptr;
}
@ -297,9 +301,8 @@ template <class Impl>
void
DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
{
for (int i=0; i < numThreads; i++) {
renameMap[i] = &rm_ptr[i];
}
for (ThreadID tid = 0; tid < numThreads; tid++)
renameMap[tid] = &rm_ptr[tid];
}
template <class Impl>
@ -317,10 +320,10 @@ DefaultCommit<Impl>::initStage()
rob->resetEntries();
// Broadcast the number of free entries.
for (int i=0; i < numThreads; i++) {
toIEW->commitInfo[i].usedROB = true;
toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
toIEW->commitInfo[i].emptyROB = true;
for (ThreadID tid = 0; tid < numThreads; tid++) {
toIEW->commitInfo[tid].usedROB = true;
toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
toIEW->commitInfo[tid].emptyROB = true;
}
// Commit must broadcast the number of free entries it has at the
@ -363,11 +366,11 @@ DefaultCommit<Impl>::takeOverFrom()
switchedOut = false;
_status = Active;
_nextStatus = Inactive;
for (int i=0; i < numThreads; i++) {
commitStatus[i] = Idle;
changedROBNumEntries[i] = false;
trapSquash[i] = false;
tcSquash[i] = false;
for (ThreadID tid = 0; tid < numThreads; tid++) {
commitStatus[tid] = Idle;
changedROBNumEntries[tid] = false;
trapSquash[tid] = false;
tcSquash[tid] = false;
}
squashCounter = 0;
rob->takeOverFrom();
@ -378,11 +381,11 @@ void
DefaultCommit<Impl>::updateStatus()
{
// reset ROB changed variable
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
changedROBNumEntries[tid] = false;
@ -410,11 +413,11 @@ DefaultCommit<Impl>::setNextStatus()
{
int squashes = 0;
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (commitStatus[tid] == ROBSquashing) {
squashes++;
@ -434,11 +437,11 @@ template <class Impl>
bool
DefaultCommit<Impl>::changedROBEntries()
{
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (changedROBNumEntries[tid]) {
return true;
@ -449,15 +452,15 @@ DefaultCommit<Impl>::changedROBEntries()
}
template <class Impl>
unsigned
DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
size_t
DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
{
return rob->numFreeEntries(tid);
}
template <class Impl>
void
DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
{
DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
@ -469,7 +472,7 @@ DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
template <class Impl>
void
DefaultCommit<Impl>::generateTCEvent(unsigned tid)
DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
{
assert(!trapInFlight[tid]);
DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
@ -479,7 +482,7 @@ DefaultCommit<Impl>::generateTCEvent(unsigned tid)
template <class Impl>
void
DefaultCommit<Impl>::squashAll(unsigned tid)
DefaultCommit<Impl>::squashAll(ThreadID tid)
{
// If we want to include the squashing instruction in the squash,
// then use one older sequence number.
@ -516,7 +519,7 @@ DefaultCommit<Impl>::squashAll(unsigned tid)
template <class Impl>
void
DefaultCommit<Impl>::squashFromTrap(unsigned tid)
DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
{
squashAll(tid);
@ -534,7 +537,7 @@ DefaultCommit<Impl>::squashFromTrap(unsigned tid)
template <class Impl>
void
DefaultCommit<Impl>::squashFromTC(unsigned tid)
DefaultCommit<Impl>::squashFromTC(ThreadID tid)
{
squashAll(tid);
@ -565,13 +568,13 @@ DefaultCommit<Impl>::tick()
if (activeThreads->empty())
return;
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
// Check if any of the threads are done squashing. Change the
// status if they are done.
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
// Clear the bit saying if the thread has committed stores
// this cycle.
@ -598,7 +601,7 @@ DefaultCommit<Impl>::tick()
threads = activeThreads->begin();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
// The ROB has more instructions it can commit. Its next status
@ -704,11 +707,11 @@ DefaultCommit<Impl>::commit()
////////////////////////////////////
// Check for any possible squashes, handle them first
////////////////////////////////////
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
// Not sure which one takes priority. I think if we have
// both, that's a bad sign.
@ -794,7 +797,7 @@ DefaultCommit<Impl>::commit()
threads = activeThreads->begin();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (changedROBNumEntries[tid]) {
toIEW->commitInfo[tid].usedROB = true;
@ -855,7 +858,7 @@ DefaultCommit<Impl>::commitInsts()
head_inst = rob->readHeadInst(commit_thread);
int tid = head_inst->threadNumber;
ThreadID tid = head_inst->threadNumber;
assert(tid == commit_thread);
@ -951,7 +954,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
{
assert(head_inst);
int tid = head_inst->threadNumber;
ThreadID tid = head_inst->threadNumber;
// If the instruction is not executed yet, then it will need extra
// handling. Signal backwards that it should be executed.
@ -1147,7 +1150,7 @@ DefaultCommit<Impl>::getInsts()
DynInstPtr inst;
inst = fromRename->insts[inst_num];
int tid = inst->threadNumber;
ThreadID tid = inst->threadNumber;
if (!inst->isSquashed() &&
commitStatus[tid] != ROBSquashing &&
@ -1220,11 +1223,11 @@ template <class Impl>
bool
DefaultCommit<Impl>::robDoneSquashing()
{
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (!rob->isDoneSquashing(tid))
return false;
@ -1237,40 +1240,40 @@ template <class Impl>
void
DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
{
unsigned thread = inst->threadNumber;
ThreadID tid = inst->threadNumber;
//
// Pick off the software prefetches
//
#ifdef TARGET_ALPHA
if (inst->isDataPrefetch()) {
statComSwp[thread]++;
statComSwp[tid]++;
} else {
statComInst[thread]++;
statComInst[tid]++;
}
#else
statComInst[thread]++;
statComInst[tid]++;
#endif
//
// Control Instructions
//
if (inst->isControl())
statComBranches[thread]++;
statComBranches[tid]++;
//
// Memory references
//
if (inst->isMemRef()) {
statComRefs[thread]++;
statComRefs[tid]++;
if (inst->isLoad()) {
statComLoads[thread]++;
statComLoads[tid]++;
}
}
if (inst->isMemBarrier()) {
statComMembars[thread]++;
statComMembars[tid]++;
}
}
@ -1280,7 +1283,7 @@ DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
// //
////////////////////////////////////////
template <class Impl>
int
ThreadID
DefaultCommit<Impl>::getCommittingThread()
{
if (numThreads > 1) {
@ -1299,31 +1302,31 @@ DefaultCommit<Impl>::getCommittingThread()
return oldestReady();
default:
return -1;
return InvalidThreadID;
}
} else {
assert(!activeThreads->empty());
int tid = activeThreads->front();
ThreadID tid = activeThreads->front();
if (commitStatus[tid] == Running ||
commitStatus[tid] == Idle ||
commitStatus[tid] == FetchTrapPending) {
return tid;
} else {
return -1;
return InvalidThreadID;
}
}
}
template<class Impl>
int
ThreadID
DefaultCommit<Impl>::roundRobin()
{
std::list<unsigned>::iterator pri_iter = priority_list.begin();
std::list<unsigned>::iterator end = priority_list.end();
list<ThreadID>::iterator pri_iter = priority_list.begin();
list<ThreadID>::iterator end = priority_list.end();
while (pri_iter != end) {
unsigned tid = *pri_iter;
ThreadID tid = *pri_iter;
if (commitStatus[tid] == Running ||
commitStatus[tid] == Idle ||
@ -1340,21 +1343,21 @@ DefaultCommit<Impl>::roundRobin()
pri_iter++;
}
return -1;
return InvalidThreadID;
}
template<class Impl>
int
ThreadID
DefaultCommit<Impl>::oldestReady()
{
unsigned oldest = 0;
bool first = true;
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (!rob->isEmpty(tid) &&
(commitStatus[tid] == Running ||
@ -1378,6 +1381,6 @@ DefaultCommit<Impl>::oldestReady()
if (!first) {
return oldest;
} else {
return -1;
return InvalidThreadID;
}
}

208
src/cpu/o3/cpu.cc
View file

@ -60,6 +60,7 @@
class BaseCPUParams;
using namespace TheISA;
using namespace std;
BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
: BaseCPU(params)
@ -184,7 +185,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
scoreboard(params->numThreads,
TheISA::NumIntRegs, params->numPhysIntRegs,
TheISA::NumFloatRegs, params->numPhysFloatRegs,
TheISA::NumMiscRegs * number_of_threads,
TheISA::NumMiscRegs * numThreads,
TheISA::ZeroReg),
timeBuffer(params->backComSize, params->forwardComSize),
@ -202,8 +203,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
physmem(system->physmem),
#endif // FULL_SYSTEM
drainCount(0),
deferRegistration(params->defer_registration),
numThreads(number_of_threads)
deferRegistration(params->defer_registration)
{
if (!deferRegistration) {
_status = Running;
@ -224,8 +224,8 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
#endif // USE_CHECKER
#if !FULL_SYSTEM
thread.resize(number_of_threads);
tids.resize(number_of_threads);
thread.resize(numThreads);
tids.resize(numThreads);
#endif
// The stages also need their CPU pointer setup. However this
@ -263,7 +263,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
rename.setCommitStage(&commit);
#if !FULL_SYSTEM
int active_threads = params->workload.size();
ThreadID active_threads = params->workload.size();
if (active_threads > Impl::MaxThreads) {
panic("Workload Size too large. Increase the 'MaxThreads'"
@ -271,7 +271,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
"edit your workload size.");
}
#else
int active_threads = 1;
ThreadID active_threads = 1;
#endif
//Make Sure That this a Valid Architeture
@ -285,7 +285,7 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
PhysRegIndex lreg_idx = 0;
PhysRegIndex freg_idx = params->numPhysIntRegs; //Index to 1 after int regs
for (int tid=0; tid < numThreads; tid++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
bool bindRegs = (tid <= active_threads - 1);
commitRenameMap[tid].init(TheISA::NumIntRegs,
@ -328,9 +328,8 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
commit.setRenameMap(commitRenameMap);
// Give renameMap & rename stage access to the freeList;
for (int i=0; i < numThreads; i++) {
renameMap[i].setFreeList(&freeList);
}
for (ThreadID tid = 0; tid < numThreads; tid++)
renameMap[tid].setFreeList(&freeList);
rename.setFreeList(&freeList);
// Setup the ROB for whichever stages need it.
@ -339,11 +338,11 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
lastRunningCycle = curTick;
lastActivatedCycle = -1;
#if 0
// Give renameMap & rename stage access to the freeList;
//for (int i=0; i < numThreads; i++) {
//globalSeqNum[i] = 1;
//}
for (ThreadID tid = 0; tid < numThreads; tid++)
globalSeqNum[tid] = 1;
#endif
contextSwitch = false;
DPRINTF(O3CPU, "Creating O3CPU object.\n");
@ -351,30 +350,30 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
// Setup any thread state.
this->thread.resize(this->numThreads);
for (int i = 0; i < this->numThreads; ++i) {
for (ThreadID tid = 0; tid < this->numThreads; ++tid) {
#if FULL_SYSTEM
// SMT is not supported in FS mode yet.
assert(this->numThreads == 1);
this->thread[i] = new Thread(this, 0);
this->thread[tid] = new Thread(this, 0);
#else
if (i < params->workload.size()) {
if (tid < params->workload.size()) {
DPRINTF(O3CPU, "Workload[%i] process is %#x",
i, this->thread[i]);
this->thread[i] = new typename FullO3CPU<Impl>::Thread(
tid, this->thread[tid]);
this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
(typename Impl::O3CPU *)(this),
i, params->workload[i], i);
tid, params->workload[tid], tid);
//usedTids[i] = true;
//threadMap[i] = i;
//usedTids[tid] = true;
//threadMap[tid] = tid;
} else {
//Allocate Empty thread so M5 can use later
//when scheduling threads to CPU
Process* dummy_proc = NULL;
this->thread[i] = new typename FullO3CPU<Impl>::Thread(
this->thread[tid] = new typename FullO3CPU<Impl>::Thread(
(typename Impl::O3CPU *)(this),
i, dummy_proc, i);
//usedTids[i] = false;
tid, dummy_proc, tid);
//usedTids[tid] = false;
}
#endif // !FULL_SYSTEM
@ -396,22 +395,21 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
o3_tc->cpu = (typename Impl::O3CPU *)(this);
assert(o3_tc->cpu);
o3_tc->thread = this->thread[i];
o3_tc->thread = this->thread[tid];
#if FULL_SYSTEM
// Setup quiesce event.
this->thread[i]->quiesceEvent = new EndQuiesceEvent(tc);
this->thread[tid]->quiesceEvent = new EndQuiesceEvent(tc);
#endif
// Give the thread the TC.
this->thread[i]->tc = tc;
this->thread[tid]->tc = tc;
// Add the TC to the CPU's list of TC's.
this->threadContexts.push_back(tc);
}
for (int i=0; i < this->numThreads; i++) {
this->thread[i]->setFuncExeInst(0);
}
for (ThreadID tid = 0; tid < this->numThreads; tid++)
this->thread[tid]->setFuncExeInst(0);
lockAddr = 0;
lockFlag = false;
@ -565,19 +563,19 @@ FullO3CPU<Impl>::init()
// Set inSyscall so that the CPU doesn't squash when initially
// setting up registers.
for (int i = 0; i < number_of_threads; ++i)
thread[i]->inSyscall = true;
for (ThreadID tid = 0; tid < numThreads; ++tid)
thread[tid]->inSyscall = true;
#if FULL_SYSTEM
for (int tid=0; tid < number_of_threads; tid++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
ThreadContext *src_tc = threadContexts[tid];
TheISA::initCPU(src_tc, src_tc->contextId());
}
#endif
// Clear inSyscall.
for (int i = 0; i < number_of_threads; ++i)
thread[i]->inSyscall = false;
for (int tid = 0; tid < numThreads; ++tid)
thread[tid]->inSyscall = false;
// Initialize stages.
fetch.initStage();
@ -590,9 +588,9 @@ FullO3CPU<Impl>::init()
template <class Impl>
void
FullO3CPU<Impl>::activateThread(unsigned tid)
FullO3CPU<Impl>::activateThread(ThreadID tid)
{
std::list<unsigned>::iterator isActive =
list<ThreadID>::iterator isActive =
std::find(activeThreads.begin(), activeThreads.end(), tid);
DPRINTF(O3CPU, "[tid:%i]: Calling activate thread.\n", tid);
@ -607,10 +605,10 @@ FullO3CPU<Impl>::activateThread(unsigned tid)
template <class Impl>
void
FullO3CPU<Impl>::deactivateThread(unsigned tid)
FullO3CPU<Impl>::deactivateThread(ThreadID tid)
{
//Remove From Active List, if Active
std::list<unsigned>::iterator thread_it =
list<ThreadID>::iterator thread_it =
std::find(activeThreads.begin(), activeThreads.end(), tid);
DPRINTF(O3CPU, "[tid:%i]: Calling deactivate thread.\n", tid);
@ -622,9 +620,22 @@ FullO3CPU<Impl>::deactivateThread(unsigned tid)
}
}
template <class Impl>
Counter
FullO3CPU<Impl>::totalInstructions() const
{
Counter total(0);
ThreadID size = thread.size();
for (ThreadID i = 0; i < size; i++)
total += thread[i]->numInst;
return total;
}
template <class Impl>
void
FullO3CPU<Impl>::activateContext(int tid, int delay)
FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
{
// Needs to set each stage to running as well.
if (delay){
@ -651,7 +662,7 @@ FullO3CPU<Impl>::activateContext(int tid, int delay)
template <class Impl>
bool
FullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay)
FullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay)
{
// Schedule removal of thread data from CPU
if (delay){
@ -669,7 +680,7 @@ FullO3CPU<Impl>::deallocateContext(int tid, bool remove, int delay)
template <class Impl>
void
FullO3CPU<Impl>::suspendContext(int tid)
FullO3CPU<Impl>::suspendContext(ThreadID tid)
{
DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
bool deallocated = deallocateContext(tid, false, 1);
@ -682,7 +693,7 @@ FullO3CPU<Impl>::suspendContext(int tid)
template <class Impl>
void
FullO3CPU<Impl>::haltContext(int tid)
FullO3CPU<Impl>::haltContext(ThreadID tid)
{
//For now, this is the same as deallocate
DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
@ -691,7 +702,7 @@ FullO3CPU<Impl>::haltContext(int tid)
template <class Impl>
void
FullO3CPU<Impl>::insertThread(unsigned tid)
FullO3CPU<Impl>::insertThread(ThreadID tid)
{
DPRINTF(O3CPU,"[tid:%i] Initializing thread into CPU");
// Will change now that the PC and thread state is internal to the CPU
@ -737,7 +748,7 @@ FullO3CPU<Impl>::insertThread(unsigned tid)
template <class Impl>
void
FullO3CPU<Impl>::removeThread(unsigned tid)
FullO3CPU<Impl>::removeThread(ThreadID tid)
{
DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
@ -796,7 +807,7 @@ FullO3CPU<Impl>::removeThread(unsigned tid)
template <class Impl>
void
FullO3CPU<Impl>::activateWhenReady(int tid)
FullO3CPU<Impl>::activateWhenReady(ThreadID tid)
{
DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming"
"(e.g. PhysRegs/ROB/IQ/LSQ) \n",
@ -855,7 +866,7 @@ FullO3CPU<Impl>::activateWhenReady(int tid)
#if FULL_SYSTEM
template <class Impl>
Fault
FullO3CPU<Impl>::hwrei(unsigned tid)
FullO3CPU<Impl>::hwrei(ThreadID tid)
{
#if THE_ISA == ALPHA_ISA
// Need to clear the lock flag upon returning from an interrupt.
@ -870,7 +881,7 @@ FullO3CPU<Impl>::hwrei(unsigned tid)
template <class Impl>
bool
FullO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid)
FullO3CPU<Impl>::simPalCheck(int palFunc, ThreadID tid)
{
#if THE_ISA == ALPHA_ISA
if (this->thread[tid]->kernelStats)
@ -925,14 +936,15 @@ FullO3CPU<Impl>::updateMemPorts()
{
// Update all ThreadContext's memory ports (Functional/Virtual
// Ports)
for (int i = 0; i < thread.size(); ++i)
ThreadID size = thread.size();
for (ThreadID i = 0; i < size; ++i)
thread[i]->connectMemPorts(thread[i]->getTC());
}
#endif
template <class Impl>
void
FullO3CPU<Impl>::trap(Fault fault, unsigned tid)
FullO3CPU<Impl>::trap(Fault fault, ThreadID tid)
{
// Pass the thread's TC into the invoke method.
fault->invoke(this->threadContexts[tid]);
@ -942,7 +954,7 @@ FullO3CPU<Impl>::trap(Fault fault, unsigned tid)
template <class Impl>
void
FullO3CPU<Impl>::syscall(int64_t callnum, int tid)
FullO3CPU<Impl>::syscall(int64_t callnum, ThreadID tid)
{
DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
@ -977,7 +989,8 @@ FullO3CPU<Impl>::serialize(std::ostream &os)
// get instantiated multiple times (causes a panic in statistics).
static SimpleThread temp;
for (int i = 0; i < thread.size(); i++) {
ThreadID size = thread.size();
for (ThreadID i = 0; i < size; i++) {
nameOut(os, csprintf("%s.xc.%i", name(), i));
temp.copyTC(thread[i]->getTC());
temp.serialize(os);
@ -998,7 +1011,8 @@ FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
// get instantiated multiple times (causes a panic in statistics).
static SimpleThread temp;
for (int i = 0; i < thread.size(); i++) {
ThreadID size = thread.size();
for (ThreadID i = 0; i < size; i++) {
temp.copyTC(thread[i]->getTC());
temp.unserialize(cp, csprintf("%s.xc.%i", section, i));
thread[i]->getTC()->copyArchRegs(temp.getTC());
@ -1134,9 +1148,9 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
// @todo: Figure out how to properly select the tid to put onto
// the active threads list.
int tid = 0;
ThreadID tid = 0;
std::list<unsigned>::iterator isActive =
list<ThreadID>::iterator isActive =
std::find(activeThreads.begin(), activeThreads.end(), tid);
if (isActive == activeThreads.end()) {
@ -1150,7 +1164,8 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
// Set all statuses to active, schedule the CPU's tick event.
// @todo: Fix up statuses so this is handled properly
for (int i = 0; i < threadContexts.size(); ++i) {
ThreadID size = threadContexts.size();
for (ThreadID i = 0; i < size; ++i) {
ThreadContext *tc = threadContexts[i];
if (tc->status() == ThreadContext::Active && _status != Running) {
_status = Running;
@ -1163,14 +1178,14 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
template <class Impl>
TheISA::MiscReg
FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, unsigned tid)
FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
{
return this->regFile.readMiscRegNoEffect(misc_reg, tid);
}
template <class Impl>
TheISA::MiscReg
FullO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
{
return this->regFile.readMiscReg(misc_reg, tid);
}
@ -1178,7 +1193,7 @@ FullO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
template <class Impl>
void
FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
const TheISA::MiscReg &val, unsigned tid)
const TheISA::MiscReg &val, ThreadID tid)
{
this->regFile.setMiscRegNoEffect(misc_reg, val, tid);
}
@ -1186,7 +1201,7 @@ FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
template <class Impl>
void
FullO3CPU<Impl>::setMiscReg(int misc_reg,
const TheISA::MiscReg &val, unsigned tid)
const TheISA::MiscReg &val, ThreadID tid)
{
this->regFile.setMiscReg(misc_reg, val, tid);
}
@ -1263,7 +1278,7 @@ FullO3CPU<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
template <class Impl>
uint64_t
FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid)
FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid)
{
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
@ -1272,7 +1287,7 @@ FullO3CPU<Impl>::readArchIntReg(int reg_idx, unsigned tid)
template <class Impl>
float
FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid)
FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, ThreadID tid)
{
int idx = reg_idx + TheISA::NumIntRegs;
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
@ -1282,7 +1297,7 @@ FullO3CPU<Impl>::readArchFloatRegSingle(int reg_idx, unsigned tid)
template <class Impl>
double
FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid)
FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, ThreadID tid)
{
int idx = reg_idx + TheISA::NumIntRegs;
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
@ -1292,7 +1307,7 @@ FullO3CPU<Impl>::readArchFloatRegDouble(int reg_idx, unsigned tid)
template <class Impl>
uint64_t
FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid)
FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
{
int idx = reg_idx + TheISA::NumIntRegs;
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
@ -1302,7 +1317,7 @@ FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, unsigned tid)
template <class Impl>
void
FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid)
FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid)
{
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
@ -1311,7 +1326,7 @@ FullO3CPU<Impl>::setArchIntReg(int reg_idx, uint64_t val, unsigned tid)
template <class Impl>
void
FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, ThreadID tid)
{
int idx = reg_idx + TheISA::NumIntRegs;
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
@ -1321,7 +1336,7 @@ FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
template <class Impl>
void
FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, ThreadID tid)
{
int idx = reg_idx + TheISA::NumIntRegs;
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
@ -1331,7 +1346,7 @@ FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
template <class Impl>
void
FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
{
int idx = reg_idx + TheISA::NumIntRegs;
PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
@ -1341,77 +1356,77 @@ FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
template <class Impl>
uint64_t
FullO3CPU<Impl>::readPC(unsigned tid)
FullO3CPU<Impl>::readPC(ThreadID tid)
{
return commit.readPC(tid);
}
template <class Impl>
void
FullO3CPU<Impl>::setPC(Addr new_PC,unsigned tid)
FullO3CPU<Impl>::setPC(Addr new_PC, ThreadID tid)
{
commit.setPC(new_PC, tid);
}
template <class Impl>
uint64_t
FullO3CPU<Impl>::readMicroPC(unsigned tid)
FullO3CPU<Impl>::readMicroPC(ThreadID tid)
{
return commit.readMicroPC(tid);
}
template <class Impl>
void
FullO3CPU<Impl>::setMicroPC(Addr new_PC,unsigned tid)
FullO3CPU<Impl>::setMicroPC(Addr new_PC, ThreadID tid)
{
commit.setMicroPC(new_PC, tid);
}
template <class Impl>
uint64_t
FullO3CPU<Impl>::readNextPC(unsigned tid)
FullO3CPU<Impl>::readNextPC(ThreadID tid)
{
return commit.readNextPC(tid);
}
template <class Impl>
void
FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
FullO3CPU<Impl>::setNextPC(uint64_t val, ThreadID tid)
{
commit.setNextPC(val, tid);
}
template <class Impl>
uint64_t
FullO3CPU<Impl>::readNextNPC(unsigned tid)
FullO3CPU<Impl>::readNextNPC(ThreadID tid)
{
return commit.readNextNPC(tid);
}
template <class Impl>
void
FullO3CPU<Impl>::setNextNPC(uint64_t val,unsigned tid)
FullO3CPU<Impl>::setNextNPC(uint64_t val, ThreadID tid)
{
commit.setNextNPC(val, tid);
}
template <class Impl>
uint64_t
FullO3CPU<Impl>::readNextMicroPC(unsigned tid)
FullO3CPU<Impl>::readNextMicroPC(ThreadID tid)
{
return commit.readNextMicroPC(tid);
}
template <class Impl>
void
FullO3CPU<Impl>::setNextMicroPC(Addr new_PC,unsigned tid)
FullO3CPU<Impl>::setNextMicroPC(Addr new_PC, ThreadID tid)
{
commit.setNextMicroPC(new_PC, tid);
}
template <class Impl>
void
FullO3CPU<Impl>::squashFromTC(unsigned tid)
FullO3CPU<Impl>::squashFromTC(ThreadID tid)
{
this->thread[tid]->inSyscall = true;
this->commit.generateTCEvent(tid);
@ -1428,7 +1443,7 @@ FullO3CPU<Impl>::addInst(DynInstPtr &inst)
template <class Impl>
void
FullO3CPU<Impl>::instDone(unsigned tid)
FullO3CPU<Impl>::instDone(ThreadID tid)
{
// Keep an instruction count.
thread[tid]->numInst++;
@ -1465,7 +1480,7 @@ FullO3CPU<Impl>::removeFrontInst(DynInstPtr &inst)
template <class Impl>
void
FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
FullO3CPU<Impl>::removeInstsNotInROB(ThreadID tid)
{
DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction"
" list.\n", tid);
@ -1510,8 +1525,7 @@ FullO3CPU<Impl>::removeInstsNotInROB(unsigned tid)
template <class Impl>
void
FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num,
unsigned tid)
FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
{
assert(!instList.empty());
@ -1540,7 +1554,7 @@ FullO3CPU<Impl>::removeInstsUntil(const InstSeqNum &seq_num,
template <class Impl>
inline void
FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, const unsigned &tid)
FullO3CPU<Impl>::squashInstIt(const ListIt &instIt, ThreadID tid)
{
if ((*instIt)->threadNumber == tid) {
DPRINTF(O3CPU, "Squashing instruction, "
@ -1646,17 +1660,17 @@ FullO3CPU<Impl>::wakeup()
#endif
template <class Impl>
int
ThreadID
FullO3CPU<Impl>::getFreeTid()
{
for (int i=0; i < numThreads; i++) {
if (!tids[i]) {
tids[i] = true;
return i;
for (ThreadID tid = 0; tid < numThreads; tid++) {
if (!tids[tid]) {
tids[tid] = true;
return tid;
}
}
return -1;
return InvalidThreadID;
}
template <class Impl>
@ -1667,7 +1681,8 @@ FullO3CPU<Impl>::doContextSwitch()
//ADD CODE TO DEACTIVE THREAD HERE (???)
for (int tid=0; tid < cpuWaitList.size(); tid++) {
ThreadID size = cpuWaitList.size();
for (ThreadID tid = 0; tid < size; tid++) {
activateWhenReady(tid);
}
@ -1680,12 +1695,11 @@ template <class Impl>
void
FullO3CPU<Impl>::updateThreadPriority()
{
if (activeThreads.size() > 1)
{
if (activeThreads.size() > 1) {
//DEFAULT TO ROUND ROBIN SCHEME
//e.g. Move highest priority to end of thread list
std::list<unsigned>::iterator list_begin = activeThreads.begin();
std::list<unsigned>::iterator list_end = activeThreads.end();
list<ThreadID>::iterator list_begin = activeThreads.begin();
list<ThreadID>::iterator list_end = activeThreads.end();
unsigned high_thread = *list_begin;

129
src/cpu/o3/cpu.hh
View file

@ -155,7 +155,7 @@ class FullO3CPU : public BaseO3CPU
{
private:
/** Number of Thread to Activate */
int tid;
ThreadID tid;
/** Pointer to the CPU. */
FullO3CPU<Impl> *cpu;
@ -175,7 +175,8 @@ class FullO3CPU : public BaseO3CPU
};
/** Schedule thread to activate , regardless of its current state. */
void scheduleActivateThreadEvent(int tid, int delay)
void
scheduleActivateThreadEvent(ThreadID tid, int delay)
{
// Schedule thread to activate, regardless of its current state.
if (activateThreadEvent[tid].squashed())
@ -187,7 +188,8 @@ class FullO3CPU : public BaseO3CPU
}
/** Unschedule actiavte thread event, regardless of its current state. */
void unscheduleActivateThreadEvent(int tid)
void
unscheduleActivateThreadEvent(ThreadID tid)
{
if (activateThreadEvent[tid].scheduled())
activateThreadEvent[tid].squash();
@ -200,7 +202,7 @@ class FullO3CPU : public BaseO3CPU
{
private:
/** Number of Thread to deactivate */
int tid;
ThreadID tid;
/** Should the thread be removed from the CPU? */
bool remove;
@ -226,7 +228,8 @@ class FullO3CPU : public BaseO3CPU
};
/** Schedule cpu to deallocate thread context.*/
void scheduleDeallocateContextEvent(int tid, bool remove, int delay)
void
scheduleDeallocateContextEvent(ThreadID tid, bool remove, int delay)
{
// Schedule thread to activate, regardless of its current state.
if (deallocateContextEvent[tid].squashed())
@ -238,7 +241,8 @@ class FullO3CPU : public BaseO3CPU
}
/** Unschedule thread deallocation in CPU */
void unscheduleDeallocateContextEvent(int tid)
void
unscheduleDeallocateContextEvent(ThreadID tid)
{
if (deallocateContextEvent[tid].scheduled())
deallocateContextEvent[tid].squash();
@ -288,46 +292,38 @@ class FullO3CPU : public BaseO3CPU
{ return activeThreads.size(); }
/** Add Thread to Active Threads List */
void activateThread(unsigned tid);
void activateThread(ThreadID tid);
/** Remove Thread from Active Threads List */
void deactivateThread(unsigned tid);
void deactivateThread(ThreadID tid);
/** Setup CPU to insert a thread's context */
void insertThread(unsigned tid);
void insertThread(ThreadID tid);
/** Remove all of a thread's context from CPU */
void removeThread(unsigned tid);
void removeThread(ThreadID tid);
/** Count the Total Instructions Committed in the CPU. */
virtual Counter totalInstructions() const
{
Counter total(0);
for (int i=0; i < thread.size(); i++)
total += thread[i]->numInst;
return total;
}
virtual Counter totalInstructions() const;
/** Add Thread to Active Threads List. */
void activateContext(int tid, int delay);
void activateContext(ThreadID tid, int delay);
/** Remove Thread from Active Threads List */
void suspendContext(int tid);
void suspendContext(ThreadID tid);
/** Remove Thread from Active Threads List &&
* Possibly Remove Thread Context from CPU.
*/
bool deallocateContext(int tid, bool remove, int delay = 1);
bool deallocateContext(ThreadID tid, bool remove, int delay = 1);
/** Remove Thread from Active Threads List &&
* Remove Thread Context from CPU.
*/
void haltContext(int tid);
void haltContext(ThreadID tid);
/** Activate a Thread When CPU Resources are Available. */
void activateWhenReady(int tid);
void activateWhenReady(ThreadID tid);
/** Add or Remove a Thread Context in the CPU. */
void doContextSwitch();
@ -346,7 +342,7 @@ class FullO3CPU : public BaseO3CPU
/** Executes a syscall.
* @todo: Determine if this needs to be virtual.
*/
void syscall(int64_t callnum, int tid);
void syscall(int64_t callnum, ThreadID tid);
#endif
/** Starts draining the CPU's pipeline of all instructions in
@ -370,13 +366,13 @@ class FullO3CPU : public BaseO3CPU
{ return globalSeqNum++; }
/** Traps to handle given fault. */
void trap(Fault fault, unsigned tid);
void trap(Fault fault, ThreadID tid);
#if FULL_SYSTEM
/** HW return from error interrupt. */
Fault hwrei(unsigned tid);
Fault hwrei(ThreadID tid);
bool simPalCheck(int palFunc, unsigned tid);
bool simPalCheck(int palFunc, ThreadID tid);
/** Returns the Fault for any valid interrupt. */
Fault getInterrupts();
@ -398,19 +394,19 @@ class FullO3CPU : public BaseO3CPU
bool validDataAddr(Addr addr) { return true; }
/** Get instruction asid. */
int getInstAsid(unsigned tid)
int getInstAsid(ThreadID tid)
{ return regFile.miscRegs[tid].getInstAsid(); }
/** Get data asid. */
int getDataAsid(unsigned tid)
int getDataAsid(ThreadID tid)
{ return regFile.miscRegs[tid].getDataAsid(); }
#else
/** Get instruction asid. */
int getInstAsid(unsigned tid)
int getInstAsid(ThreadID tid)
{ return thread[tid]->getInstAsid(); }
/** Get data asid. */
int getDataAsid(unsigned tid)
int getDataAsid(ThreadID tid)
{ return thread[tid]->getDataAsid(); }
#endif
@ -418,21 +414,22 @@ class FullO3CPU : public BaseO3CPU
/** Register accessors. Index refers to the physical register index. */
/** Reads a miscellaneous register. */
TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
/** Reads a misc. register, including any side effects the read
* might have as defined by the architecture.
*/
TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
TheISA::MiscReg readMiscReg(int misc_reg, ThreadID tid);
/** Sets a miscellaneous register. */
void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val,
ThreadID tid);
/** Sets a misc. register, including any side effects the write
* might have as defined by the architecture.
*/
void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
unsigned tid);
ThreadID tid);
uint64_t readIntReg(int reg_idx);
@ -454,62 +451,62 @@ class FullO3CPU : public BaseO3CPU
void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width);
uint64_t readArchIntReg(int reg_idx, unsigned tid);
uint64_t readArchIntReg(int reg_idx, ThreadID tid);
float readArchFloatRegSingle(int reg_idx, unsigned tid);
float readArchFloatRegSingle(int reg_idx, ThreadID tid);
double readArchFloatRegDouble(int reg_idx, unsigned tid);
double readArchFloatRegDouble(int reg_idx, ThreadID tid);
uint64_t readArchFloatRegInt(int reg_idx, unsigned tid);
uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
/** Architectural register accessors. Looks up in the commit
* rename table to obtain the true physical index of the
* architected register first, then accesses that physical
* register.
*/
void setArchIntReg(int reg_idx, uint64_t val, unsigned tid);
void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
void setArchFloatRegSingle(int reg_idx, float val, unsigned tid);
void setArchFloatRegSingle(int reg_idx, float val, ThreadID tid);
void setArchFloatRegDouble(int reg_idx, double val, unsigned tid);
void setArchFloatRegDouble(int reg_idx, double val, ThreadID tid);
void setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid);
void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
/** Reads the commit PC of a specific thread. */
Addr readPC(unsigned tid);
Addr readPC(ThreadID tid);
/** Sets the commit PC of a specific thread. */
void setPC(Addr new_PC, unsigned tid);
void setPC(Addr new_PC, ThreadID tid);
/** Reads the commit micro PC of a specific thread. */
Addr readMicroPC(unsigned tid);
Addr readMicroPC(ThreadID tid);
/** Sets the commmit micro PC of a specific thread. */
void setMicroPC(Addr new_microPC, unsigned tid);
void setMicroPC(Addr new_microPC, ThreadID tid);
/** Reads the next PC of a specific thread. */
Addr readNextPC(unsigned tid);
Addr readNextPC(ThreadID tid);
/** Sets the next PC of a specific thread. */
void setNextPC(Addr val, unsigned tid);
void setNextPC(Addr val, ThreadID tid);
/** Reads the next NPC of a specific thread. */
Addr readNextNPC(unsigned tid);
Addr readNextNPC(ThreadID tid);
/** Sets the next NPC of a specific thread. */
void setNextNPC(Addr val, unsigned tid);
void setNextNPC(Addr val, ThreadID tid);
/** Reads the commit next micro PC of a specific thread. */
Addr readNextMicroPC(unsigned tid);
Addr readNextMicroPC(ThreadID tid);
/** Sets the commit next micro PC of a specific thread. */
void setNextMicroPC(Addr val, unsigned tid);
void setNextMicroPC(Addr val, ThreadID tid);
/** Initiates a squash of all in-flight instructions for a given
* thread. The source of the squash is an external update of
* state through the TC.
*/
void squashFromTC(unsigned tid);
void squashFromTC(ThreadID tid);
/** Function to add instruction onto the head of the list of the
* instructions. Used when new instructions are fetched.
@ -517,7 +514,7 @@ class FullO3CPU : public BaseO3CPU
ListIt addInst(DynInstPtr &inst);
/** Function to tell the CPU that an instruction has completed. */
void instDone(unsigned tid);
void instDone(ThreadID tid);
/** Add Instructions to the CPU Remove List*/
void addToRemoveList(DynInstPtr &inst);
@ -529,13 +526,13 @@ class FullO3CPU : public BaseO3CPU
/** Remove all instructions that are not currently in the ROB.
* There's also an option to not squash delay slot instructions.*/
void removeInstsNotInROB(unsigned tid);
void removeInstsNotInROB(ThreadID tid);
/** Remove all instructions younger than the given sequence number. */
void removeInstsUntil(const InstSeqNum &seq_num,unsigned tid);
void removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid);
/** Removes the instruction pointed to by the iterator. */
inline void squashInstIt(const ListIt &instIt, const unsigned &tid);
inline void squashInstIt(const ListIt &instIt, ThreadID tid);
/** Cleans up all instructions on the remove list. */
void cleanUpRemovedInsts();
@ -601,7 +598,7 @@ class FullO3CPU : public BaseO3CPU
typename CPUPolicy::ROB rob;
/** Active Threads List */
std::list<unsigned> activeThreads;
std::list<ThreadID> activeThreads;
/** Integer Register Scoreboard */
Scoreboard scoreboard;
@ -674,11 +671,12 @@ class FullO3CPU : public BaseO3CPU
#endif
/** Gets a free thread id. Use if thread ids change across system. */
int getFreeTid();
ThreadID getFreeTid();
public:
/** Returns a pointer to a thread context. */
ThreadContext *tcBase(unsigned tid)
ThreadContext *
tcBase(ThreadID tid)
{
return thread[tid]->getTC();
}
@ -726,14 +724,11 @@ class FullO3CPU : public BaseO3CPU
/** The cycle that the CPU was last activated by a new thread*/
Tick lastActivatedCycle;
/** Number of Threads CPU can process */
unsigned numThreads;
/** Mapping for system thread id to cpu id */
std::map<unsigned,unsigned> threadMap;
std::map<ThreadID, unsigned> threadMap;
/** Available thread ids in the cpu*/
std::vector<unsigned> tids;
std::vector<ThreadID> tids;
/** CPU read function, forwards read to LSQ. */
template <class T>

4
src/cpu/o3/cpu_builder.cc
View file

@ -49,11 +49,11 @@ DerivO3CPUParams::create()
{
#if FULL_SYSTEM
// Full-system only supports a single thread for the moment.
int actual_num_threads = 1;
ThreadID actual_num_threads = 1;
#else
// In non-full-system mode, we infer the number of threads from
// the workload if it's not explicitly specified.
int actual_num_threads =
ThreadID actual_num_threads =
(numThreads >= workload.size()) ? numThreads : workload.size();
if (workload.size() == 0) {

26
src/cpu/o3/decode.hh
View file

@ -105,7 +105,7 @@ class DefaultDecode
void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
/** Sets pointer to list of active threads. */
void setActiveThreads(std::list<unsigned> *at_ptr);
void setActiveThreads(std::list<ThreadID> *at_ptr);
/** Drains the decode stage. */
bool drain();
@ -129,20 +129,20 @@ class DefaultDecode
* change (ie switching from from blocking to unblocking).
* @param tid Thread id to decode instructions from.
*/
void decode(bool &status_change, unsigned tid);
void decode(bool &status_change, ThreadID tid);
/** Processes instructions from fetch and passes them on to rename.
* Decoding of instructions actually happens when they are created in
* fetch, so this function mostly checks if PC-relative branches are
* correct.
*/
void decodeInsts(unsigned tid);
void decodeInsts(ThreadID tid);
private:
/** Inserts a thread's instructions into the skid buffer, to be decoded
* once decode unblocks.
*/
void skidInsert(unsigned tid);
void skidInsert(ThreadID tid);
/** Returns if all of the skid buffers are empty. */
bool skidsEmpty();
@ -156,13 +156,13 @@ class DefaultDecode
void sortInsts();
/** Reads all stall signals from the backwards communication timebuffer. */
void readStallSignals(unsigned tid);
void readStallSignals(ThreadID tid);
/** Checks all input signals and updates decode's status appropriately. */
bool checkSignalsAndUpdate(unsigned tid);
bool checkSignalsAndUpdate(ThreadID tid);
/** Checks all stall signals, and returns if any are true. */
bool checkStall(unsigned tid) const;
bool checkStall(ThreadID tid) const;
/** Returns if there any instructions from fetch on this cycle. */
inline bool fetchInstsValid();
@ -171,24 +171,24 @@ class DefaultDecode
* become blocked.
* @return Returns true if there is a status change.
*/
bool block(unsigned tid);
bool block(ThreadID tid);
/** Switches decode to unblocking if the skid buffer is empty, and
* signals back that decode has unblocked.
* @return Returns true if there is a status change.
*/
bool unblock(unsigned tid);
bool unblock(ThreadID tid);
/** Squashes if there is a PC-relative branch that was predicted
* incorrectly. Sends squash information back to fetch.
*/
void squash(DynInstPtr &inst, unsigned tid);
void squash(DynInstPtr &inst, ThreadID tid);
public:
/** Squashes due to commit signalling a squash. Changes status to
* squashing and clears block/unblock signals as needed.
*/
unsigned squash(unsigned tid);
unsigned squash(ThreadID tid);
private:
// Interfaces to objects outside of decode.
@ -263,10 +263,10 @@ class DefaultDecode
unsigned toRenameIndex;
/** number of Active Threads*/
unsigned numThreads;
ThreadID numThreads;
/** List of active thread ids */
std::list<unsigned> *activeThreads;
std::list<ThreadID> *activeThreads;
/** Number of branches in flight. */
unsigned branchCount[Impl::MaxThreads];

77
src/cpu/o3/decode_impl.hh
View file

@ -29,9 +29,10 @@
*/
#include "cpu/o3/decode.hh"
#include "params/DerivO3CPU.hh"
using namespace std;
template<class Impl>
DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
: cpu(_cpu),
@ -45,12 +46,12 @@ DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
_status = Inactive;
// Setup status, make sure stall signals are clear.
for (int i = 0; i < numThreads; ++i) {
decodeStatus[i] = Idle;
for (ThreadID tid = 0; tid < numThreads; ++tid) {
decodeStatus[tid] = Idle;
stalls[i].rename = false;
stalls[i].iew = false;
stalls[i].commit = false;
stalls[tid].rename = false;
stalls[tid].iew = false;
stalls[tid].commit = false;
}
// @todo: Make into a parameter
@ -148,7 +149,7 @@ DefaultDecode<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
template<class Impl>
void
DefaultDecode<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
DefaultDecode<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
{
activeThreads = at_ptr;
}
@ -169,24 +170,24 @@ DefaultDecode<Impl>::takeOverFrom()
_status = Inactive;
// Be sure to reset state and clear out any old instructions.
for (int i = 0; i < numThreads; ++i) {
decodeStatus[i] = Idle;
for (ThreadID tid = 0; tid < numThreads; ++tid) {
decodeStatus[tid] = Idle;
stalls[i].rename = false;
stalls[i].iew = false;
stalls[i].commit = false;
while (!insts[i].empty())
insts[i].pop();
while (!skidBuffer[i].empty())
skidBuffer[i].pop();
branchCount[i] = 0;
stalls[tid].rename = false;
stalls[tid].iew = false;
stalls[tid].commit = false;
while (!insts[tid].empty())
insts[tid].pop();
while (!skidBuffer[tid].empty())
skidBuffer[tid].pop();
branchCount[tid] = 0;
}
wroteToTimeBuffer = false;
}
template<class Impl>
bool
DefaultDecode<Impl>::checkStall(unsigned tid) const
DefaultDecode<Impl>::checkStall(ThreadID tid) const
{
bool ret_val = false;
@ -213,7 +214,7 @@ DefaultDecode<Impl>::fetchInstsValid()
template<class Impl>
bool
DefaultDecode<Impl>::block(unsigned tid)
DefaultDecode<Impl>::block(ThreadID tid)
{
DPRINTF(Decode, "[tid:%u]: Blocking.\n", tid);
@ -241,7 +242,7 @@ DefaultDecode<Impl>::block(unsigned tid)
template<class Impl>
bool
DefaultDecode<Impl>::unblock(unsigned tid)
DefaultDecode<Impl>::unblock(ThreadID tid)
{
// Decode is done unblocking only if the skid buffer is empty.
if (skidBuffer[tid].empty()) {
@ -260,7 +261,7 @@ DefaultDecode<Impl>::unblock(unsigned tid)
template<class Impl>
void
DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid)
DefaultDecode<Impl>::squash(DynInstPtr &inst, ThreadID tid)
{
DPRINTF(Decode, "[tid:%i]: [sn:%i] Squashing due to incorrect branch prediction "
"detected at decode.\n", tid, inst->seqNum);
@ -320,7 +321,7 @@ DefaultDecode<Impl>::squash(DynInstPtr &inst, unsigned tid)
template<class Impl>
unsigned
DefaultDecode<Impl>::squash(unsigned tid)
DefaultDecode<Impl>::squash(ThreadID tid)
{
DPRINTF(Decode, "[tid:%i]: Squashing.\n",tid);
@ -369,7 +370,7 @@ DefaultDecode<Impl>::squash(unsigned tid)
template<class Impl>
void
DefaultDecode<Impl>::skidInsert(unsigned tid)
DefaultDecode<Impl>::skidInsert(ThreadID tid)
{
DynInstPtr inst = NULL;
@ -395,11 +396,11 @@ template<class Impl>
bool
DefaultDecode<Impl>::skidsEmpty()
{
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (!skidBuffer[tid].empty())
return false;
}
@ -413,11 +414,11 @@ DefaultDecode<Impl>::updateStatus()
{
bool any_unblocking = false;
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (decodeStatus[tid] == Unblocking) {
any_unblocking = true;
@ -452,8 +453,8 @@ DefaultDecode<Impl>::sortInsts()
{
int insts_from_fetch = fromFetch->size;
#ifdef DEBUG
for (int i=0; i < numThreads; i++)
assert(insts[i].empty());
for (ThreadID tid = 0; tid < numThreads; tid++)
assert(insts[tid].empty());
#endif
for (int i = 0; i < insts_from_fetch; ++i) {
insts[fromFetch->insts[i]->threadNumber].push(fromFetch->insts[i]);
@ -462,7 +463,7 @@ DefaultDecode<Impl>::sortInsts()
template<class Impl>
void
DefaultDecode<Impl>::readStallSignals(unsigned tid)
DefaultDecode<Impl>::readStallSignals(ThreadID tid)
{
if (fromRename->renameBlock[tid]) {
stalls[tid].rename = true;
@ -494,7 +495,7 @@ DefaultDecode<Impl>::readStallSignals(unsigned tid)
template <class Impl>
bool
DefaultDecode<Impl>::checkSignalsAndUpdate(unsigned tid)
DefaultDecode<Impl>::checkSignalsAndUpdate(ThreadID tid)
{
// Check if there's a squash signal, squash if there is.
// Check stall signals, block if necessary.
@ -569,14 +570,14 @@ DefaultDecode<Impl>::tick()
toRenameIndex = 0;
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
sortInsts();
//Check stall and squash signals.
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
DPRINTF(Decode,"Processing [tid:%i]\n",tid);
status_change = checkSignalsAndUpdate(tid) || status_change;
@ -597,7 +598,7 @@ DefaultDecode<Impl>::tick()
template<class Impl>
void
DefaultDecode<Impl>::decode(bool &status_change, unsigned tid)
DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid)
{
// If status is Running or idle,
// call decodeInsts()
@ -642,7 +643,7 @@ DefaultDecode<Impl>::decode(bool &status_change, unsigned tid)
template <class Impl>
void
DefaultDecode<Impl>::decodeInsts(unsigned tid)
DefaultDecode<Impl>::decodeInsts(ThreadID tid)
{
// Instructions can come either from the skid buffer or the list of
// instructions coming from fetch, depending on decode's status.

39
src/cpu/o3/fetch.hh
View file

@ -157,7 +157,7 @@ class DefaultFetch
FetchPriority fetchPolicy;
/** List that has the threads organized by priority. */
std::list<unsigned> priorityList;
std::list<ThreadID> priorityList;
public:
/** DefaultFetch constructor. */
@ -176,7 +176,7 @@ class DefaultFetch
void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
/** Sets pointer to list of active threads. */
void setActiveThreads(std::list<unsigned> *at_ptr);
void setActiveThreads(std::list<ThreadID> *at_ptr);
/** Sets pointer to time buffer used to communicate to the next stage. */
void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
@ -240,21 +240,21 @@ class DefaultFetch
* @param tid Thread id.
* @return Any fault that occured.
*/
bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, ThreadID tid);
/** Squashes a specific thread and resets the PC. */
inline void doSquash(const Addr &new_PC, const Addr &new_NPC,
const Addr &new_MicroPC, unsigned tid);
const Addr &new_MicroPC, ThreadID tid);
/** Squashes a specific thread and resets the PC. Also tells the CPU to
* remove any instructions between fetch and decode that should be sqaushed.
*/
void squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
const Addr &new_MicroPC,
const InstSeqNum &seq_num, unsigned tid);
const InstSeqNum &seq_num, ThreadID tid);
/** Checks if a thread is stalled. */
bool checkStall(unsigned tid) const;
bool checkStall(ThreadID tid) const;
/** Updates overall fetch stage status; to be called at the end of each
* cycle. */
@ -267,7 +267,7 @@ class DefaultFetch
*/
void squash(const Addr &new_PC, const Addr &new_NPC,
const Addr &new_MicroPC,
const InstSeqNum &seq_num, unsigned tid);
const InstSeqNum &seq_num, ThreadID tid);
/** Ticks the fetch stage, processing all inputs signals and fetching
* as many instructions as possible.
@ -277,7 +277,7 @@ class DefaultFetch
/** Checks all input signals and updates the status as necessary.
* @return: Returns if the status has changed due to input signals.
*/
bool checkSignalsAndUpdate(unsigned tid);
bool checkSignalsAndUpdate(ThreadID tid);
/** Does the actual fetching of instructions and passing them on to the
* next stage.
@ -298,19 +298,20 @@ class DefaultFetch
void recvRetry();
/** Returns the appropriate thread to fetch, given the fetch policy. */
int getFetchingThread(FetchPriority &fetch_priority);
ThreadID getFetchingThread(FetchPriority &fetch_priority);
/** Returns the appropriate thread to fetch using a round robin policy. */
int roundRobin();
ThreadID roundRobin();
/** Returns the appropriate thread to fetch using the IQ count policy. */
int iqCount();
ThreadID iqCount();
/** Returns the appropriate thread to fetch using the LSQ count policy. */
int lsqCount();
ThreadID lsqCount();
/** Returns the appropriate thread to fetch using the branch count policy. */
int branchCount();
/** Returns the appropriate thread to fetch using the branch count
* policy. */
ThreadID branchCount();
private:
/** Pointer to the O3CPU. */
@ -400,7 +401,7 @@ class DefaultFetch
PacketPtr retryPkt;
/** The thread that is waiting on the cache to tell fetch to retry. */
int retryTid;
ThreadID retryTid;
/** Cache block size. */
int cacheBlkSize;
@ -424,16 +425,16 @@ class DefaultFetch
Counter lastIcacheStall[Impl::MaxThreads];
/** List of Active Threads */
std::list<unsigned> *activeThreads;
std::list<ThreadID> *activeThreads;
/** Number of threads. */
unsigned numThreads;
ThreadID numThreads;
/** Number of threads that are actively fetching. */
unsigned numFetchingThreads;
ThreadID numFetchingThreads;
/** Thread ID being fetched. */
int threadFetched;
ThreadID threadFetched;
/** Checks if there is an interrupt pending. If there is, fetch
* must stop once it is not fetching PAL instructions.

120
src/cpu/o3/fetch_impl.hh
View file

@ -51,6 +51,8 @@
#include "sim/system.hh"
#endif // FULL_SYSTEM
using namespace std;
template<class Impl>
void
DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
@ -122,7 +124,7 @@ DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
fetchWidth(params->fetchWidth),
cacheBlocked(false),
retryPkt(NULL),
retryTid(-1),
retryTid(InvalidThreadID),
numThreads(params->numThreads),
numFetchingThreads(params->smtNumFetchingThreads),
interruptPending(false),
@ -292,7 +294,7 @@ DefaultFetch<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer)
template<class Impl>
void
DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
DefaultFetch<Impl>::setActiveThreads(std::list<ThreadID> *at_ptr)
{
activeThreads = at_ptr;
}
@ -312,13 +314,13 @@ void
DefaultFetch<Impl>::initStage()
{
// Setup PC and nextPC with initial state.
for (int tid = 0; tid < numThreads; tid++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
PC[tid] = cpu->readPC(tid);
nextPC[tid] = cpu->readNextPC(tid);
microPC[tid] = cpu->readMicroPC(tid);
}
for (int tid=0; tid < numThreads; tid++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
fetchStatus[tid] = Running;
@ -350,7 +352,7 @@ DefaultFetch<Impl>::setIcache()
// Create mask to get rid of offset bits.
cacheBlkMask = (cacheBlkSize - 1);
for (int tid=0; tid < numThreads; tid++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
// Create space to store a cache line.
cacheData[tid] = new uint8_t[cacheBlkSize];
cacheDataPC[tid] = 0;
@ -362,7 +364,7 @@ template<class Impl>
void
DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
{
unsigned tid = pkt->req->threadId();
ThreadID tid = pkt->req->threadId();
DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
@ -437,7 +439,7 @@ void
DefaultFetch<Impl>::takeOverFrom()
{
// Reset all state
for (int i = 0; i < Impl::MaxThreads; ++i) {
for (ThreadID i = 0; i < Impl::MaxThreads; ++i) {
stalls[i].decode = 0;
stalls[i].rename = 0;
stalls[i].iew = 0;
@ -518,7 +520,7 @@ DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
//would reset the micro pc to 0.
next_MicroPC = 0;
int tid = inst->threadNumber;
ThreadID tid = inst->threadNumber;
Addr pred_PC = next_PC;
predict_taken = branchPred.predict(inst, pred_PC, tid);
@ -560,7 +562,7 @@ DefaultFetch<Impl>::lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC,
template <class Impl>
bool
DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid)
DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, ThreadID tid)
{
Fault fault = NoFault;
@ -637,7 +639,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
// exists within the cache.
if (!icachePort->sendTiming(data_pkt)) {
assert(retryPkt == NULL);
assert(retryTid == -1);
assert(retryTid == InvalidThreadID);
DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
fetchStatus[tid] = IcacheWaitRetry;
retryPkt = data_pkt;
@ -666,7 +668,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
template <class Impl>
inline void
DefaultFetch<Impl>::doSquash(const Addr &new_PC,
const Addr &new_NPC, const Addr &new_microPC, unsigned tid)
const Addr &new_NPC, const Addr &new_microPC, ThreadID tid)
{
DPRINTF(Fetch, "[tid:%i]: Squashing, setting PC to: %#x, NPC to: %#x.\n",
tid, new_PC, new_NPC);
@ -690,7 +692,7 @@ DefaultFetch<Impl>::doSquash(const Addr &new_PC,
delete retryPkt;
}
retryPkt = NULL;
retryTid = -1;
retryTid = InvalidThreadID;
}
fetchStatus[tid] = Squashing;
@ -702,7 +704,7 @@ template<class Impl>
void
DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
const Addr &new_MicroPC,
const InstSeqNum &seq_num, unsigned tid)
const InstSeqNum &seq_num, ThreadID tid)
{
DPRINTF(Fetch, "[tid:%i]: Squashing from decode.\n",tid);
@ -715,7 +717,7 @@ DefaultFetch<Impl>::squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
template<class Impl>
bool
DefaultFetch<Impl>::checkStall(unsigned tid) const
DefaultFetch<Impl>::checkStall(ThreadID tid) const
{
bool ret_val = false;
@ -744,11 +746,11 @@ typename DefaultFetch<Impl>::FetchStatus
DefaultFetch<Impl>::updateFetchStatus()
{
//Check Running
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (fetchStatus[tid] == Running ||
fetchStatus[tid] == Squashing ||
@ -783,7 +785,7 @@ template <class Impl>
void
DefaultFetch<Impl>::squash(const Addr &new_PC, const Addr &new_NPC,
const Addr &new_MicroPC,
const InstSeqNum &seq_num, unsigned tid)
const InstSeqNum &seq_num, ThreadID tid)
{
DPRINTF(Fetch, "[tid:%u]: Squash from commit.\n",tid);
@ -797,14 +799,14 @@ template <class Impl>
void
DefaultFetch<Impl>::tick()
{
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
bool status_change = false;
wroteToTimeBuffer = false;
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
// Check the signals for each thread to determine the proper status
// for each thread.
@ -851,7 +853,7 @@ DefaultFetch<Impl>::tick()
template <class Impl>
bool
DefaultFetch<Impl>::checkSignalsAndUpdate(unsigned tid)
DefaultFetch<Impl>::checkSignalsAndUpdate(ThreadID tid)
{
// Update the per thread stall statuses.
if (fromDecode->decodeBlock[tid]) {
@ -1000,9 +1002,9 @@ DefaultFetch<Impl>::fetch(bool &status_change)
//////////////////////////////////////////
// Start actual fetch
//////////////////////////////////////////
int tid = getFetchingThread(fetchPolicy);
ThreadID tid = getFetchingThread(fetchPolicy);
if (tid == -1 || drainPending) {
if (tid == InvalidThreadID || drainPending) {
DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
// Breaks looping condition in tick()
@ -1277,17 +1279,17 @@ DefaultFetch<Impl>::recvRetry()
{
if (retryPkt != NULL) {
assert(cacheBlocked);
assert(retryTid != -1);
assert(retryTid != InvalidThreadID);
assert(fetchStatus[retryTid] == IcacheWaitRetry);
if (icachePort->sendTiming(retryPkt)) {
fetchStatus[retryTid] = IcacheWaitResponse;
retryPkt = NULL;
retryTid = -1;
retryTid = InvalidThreadID;
cacheBlocked = false;
}
} else {
assert(retryTid == -1);
assert(retryTid == InvalidThreadID);
// Access has been squashed since it was sent out. Just clear
// the cache being blocked.
cacheBlocked = false;
@ -1300,7 +1302,7 @@ DefaultFetch<Impl>::recvRetry()
// //
///////////////////////////////////////
template<class Impl>
int
ThreadID
DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
{
if (numThreads > 1) {
@ -1322,36 +1324,35 @@ DefaultFetch<Impl>::getFetchingThread(FetchPriority &fetch_priority)
return branchCount();
default:
return -1;
return InvalidThreadID;
}
} else {
std::list<unsigned>::iterator thread = activeThreads->begin();
list<ThreadID>::iterator thread = activeThreads->begin();
if (thread == activeThreads->end()) {
return -1;
return InvalidThreadID;
}
int tid = *thread;
ThreadID tid = *thread;
if (fetchStatus[tid] == Running ||
fetchStatus[tid] == IcacheAccessComplete ||
fetchStatus[tid] == Idle) {
return tid;
} else {
return -1;
return InvalidThreadID;
}
}
}
template<class Impl>
int
ThreadID
DefaultFetch<Impl>::roundRobin()
{
std::list<unsigned>::iterator pri_iter = priorityList.begin();
std::list<unsigned>::iterator end = priorityList.end();
list<ThreadID>::iterator pri_iter = priorityList.begin();
list<ThreadID>::iterator end = priorityList.end();
int high_pri;
ThreadID high_pri;
while (pri_iter != end) {
high_pri = *pri_iter;
@ -1371,27 +1372,26 @@ DefaultFetch<Impl>::roundRobin()
pri_iter++;
}
return -1;
return InvalidThreadID;
}
template<class Impl>
int
ThreadID
DefaultFetch<Impl>::iqCount()
{
std::priority_queue<unsigned> PQ;
std::priority_queue<ThreadID> PQ;
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
PQ.push(fromIEW->iewInfo[tid].iqCount);
}
while (!PQ.empty()) {
unsigned high_pri = PQ.top();
ThreadID high_pri = PQ.top();
if (fetchStatus[high_pri] == Running ||
fetchStatus[high_pri] == IcacheAccessComplete ||
@ -1402,27 +1402,26 @@ DefaultFetch<Impl>::iqCount()
}
return -1;
return InvalidThreadID;
}
template<class Impl>
int
ThreadID
DefaultFetch<Impl>::lsqCount()
{
std::priority_queue<unsigned> PQ;
std::priority_queue<ThreadID> PQ;
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
PQ.push(fromIEW->iewInfo[tid].ldstqCount);
}
while (!PQ.empty()) {
unsigned high_pri = PQ.top();
ThreadID high_pri = PQ.top();
if (fetchStatus[high_pri] == Running ||
fetchStatus[high_pri] == IcacheAccessComplete ||
@ -1430,20 +1429,21 @@ DefaultFetch<Impl>::lsqCount()
return high_pri;
else
PQ.pop();
}
return -1;
return InvalidThreadID;
}
template<class Impl>
int
ThreadID
DefaultFetch<Impl>::branchCount()
{
std::list<unsigned>::iterator thread = activeThreads->begin();
#if 0
list<ThreadID>::iterator thread = activeThreads->begin();
assert(thread != activeThreads->end());
unsigned tid = *thread;
ThreadID tid = *thread;
#endif
panic("Branch Count Fetch policy unimplemented\n");
return 0 * tid;
return InvalidThreadID;
}

2
src/cpu/o3/free_list.cc
View file

@ -32,7 +32,7 @@
#include "cpu/o3/free_list.hh"
SimpleFreeList::SimpleFreeList(unsigned activeThreads,
SimpleFreeList::SimpleFreeList(ThreadID activeThreads,
unsigned _numLogicalIntRegs,
unsigned _numPhysicalIntRegs,
unsigned _numLogicalFloatRegs,

2
src/cpu/o3/free_list.hh
View file

@ -85,7 +85,7 @@ class SimpleFreeList
* @param _numLogicalFloatRegs Number of logical fp registers.
* @param _numPhysicalFloatRegs Number of physical fp registers.
*/
SimpleFreeList(unsigned activeThreads,
SimpleFreeList(ThreadID activeThreads,
unsigned _numLogicalIntRegs,
unsigned _numPhysicalIntRegs,
unsigned _numLogicalFloatRegs,

37
src/cpu/o3/iew.hh
View file

@ -31,12 +31,11 @@
#ifndef __CPU_O3_IEW_HH__
#define __CPU_O3_IEW_HH__
#include "config/full_system.hh"
#include <queue>
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "config/full_system.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/scoreboard.hh"
#include "cpu/o3/lsq.hh"
@ -139,7 +138,7 @@ class DefaultIEW
void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
/** Sets pointer to list of active threads. */
void setActiveThreads(std::list<unsigned> *at_ptr);
void setActiveThreads(std::list<ThreadID> *at_ptr);
/** Sets pointer to the scoreboard. */
void setScoreboard(Scoreboard *sb_ptr);
@ -160,7 +159,7 @@ class DefaultIEW
bool isSwitchedOut() { return switchedOut; }
/** Squashes instructions in IEW for a specific thread. */
void squash(unsigned tid);
void squash(ThreadID tid);
/** Wakes all dependents of a completed instruction. */
void wakeDependents(DynInstPtr &inst);
@ -177,7 +176,7 @@ class DefaultIEW
void instToCommit(DynInstPtr &inst);
/** Inserts unused instructions of a thread into the skid buffer. */
void skidInsert(unsigned tid);
void skidInsert(ThreadID tid);
/** Returns the max of the number of entries in all of the skid buffers. */
int skidCount();
@ -209,7 +208,7 @@ class DefaultIEW
bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); }
/** Returns if the LSQ has any stores to writeback. */
bool hasStoresToWB(unsigned tid) { return ldstQueue.hasStoresToWB(tid); }
bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
void incrWb(InstSeqNum &sn)
{
@ -256,31 +255,31 @@ class DefaultIEW
/** Sends commit proper information for a squash due to a branch
* mispredict.
*/
void squashDueToBranch(DynInstPtr &inst, unsigned thread_id);
void squashDueToBranch(DynInstPtr &inst, ThreadID tid);
/** Sends commit proper information for a squash due to a memory order
* violation.
*/
void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id);
void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid);
/** Sends commit proper information for a squash due to memory becoming
* blocked (younger issued instructions must be retried).
*/
void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id);
void squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid);
/** Sets Dispatch to blocked, and signals back to other stages to block. */
void block(unsigned thread_id);
void block(ThreadID tid);
/** Unblocks Dispatch if the skid buffer is empty, and signals back to
* other stages to unblock.
*/
void unblock(unsigned thread_id);
void unblock(ThreadID tid);
/** Determines proper actions to take given Dispatch's status. */
void dispatch(unsigned tid);
void dispatch(ThreadID tid);
/** Dispatches instructions to IQ and LSQ. */
void dispatchInsts(unsigned tid);
void dispatchInsts(ThreadID tid);
/** Executes instructions. In the case of memory operations, it informs the
* LSQ to execute the instructions. Also handles any redirects that occur
@ -301,16 +300,16 @@ class DefaultIEW
unsigned validInstsFromRename();
/** Reads the stall signals. */
void readStallSignals(unsigned tid);
void readStallSignals(ThreadID tid);
/** Checks if any of the stall conditions are currently true. */
bool checkStall(unsigned tid);
bool checkStall(ThreadID tid);
/** Processes inputs and changes state accordingly. */
void checkSignalsAndUpdate(unsigned tid);
void checkSignalsAndUpdate(ThreadID tid);
/** Removes instructions from rename from a thread's instruction list. */
void emptyRenameInsts(unsigned tid);
void emptyRenameInsts(ThreadID tid);
/** Sorts instructions coming from rename into lists separated by thread. */
void sortInsts();
@ -453,10 +452,10 @@ class DefaultIEW
unsigned wbMax;
/** Number of active threads. */
unsigned numThreads;
ThreadID numThreads;
/** Pointer to list of active threads. */
std::list<unsigned> *activeThreads;
std::list<ThreadID> *activeThreads;
/** Maximum size of the skid buffer. */
unsigned skidBufferMax;

131
src/cpu/o3/iew_impl.hh
View file

@ -39,6 +39,8 @@
#include "cpu/o3/iew.hh"
#include "params/DerivO3CPU.hh"
using namespace std;
template<class Impl>
DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
: issueToExecQueue(params->backComSize, params->forwardComSize),
@ -66,10 +68,10 @@ DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
// Instruction queue needs the queue between issue and execute.
instQueue.setIssueToExecuteQueue(&issueToExecQueue);
for (int i=0; i < numThreads; i++) {
dispatchStatus[i] = Running;
stalls[i].commit = false;
fetchRedirect[i] = false;
for (ThreadID tid = 0; tid < numThreads; tid++) {
dispatchStatus[tid] = Running;
stalls[tid].commit = false;
fetchRedirect[tid] = false;
}
wbMax = wbWidth * params->wbDepth;
@ -164,7 +166,7 @@ DefaultIEW<Impl>::regStats()
.desc("Number of executed instructions");
iewExecLoadInsts
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".iewExecLoadInsts")
.desc("Number of load instructions executed")
.flags(total);
@ -174,25 +176,25 @@ DefaultIEW<Impl>::regStats()
.desc("Number of squashed instructions skipped in execute");
iewExecutedSwp
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".EXEC:swp")
.desc("number of swp insts executed")
.flags(total);
iewExecutedNop
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".EXEC:nop")
.desc("number of nop insts executed")
.flags(total);
iewExecutedRefs
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".EXEC:refs")
.desc("number of memory reference insts executed")
.flags(total);
iewExecutedBranches
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".EXEC:branches")
.desc("Number of branches executed")
.flags(total);
@ -211,31 +213,31 @@ DefaultIEW<Impl>::regStats()
iewExecRate = iewExecutedInsts / cpu->numCycles;
iewInstsToCommit
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".WB:sent")
.desc("cumulative count of insts sent to commit")
.flags(total);
writebackCount
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".WB:count")
.desc("cumulative count of insts written-back")
.flags(total);
producerInst
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".WB:producers")
.desc("num instructions producing a value")
.flags(total);
consumerInst
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".WB:consumers")
.desc("num instructions consuming a value")
.flags(total);
wbPenalized
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".WB:penalized")
.desc("number of instrctions required to write to 'other' IQ")
.flags(total);
@ -265,7 +267,7 @@ template<class Impl>
void
DefaultIEW<Impl>::initStage()
{
for (int tid=0; tid < numThreads; tid++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
toRename->iewInfo[tid].usedIQ = true;
toRename->iewInfo[tid].freeIQEntries =
instQueue.numFreeEntries(tid);
@ -318,7 +320,7 @@ DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
template<class Impl>
void
DefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
{
activeThreads = at_ptr;
@ -361,11 +363,11 @@ DefaultIEW<Impl>::switchOut()
ldstQueue.switchOut();
fuPool->switchOut();
for (int i = 0; i < numThreads; i++) {
while (!insts[i].empty())
insts[i].pop();
while (!skidBuffer[i].empty())
skidBuffer[i].pop();
for (ThreadID tid = 0; tid < numThreads; tid++) {
while (!insts[tid].empty())
insts[tid].pop();
while (!skidBuffer[tid].empty())
skidBuffer[tid].pop();
}
}
@ -386,10 +388,10 @@ DefaultIEW<Impl>::takeOverFrom()
initStage();
cpu->activityThisCycle();
for (int i=0; i < numThreads; i++) {
dispatchStatus[i] = Running;
stalls[i].commit = false;
fetchRedirect[i] = false;
for (ThreadID tid = 0; tid < numThreads; tid++) {
dispatchStatus[tid] = Running;
stalls[tid].commit = false;
fetchRedirect[tid] = false;
}
updateLSQNextCycle = false;
@ -401,10 +403,9 @@ DefaultIEW<Impl>::takeOverFrom()
template<class Impl>
void
DefaultIEW<Impl>::squash(unsigned tid)
DefaultIEW<Impl>::squash(ThreadID tid)
{
DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n",
tid);
DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
// Tell the IQ to start squashing.
instQueue.squash(tid);
@ -433,7 +434,7 @@ DefaultIEW<Impl>::squash(unsigned tid)
template<class Impl>
void
DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
{
DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
"[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
@ -464,7 +465,7 @@ DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid)
template<class Impl>
void
DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
{
DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
"PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
@ -482,7 +483,7 @@ DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
template<class Impl>
void
DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
{
DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
"PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
@ -503,7 +504,7 @@ DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
template<class Impl>
void
DefaultIEW<Impl>::block(unsigned tid)
DefaultIEW<Impl>::block(ThreadID tid)
{
DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
@ -522,7 +523,7 @@ DefaultIEW<Impl>::block(unsigned tid)
template<class Impl>
void
DefaultIEW<Impl>::unblock(unsigned tid)
DefaultIEW<Impl>::unblock(ThreadID tid)
{
DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
"buffer %u.\n",tid, tid);
@ -605,7 +606,7 @@ DefaultIEW<Impl>::validInstsFromRename()
template<class Impl>
void
DefaultIEW<Impl>::skidInsert(unsigned tid)
DefaultIEW<Impl>::skidInsert(ThreadID tid)
{
DynInstPtr inst = NULL;
@ -631,11 +632,11 @@ DefaultIEW<Impl>::skidCount()
{
int max=0;
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
unsigned thread_count = skidBuffer[tid].size();
if (max < thread_count)
max = thread_count;
@ -648,11 +649,11 @@ template<class Impl>
bool
DefaultIEW<Impl>::skidsEmpty()
{
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (!skidBuffer[tid].empty())
return false;
@ -667,11 +668,11 @@ DefaultIEW<Impl>::updateStatus()
{
bool any_unblocking = false;
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (dispatchStatus[tid] == Unblocking) {
any_unblocking = true;
@ -711,7 +712,7 @@ DefaultIEW<Impl>::resetEntries()
template <class Impl>
void
DefaultIEW<Impl>::readStallSignals(unsigned tid)
DefaultIEW<Impl>::readStallSignals(ThreadID tid)
{
if (fromCommit->commitBlock[tid]) {
stalls[tid].commit = true;
@ -725,7 +726,7 @@ DefaultIEW<Impl>::readStallSignals(unsigned tid)
template <class Impl>
bool
DefaultIEW<Impl>::checkStall(unsigned tid)
DefaultIEW<Impl>::checkStall(ThreadID tid)
{
bool ret_val(false);
@ -761,7 +762,7 @@ DefaultIEW<Impl>::checkStall(unsigned tid)
template <class Impl>
void
DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid)
DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
{
// Check if there's a squash signal, squash if there is
// Check stall signals, block if there is.
@ -834,8 +835,8 @@ DefaultIEW<Impl>::sortInsts()
{
int insts_from_rename = fromRename->size;
#ifdef DEBUG
for (int i = 0; i < numThreads; i++)
assert(insts[i].empty());
for (ThreadID tid = 0; tid < numThreads; tid++)
assert(insts[tid].empty());
#endif
for (int i = 0; i < insts_from_rename; ++i) {
insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
@ -844,7 +845,7 @@ DefaultIEW<Impl>::sortInsts()
template <class Impl>
void
DefaultIEW<Impl>::emptyRenameInsts(unsigned tid)
DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
{
DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
@ -894,7 +895,7 @@ DefaultIEW<Impl>::deactivateStage()
template<class Impl>
void
DefaultIEW<Impl>::dispatch(unsigned tid)
DefaultIEW<Impl>::dispatch(ThreadID tid)
{
// If status is Running or idle,
// call dispatchInsts()
@ -942,7 +943,7 @@ DefaultIEW<Impl>::dispatch(unsigned tid)
template <class Impl>
void
DefaultIEW<Impl>::dispatchInsts(unsigned tid)
DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
{
// Obtain instructions from skid buffer if unblocking, or queue from rename
// otherwise.
@ -1169,11 +1170,11 @@ DefaultIEW<Impl>::executeInsts()
wbNumInst = 0;
wbCycle = 0;
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
fetchRedirect[tid] = false;
}
@ -1273,7 +1274,7 @@ DefaultIEW<Impl>::executeInsts()
// This probably needs to prioritize the redirects if a different
// scheduler is used. Currently the scheduler schedules the oldest
// instruction first, so the branch resolution order will be correct.
unsigned tid = inst->threadNumber;
ThreadID tid = inst->threadNumber;
if (!fetchRedirect[tid] ||
toCommit->squashedSeqNum[tid] > inst->seqNum) {
@ -1391,7 +1392,7 @@ DefaultIEW<Impl>::writebackInsts()
for (int inst_num = 0; inst_num < wbWidth &&
toCommit->insts[inst_num]; inst_num++) {
DynInstPtr inst = toCommit->insts[inst_num];
int tid = inst->threadNumber;
ThreadID tid = inst->threadNumber;
DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
inst->seqNum, inst->readPC());
@ -1439,12 +1440,12 @@ DefaultIEW<Impl>::tick()
// Free function units marked as being freed this cycle.
fuPool->processFreeUnits();
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
// Check stall and squash signals, dispatch any instructions.
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
@ -1486,7 +1487,7 @@ DefaultIEW<Impl>::tick()
threads = activeThreads->begin();
while (threads != end) {
unsigned tid = (*threads++);
ThreadID tid = (*threads++);
DPRINTF(IEW,"Processing [tid:%i]\n",tid);
@ -1552,14 +1553,14 @@ template <class Impl>
void
DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
{
int thread_number = inst->threadNumber;
ThreadID tid = inst->threadNumber;
//
// Pick off the software prefetches
//
#ifdef TARGET_ALPHA
if (inst->isDataPrefetch())
iewExecutedSwp[thread_number]++;
iewExecutedSwp[tid]++;
else
iewIewExecutedcutedInsts++;
#else
@ -1570,16 +1571,16 @@ DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
// Control operations
//
if (inst->isControl())
iewExecutedBranches[thread_number]++;
iewExecutedBranches[tid]++;
//
// Memory operations
//
if (inst->isMemRef()) {
iewExecutedRefs[thread_number]++;
iewExecutedRefs[tid]++;
if (inst->isLoad()) {
iewExecLoadInsts[thread_number]++;
iewExecLoadInsts[tid]++;
}
}
}

20
src/cpu/o3/inst_queue.hh
View file

@ -126,7 +126,7 @@ class InstructionQueue
void resetState();
/** Sets active threads list. */
void setActiveThreads(std::list<unsigned> *at_ptr);
void setActiveThreads(std::list<ThreadID> *at_ptr);
/** Sets the timer buffer between issue and execute. */
void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue);
@ -144,7 +144,7 @@ class InstructionQueue
bool isSwitchedOut() { return switchedOut; }
/** Number of entries needed for given amount of threads. */
int entryAmount(int num_threads);
int entryAmount(ThreadID num_threads);
/** Resets max entries for all threads. */
void resetEntries();
@ -153,13 +153,13 @@ class InstructionQueue
unsigned numFreeEntries();
/** Returns number of free entries for a thread. */
unsigned numFreeEntries(unsigned tid);
unsigned numFreeEntries(ThreadID tid);
/** Returns whether or not the IQ is full. */
bool isFull();
/** Returns whether or not the IQ is full for a specific thread. */
bool isFull(unsigned tid);
bool isFull(ThreadID tid);
/** Returns if there are any ready instructions in the IQ. */
bool hasReadyInsts();
@ -203,7 +203,7 @@ class InstructionQueue
* Commits all instructions up to and including the given sequence number,
* for a specific thread.
*/
void commit(const InstSeqNum &inst, unsigned tid = 0);
void commit(const InstSeqNum &inst, ThreadID tid = 0);
/** Wakes all dependents of a completed instruction. */
int wakeDependents(DynInstPtr &completed_inst);
@ -230,17 +230,17 @@ class InstructionQueue
* Squashes instructions for a thread. Squashing information is obtained
* from the time buffer.
*/
void squash(unsigned tid);
void squash(ThreadID tid);
/** Returns the number of used entries for a thread. */
unsigned getCount(unsigned tid) { return count[tid]; };
unsigned getCount(ThreadID tid) { return count[tid]; };
/** Debug function to print all instructions. */
void printInsts();
private:
/** Does the actual squashing. */
void doSquash(unsigned tid);
void doSquash(ThreadID tid);
/////////////////////////
// Various pointers
@ -368,10 +368,10 @@ class InstructionQueue
IQPolicy iqPolicy;
/** Number of Total Threads*/
unsigned numThreads;
ThreadID numThreads;
/** Pointer to list of active threads. */
std::list<unsigned> *activeThreads;
std::list<ThreadID> *activeThreads;
/** Per Thread IQ count */
unsigned count[Impl::MaxThreads];

81
src/cpu/o3/inst_queue_impl.hh
View file

@ -35,9 +35,10 @@
#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/inst_queue.hh"
#include "enums/OpClass.hh"
#include "params/DerivO3CPU.hh"
#include "sim/core.hh"
#include "params/DerivO3CPU.hh"
using namespace std;
template <class Impl>
InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
@ -93,9 +94,9 @@ InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
regScoreboard.resize(numPhysRegs);
//Initialize Mem Dependence Units
for (int i = 0; i < numThreads; i++) {
memDepUnit[i].init(params,i);
memDepUnit[i].setIQ(this);
for (ThreadID tid = 0; tid < numThreads; tid++) {
memDepUnit[tid].init(params, tid);
memDepUnit[tid].setIQ(this);
}
resetState();
@ -111,8 +112,8 @@ InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
iqPolicy = Dynamic;
//Set Max Entries to Total ROB Capacity
for (int i = 0; i < numThreads; i++) {
maxEntries[i] = numEntries;
for (ThreadID tid = 0; tid < numThreads; tid++) {
maxEntries[tid] = numEntries;
}
} else if (policy == "partitioned") {
@ -122,8 +123,8 @@ InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
int part_amt = numEntries / numThreads;
//Divide ROB up evenly
for (int i = 0; i < numThreads; i++) {
maxEntries[i] = part_amt;
for (ThreadID tid = 0; tid < numThreads; tid++) {
maxEntries[tid] = part_amt;
}
DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
@ -136,8 +137,8 @@ InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
int thresholdIQ = (int)((double)threshold * numEntries);
//Divide up by threshold amount
for (int i = 0; i < numThreads; i++) {
maxEntries[i] = thresholdIQ;
for (ThreadID tid = 0; tid < numThreads; tid++) {
maxEntries[tid] = thresholdIQ;
}
DPRINTF(IQ, "IQ sharing policy set to Threshold:"
@ -315,9 +316,9 @@ InstructionQueue<Impl>::regStats()
;
fuBusyRate = fuBusy / iqInstsIssued;
for ( int i=0; i < numThreads; i++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
// Tell mem dependence unit to reg stats as well.
memDepUnit[i].regStats();
memDepUnit[tid].regStats();
}
}
@ -326,9 +327,9 @@ void
InstructionQueue<Impl>::resetState()
{
//Initialize thread IQ counts
for (int i = 0; i <numThreads; i++) {
count[i] = 0;
instList[i].clear();
for (ThreadID tid = 0; tid <numThreads; tid++) {
count[tid] = 0;
instList[tid].clear();
}
// Initialize the number of free IQ entries.
@ -343,8 +344,8 @@ InstructionQueue<Impl>::resetState()
regScoreboard[i] = false;
}
for (int i = 0; i < numThreads; ++i) {
squashedSeqNum[i] = 0;
for (ThreadID tid = 0; tid < numThreads; ++tid) {
squashedSeqNum[tid] = 0;
}
for (int i = 0; i < Num_OpClasses; ++i) {
@ -359,7 +360,7 @@ InstructionQueue<Impl>::resetState()
template <class Impl>
void
InstructionQueue<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
{
activeThreads = at_ptr;
}
@ -395,8 +396,8 @@ InstructionQueue<Impl>::switchOut()
dependGraph.reset();
instsToExecute.clear();
switchedOut = true;
for (int i = 0; i < numThreads; ++i) {
memDepUnit[i].switchOut();
for (ThreadID tid = 0; tid < numThreads; ++tid) {
memDepUnit[tid].switchOut();
}
}
@ -409,7 +410,7 @@ InstructionQueue<Impl>::takeOverFrom()
template <class Impl>
int
InstructionQueue<Impl>::entryAmount(int num_threads)
InstructionQueue<Impl>::entryAmount(ThreadID num_threads)
{
if (iqPolicy == Partitioned) {
return numEntries / num_threads;
@ -426,11 +427,11 @@ InstructionQueue<Impl>::resetEntries()
if (iqPolicy != Dynamic || numThreads > 1) {
int active_threads = activeThreads->size();
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (iqPolicy == Partitioned) {
maxEntries[tid] = numEntries / active_threads;
@ -450,7 +451,7 @@ InstructionQueue<Impl>::numFreeEntries()
template <class Impl>
unsigned
InstructionQueue<Impl>::numFreeEntries(unsigned tid)
InstructionQueue<Impl>::numFreeEntries(ThreadID tid)
{
return maxEntries[tid] - count[tid];
}
@ -470,7 +471,7 @@ InstructionQueue<Impl>::isFull()
template <class Impl>
bool
InstructionQueue<Impl>::isFull(unsigned tid)
InstructionQueue<Impl>::isFull(ThreadID tid)
{
if (numFreeEntries(tid) == 0) {
return(true);
@ -726,7 +727,7 @@ InstructionQueue<Impl>::scheduleReadyInsts()
int idx = -2;
int op_latency = 1;
int tid = issuing_inst->threadNumber;
ThreadID tid = issuing_inst->threadNumber;
if (op_class != No_OpClass) {
idx = fuPool->getUnit(op_class);
@ -825,7 +826,7 @@ InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
assert(inst_it != nonSpecInsts.end());
unsigned tid = (*inst_it).second->threadNumber;
ThreadID tid = (*inst_it).second->threadNumber;
(*inst_it).second->setAtCommit();
@ -844,7 +845,7 @@ InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
template <class Impl>
void
InstructionQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid)
InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid)
{
DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
tid,inst);
@ -976,7 +977,7 @@ template <class Impl>
void
InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
{
int tid = completed_inst->threadNumber;
ThreadID tid = completed_inst->threadNumber;
DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n",
completed_inst->readPC(), completed_inst->seqNum);
@ -999,7 +1000,7 @@ InstructionQueue<Impl>::violation(DynInstPtr &store,
template <class Impl>
void
InstructionQueue<Impl>::squash(unsigned tid)
InstructionQueue<Impl>::squash(ThreadID tid)
{
DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
"the IQ.\n", tid);
@ -1019,7 +1020,7 @@ InstructionQueue<Impl>::squash(unsigned tid)
template <class Impl>
void
InstructionQueue<Impl>::doSquash(unsigned tid)
InstructionQueue<Impl>::doSquash(ThreadID tid)
{
// Start at the tail.
ListIt squash_it = instList[tid].end();
@ -1253,10 +1254,10 @@ InstructionQueue<Impl>::countInsts()
// Change the #if if you want to use this method.
int total_insts = 0;
for (int i = 0; i < numThreads; ++i) {
ListIt count_it = instList[i].begin();
for (ThreadID tid = 0; tid < numThreads; ++tid) {
ListIt count_it = instList[tid].begin();
while (count_it != instList[i].end()) {
while (count_it != instList[tid].end()) {
if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
if (!(*count_it)->isIssued()) {
++total_insts;
@ -1325,15 +1326,13 @@ template <class Impl>
void
InstructionQueue<Impl>::dumpInsts()
{
for (int i = 0; i < numThreads; ++i) {
for (ThreadID tid = 0; tid < numThreads; ++tid) {
int num = 0;
int valid_num = 0;
ListIt inst_list_it = instList[i].begin();
ListIt inst_list_it = instList[tid].begin();
while (inst_list_it != instList[i].end())
{
cprintf("Instruction:%i\n",
num);
while (inst_list_it != instList[tid].end()) {
cprintf("Instruction:%i\n", num);
if (!(*inst_list_it)->isSquashed()) {
if (!(*inst_list_it)->isIssued()) {
++valid_num;

76
src/cpu/o3/lsq.hh
View file

@ -74,24 +74,24 @@ class LSQ {
Port *getDcachePort() { return &dcachePort; }
/** Sets the pointer to the list of active threads. */
void setActiveThreads(std::list<unsigned> *at_ptr);
void setActiveThreads(std::list<ThreadID> *at_ptr);
/** Switches out the LSQ. */
void switchOut();
/** Takes over execution from another CPU's thread. */
void takeOverFrom();
/** Number of entries needed for the given amount of threads.*/
int entryAmount(int num_threads);
void removeEntries(unsigned tid);
int entryAmount(ThreadID num_threads);
void removeEntries(ThreadID tid);
/** Reset the max entries for each thread. */
void resetEntries();
/** Resize the max entries for a thread. */
void resizeEntries(unsigned size, unsigned tid);
void resizeEntries(unsigned size, ThreadID tid);
/** Ticks the LSQ. */
void tick();
/** Ticks a specific LSQ Unit. */
void tick(unsigned tid)
void tick(ThreadID tid)
{ thread[tid].tick(); }
/** Inserts a load into the LSQ. */
@ -108,13 +108,13 @@ class LSQ {
/**
* Commits loads up until the given sequence number for a specific thread.
*/
void commitLoads(InstSeqNum &youngest_inst, unsigned tid)
void commitLoads(InstSeqNum &youngest_inst, ThreadID tid)
{ thread[tid].commitLoads(youngest_inst); }
/**
* Commits stores up until the given sequence number for a specific thread.
*/
void commitStores(InstSeqNum &youngest_inst, unsigned tid)
void commitStores(InstSeqNum &youngest_inst, ThreadID tid)
{ thread[tid].commitStores(youngest_inst); }
/**
@ -123,12 +123,12 @@ class LSQ {
*/
void writebackStores();
/** Same as above, but only for one thread. */
void writebackStores(unsigned tid);
void writebackStores(ThreadID tid);
/**
* Squash instructions from a thread until the specified sequence number.
*/
void squash(const InstSeqNum &squashed_num, unsigned tid)
void squash(const InstSeqNum &squashed_num, ThreadID tid)
{ thread[tid].squash(squashed_num); }
/** Returns whether or not there was a memory ordering violation. */
@ -137,41 +137,41 @@ class LSQ {
* Returns whether or not there was a memory ordering violation for a
* specific thread.
*/
bool violation(unsigned tid)
bool violation(ThreadID tid)
{ return thread[tid].violation(); }
/** Returns if a load is blocked due to the memory system for a specific
* thread.
*/
bool loadBlocked(unsigned tid)
bool loadBlocked(ThreadID tid)
{ return thread[tid].loadBlocked(); }
bool isLoadBlockedHandled(unsigned tid)
bool isLoadBlockedHandled(ThreadID tid)
{ return thread[tid].isLoadBlockedHandled(); }
void setLoadBlockedHandled(unsigned tid)
void setLoadBlockedHandled(ThreadID tid)
{ thread[tid].setLoadBlockedHandled(); }
/** Gets the instruction that caused the memory ordering violation. */
DynInstPtr getMemDepViolator(unsigned tid)
DynInstPtr getMemDepViolator(ThreadID tid)
{ return thread[tid].getMemDepViolator(); }
/** Returns the head index of the load queue for a specific thread. */
int getLoadHead(unsigned tid)
int getLoadHead(ThreadID tid)
{ return thread[tid].getLoadHead(); }
/** Returns the sequence number of the head of the load queue. */
InstSeqNum getLoadHeadSeqNum(unsigned tid)
InstSeqNum getLoadHeadSeqNum(ThreadID tid)
{
return thread[tid].getLoadHeadSeqNum();
}
/** Returns the head index of the store queue. */
int getStoreHead(unsigned tid)
int getStoreHead(ThreadID tid)
{ return thread[tid].getStoreHead(); }
/** Returns the sequence number of the head of the store queue. */
InstSeqNum getStoreHeadSeqNum(unsigned tid)
InstSeqNum getStoreHeadSeqNum(ThreadID tid)
{
return thread[tid].getStoreHeadSeqNum();
}
@ -179,31 +179,31 @@ class LSQ {
/** Returns the number of instructions in all of the queues. */
int getCount();
/** Returns the number of instructions in the queues of one thread. */
int getCount(unsigned tid)
int getCount(ThreadID tid)
{ return thread[tid].getCount(); }
/** Returns the total number of loads in the load queue. */
int numLoads();
/** Returns the total number of loads for a single thread. */
int numLoads(unsigned tid)
int numLoads(ThreadID tid)
{ return thread[tid].numLoads(); }
/** Returns the total number of stores in the store queue. */
int numStores();
/** Returns the total number of stores for a single thread. */
int numStores(unsigned tid)
int numStores(ThreadID tid)
{ return thread[tid].numStores(); }
/** Returns the total number of loads that are ready. */
int numLoadsReady();
/** Returns the number of loads that are ready for a single thread. */
int numLoadsReady(unsigned tid)
int numLoadsReady(ThreadID tid)
{ return thread[tid].numLoadsReady(); }
/** Returns the number of free entries. */
unsigned numFreeEntries();
/** Returns the number of free entries for a specific thread. */
unsigned numFreeEntries(unsigned tid);
unsigned numFreeEntries(ThreadID tid);
/** Returns if the LSQ is full (either LQ or SQ is full). */
bool isFull();
@ -211,17 +211,17 @@ class LSQ {
* Returns if the LSQ is full for a specific thread (either LQ or SQ is
* full).
*/
bool isFull(unsigned tid);
bool isFull(ThreadID tid);
/** Returns if any of the LQs are full. */
bool lqFull();
/** Returns if the LQ of a given thread is full. */
bool lqFull(unsigned tid);
bool lqFull(ThreadID tid);
/** Returns if any of the SQs are full. */
bool sqFull();
/** Returns if the SQ of a given thread is full. */
bool sqFull(unsigned tid);
bool sqFull(ThreadID tid);
/**
* Returns if the LSQ is stalled due to a memory operation that must be
@ -232,7 +232,7 @@ class LSQ {
* Returns if the LSQ of a specific thread is stalled due to a memory
* operation that must be replayed.
*/
bool isStalled(unsigned tid);
bool isStalled(ThreadID tid);
/** Returns whether or not there are any stores to write back to memory. */
bool hasStoresToWB();
@ -240,11 +240,11 @@ class LSQ {
/** Returns whether or not a specific thread has any stores to write back
* to memory.
*/
bool hasStoresToWB(unsigned tid)
bool hasStoresToWB(ThreadID tid)
{ return thread[tid].hasStoresToWB(); }
/** Returns the number of stores a specific thread has to write back. */
int numStoresToWB(unsigned tid)
int numStoresToWB(ThreadID tid)
{ return thread[tid].numStoresToWB(); }
/** Returns if the LSQ will write back to memory this cycle. */
@ -252,22 +252,22 @@ class LSQ {
/** Returns if the LSQ of a specific thread will write back to memory this
* cycle.
*/
bool willWB(unsigned tid)
bool willWB(ThreadID tid)
{ return thread[tid].willWB(); }
/** Returns if the cache is currently blocked. */
bool cacheBlocked()
{ return retryTid != -1; }
{ return retryTid != InvalidThreadID; }
/** Sets the retry thread id, indicating that one of the LSQUnits
* tried to access the cache but the cache was blocked. */
void setRetryTid(int tid)
void setRetryTid(ThreadID tid)
{ retryTid = tid; }
/** Debugging function to print out all instructions. */
void dumpInsts();
/** Debugging function to print out instructions from a specific thread. */
void dumpInsts(unsigned tid)
void dumpInsts(ThreadID tid)
{ thread[tid].dumpInsts(); }
/** Executes a read operation, using the load specified at the load index. */
@ -345,7 +345,7 @@ class LSQ {
LSQUnit thread[Impl::MaxThreads];
/** List of Active Threads in System. */
std::list<unsigned> *activeThreads;
std::list<ThreadID> *activeThreads;
/** Total Size of LQ Entries. */
unsigned LQEntries;
@ -359,11 +359,11 @@ class LSQ {
unsigned maxSQEntries;
/** Number of Threads. */
unsigned numThreads;
ThreadID numThreads;
/** The thread id of the LSQ Unit that is currently waiting for a
* retry. */
int retryTid;
ThreadID retryTid;
};
template <class Impl>
@ -371,7 +371,7 @@ template <class T>
Fault
LSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
{
unsigned tid = req->threadId();
ThreadID tid = req->threadId();
return thread[tid].read(req, data, load_idx);
}
@ -381,7 +381,7 @@ template <class T>
Fault
LSQ<Impl>::write(RequestPtr req, T &data, int store_idx)
{
unsigned tid = req->threadId();
ThreadID tid = req->threadId();
return thread[tid].write(req, data, store_idx);
}

133
src/cpu/o3/lsq_impl.hh
View file

@ -33,9 +33,10 @@
#include <string>
#include "cpu/o3/lsq.hh"
#include "params/DerivO3CPU.hh"
using namespace std;
template<class Impl>
void
LSQ<Impl>::DcachePort::setPeer(Port *port)
@ -170,7 +171,7 @@ LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params)
}
//Initialize LSQs
for (int tid=0; tid < numThreads; tid++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
thread[tid].init(cpu, iew_ptr, params, this,
maxLQEntries, maxSQEntries, tid);
thread[tid].setDcachePort(&dcachePort);
@ -190,14 +191,14 @@ void
LSQ<Impl>::regStats()
{
//Initialize LSQs
for (int tid=0; tid < numThreads; tid++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
thread[tid].regStats();
}
}
template<class Impl>
void
LSQ<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
LSQ<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
{
activeThreads = at_ptr;
assert(activeThreads != 0);
@ -207,7 +208,7 @@ template <class Impl>
void
LSQ<Impl>::switchOut()
{
for (int tid = 0; tid < numThreads; tid++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
thread[tid].switchOut();
}
}
@ -216,14 +217,14 @@ template <class Impl>
void
LSQ<Impl>::takeOverFrom()
{
for (int tid = 0; tid < numThreads; tid++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
thread[tid].takeOverFrom();
}
}
template <class Impl>
int
LSQ<Impl>::entryAmount(int num_threads)
LSQ<Impl>::entryAmount(ThreadID num_threads)
{
if (lsqPolicy == Partitioned) {
return LQEntries / num_threads;
@ -249,11 +250,11 @@ LSQ<Impl>::resetEntries()
maxEntries = LQEntries;
}
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
resizeEntries(maxEntries, tid);
}
@ -262,7 +263,7 @@ LSQ<Impl>::resetEntries()
template<class Impl>
void
LSQ<Impl>::removeEntries(unsigned tid)
LSQ<Impl>::removeEntries(ThreadID tid)
{
thread[tid].clearLQ();
thread[tid].clearSQ();
@ -270,7 +271,7 @@ LSQ<Impl>::removeEntries(unsigned tid)
template<class Impl>
void
LSQ<Impl>::resizeEntries(unsigned size,unsigned tid)
LSQ<Impl>::resizeEntries(unsigned size, ThreadID tid)
{
thread[tid].resizeLQ(size);
thread[tid].resizeSQ(size);
@ -280,11 +281,11 @@ template<class Impl>
void
LSQ<Impl>::tick()
{
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
thread[tid].tick();
}
@ -294,7 +295,7 @@ template<class Impl>
void
LSQ<Impl>::insertLoad(DynInstPtr &load_inst)
{
unsigned tid = load_inst->threadNumber;
ThreadID tid = load_inst->threadNumber;
thread[tid].insertLoad(load_inst);
}
@ -303,7 +304,7 @@ template<class Impl>
void
LSQ<Impl>::insertStore(DynInstPtr &store_inst)
{
unsigned tid = store_inst->threadNumber;
ThreadID tid = store_inst->threadNumber;
thread[tid].insertStore(store_inst);
}
@ -312,7 +313,7 @@ template<class Impl>
Fault
LSQ<Impl>::executeLoad(DynInstPtr &inst)
{
unsigned tid = inst->threadNumber;
ThreadID tid = inst->threadNumber;
return thread[tid].executeLoad(inst);
}
@ -321,7 +322,7 @@ template<class Impl>
Fault
LSQ<Impl>::executeStore(DynInstPtr &inst)
{
unsigned tid = inst->threadNumber;
ThreadID tid = inst->threadNumber;
return thread[tid].executeStore(inst);
}
@ -330,11 +331,11 @@ template<class Impl>
void
LSQ<Impl>::writebackStores()
{
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (numStoresToWB(tid) > 0) {
DPRINTF(Writeback,"[tid:%i] Writing back stores. %i stores "
@ -350,11 +351,11 @@ bool
LSQ<Impl>::violation()
{
/* Answers: Does Anybody Have a Violation?*/
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (thread[tid].violation())
return true;
@ -369,11 +370,11 @@ LSQ<Impl>::getCount()
{
unsigned total = 0;
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
total += getCount(tid);
}
@ -387,11 +388,11 @@ LSQ<Impl>::numLoads()
{
unsigned total = 0;
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
total += numLoads(tid);
}
@ -405,11 +406,11 @@ LSQ<Impl>::numStores()
{
unsigned total = 0;
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
total += thread[tid].numStores();
}
@ -423,11 +424,11 @@ LSQ<Impl>::numLoadsReady()
{
unsigned total = 0;
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
total += thread[tid].numLoadsReady();
}
@ -441,11 +442,11 @@ LSQ<Impl>::numFreeEntries()
{
unsigned total = 0;
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
total += thread[tid].numFreeEntries();
}
@ -455,7 +456,7 @@ LSQ<Impl>::numFreeEntries()
template<class Impl>
unsigned
LSQ<Impl>::numFreeEntries(unsigned tid)
LSQ<Impl>::numFreeEntries(ThreadID tid)
{
//if (lsqPolicy == Dynamic)
//return numFreeEntries();
@ -467,11 +468,11 @@ template<class Impl>
bool
LSQ<Impl>::isFull()
{
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (!(thread[tid].lqFull() || thread[tid].sqFull()))
return false;
@ -482,7 +483,7 @@ LSQ<Impl>::isFull()
template<class Impl>
bool
LSQ<Impl>::isFull(unsigned tid)
LSQ<Impl>::isFull(ThreadID tid)
{
//@todo: Change to Calculate All Entries for
//Dynamic Policy
@ -496,11 +497,11 @@ template<class Impl>
bool
LSQ<Impl>::lqFull()
{
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (!thread[tid].lqFull())
return false;
@ -511,7 +512,7 @@ LSQ<Impl>::lqFull()
template<class Impl>
bool
LSQ<Impl>::lqFull(unsigned tid)
LSQ<Impl>::lqFull(ThreadID tid)
{
//@todo: Change to Calculate All Entries for
//Dynamic Policy
@ -525,11 +526,11 @@ template<class Impl>
bool
LSQ<Impl>::sqFull()
{
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (!sqFull(tid))
return false;
@ -540,7 +541,7 @@ LSQ<Impl>::sqFull()
template<class Impl>
bool
LSQ<Impl>::sqFull(unsigned tid)
LSQ<Impl>::sqFull(ThreadID tid)
{
//@todo: Change to Calculate All Entries for
//Dynamic Policy
@ -554,11 +555,11 @@ template<class Impl>
bool
LSQ<Impl>::isStalled()
{
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (!thread[tid].isStalled())
return false;
@ -569,7 +570,7 @@ LSQ<Impl>::isStalled()
template<class Impl>
bool
LSQ<Impl>::isStalled(unsigned tid)
LSQ<Impl>::isStalled(ThreadID tid)
{
if (lsqPolicy == Dynamic)
return isStalled();
@ -581,11 +582,11 @@ template<class Impl>
bool
LSQ<Impl>::hasStoresToWB()
{
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (hasStoresToWB(tid))
return true;
@ -598,11 +599,11 @@ template<class Impl>
bool
LSQ<Impl>::willWB()
{
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (willWB(tid))
return true;
@ -615,11 +616,11 @@ template<class Impl>
void
LSQ<Impl>::dumpInsts()
{
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
thread[tid].dumpInsts();
}

2
src/cpu/o3/lsq_unit.hh
View file

@ -325,7 +325,7 @@ class LSQUnit {
private:
/** The LSQUnit thread id. */
unsigned lsqID;
ThreadID lsqID;
/** The store queue. */
std::vector<SQEntry> storeQueue;

2
src/cpu/o3/lsq_unit_impl.hh
View file

@ -938,7 +938,7 @@ LSQUnit<Impl>::recvRetry()
storePostSend(retryPkt);
retryPkt = NULL;
isStoreBlocked = false;
lsq->setRetryTid(-1);
lsq->setRetryTid(InvalidThreadID);
} else {
// Still blocked!
++lsqCacheBlocked;

4
src/cpu/o3/mem_dep_unit.hh
View file

@ -86,7 +86,7 @@ class MemDepUnit
std::string name() const { return _name; }
/** Initializes the unit with parameters and a thread id. */
void init(DerivO3CPUParams *params, int tid);
void init(DerivO3CPUParams *params, ThreadID tid);
/** Registers statistics. */
void regStats();
@ -135,7 +135,7 @@ class MemDepUnit
/** Squashes all instructions up until a given sequence number for a
* specific thread.
*/
void squash(const InstSeqNum &squashed_num, unsigned tid);
void squash(const InstSeqNum &squashed_num, ThreadID tid);
/** Indicates an ordering violation between a store and a younger load. */
void violation(DynInstPtr &store_inst, DynInstPtr &violating_load);

16
src/cpu/o3/mem_dep_unit_impl.hh
View file

@ -54,7 +54,7 @@ MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params)
template <class MemDepPred, class Impl>
MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
{
for (int tid=0; tid < Impl::MaxThreads; tid++) {
for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
ListIt inst_list_it = instList[tid].begin();
@ -78,7 +78,7 @@ MemDepUnit<MemDepPred, Impl>::~MemDepUnit()
template <class MemDepPred, class Impl>
void
MemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, int tid)
MemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, ThreadID tid)
{
DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
@ -145,7 +145,7 @@ template <class MemDepPred, class Impl>
void
MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
{
unsigned tid = inst->threadNumber;
ThreadID tid = inst->threadNumber;
MemDepEntryPtr inst_entry = new MemDepEntry(inst);
@ -242,7 +242,7 @@ template <class MemDepPred, class Impl>
void
MemDepUnit<MemDepPred, Impl>::insertNonSpec(DynInstPtr &inst)
{
unsigned tid = inst->threadNumber;
ThreadID tid = inst->threadNumber;
MemDepEntryPtr inst_entry = new MemDepEntry(inst);
@ -292,7 +292,7 @@ MemDepUnit<MemDepPred, Impl>::insertBarrier(DynInstPtr &barr_inst)
DPRINTF(MemDepUnit, "Inserted a write barrier\n");
}
unsigned tid = barr_inst->threadNumber;
ThreadID tid = barr_inst->threadNumber;
MemDepEntryPtr inst_entry = new MemDepEntry(barr_inst);
@ -382,7 +382,7 @@ MemDepUnit<MemDepPred, Impl>::completed(DynInstPtr &inst)
"[sn:%lli].\n",
inst->readPC(), inst->seqNum);
unsigned tid = inst->threadNumber;
ThreadID tid = inst->threadNumber;
// Remove the instruction from the hash and the list.
MemDepHashIt hash_it = memDepHash.find(inst->seqNum);
@ -457,7 +457,7 @@ MemDepUnit<MemDepPred, Impl>::wakeDependents(DynInstPtr &inst)
template <class MemDepPred, class Impl>
void
MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num,
unsigned tid)
ThreadID tid)
{
if (!instsToReplay.empty()) {
ListIt replay_it = instsToReplay.begin();
@ -552,7 +552,7 @@ template <class MemDepPred, class Impl>
void
MemDepUnit<MemDepPred, Impl>::dumpLists()
{
for (unsigned tid=0; tid < Impl::MaxThreads; tid++) {
for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) {
cprintf("Instruction list %i size: %i\n",
tid, instList[tid].size());

23
src/cpu/o3/regfile.hh
View file

@ -230,27 +230,28 @@ class PhysRegFile
floatRegFile[reg_idx].q = val;
}
MiscReg readMiscRegNoEffect(int misc_reg, unsigned thread_id)
MiscReg
readMiscRegNoEffect(int misc_reg, ThreadID tid)
{
return miscRegs[thread_id].readRegNoEffect(misc_reg);
return miscRegs[tid].readRegNoEffect(misc_reg);
}
MiscReg readMiscReg(int misc_reg, unsigned thread_id)
MiscReg
readMiscReg(int misc_reg, ThreadID tid)
{
return miscRegs[thread_id].readReg(misc_reg, cpu->tcBase(thread_id));
return miscRegs[tid].readReg(misc_reg, cpu->tcBase(tid));
}
void setMiscRegNoEffect(int misc_reg,
const MiscReg &val, unsigned thread_id)
void
setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
{
miscRegs[thread_id].setRegNoEffect(misc_reg, val);
miscRegs[tid].setRegNoEffect(misc_reg, val);
}
void setMiscReg(int misc_reg, const MiscReg &val,
unsigned thread_id)
void
setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
{
miscRegs[thread_id].setReg(misc_reg, val,
cpu->tcBase(thread_id));
miscRegs[tid].setReg(misc_reg, val, cpu->tcBase(tid));
}
public:

42
src/cpu/o3/rename.hh
View file

@ -145,7 +145,7 @@ class DefaultRename
void initStage();
/** Sets pointer to list of active threads. */
void setActiveThreads(std::list<unsigned> *at_ptr);
void setActiveThreads(std::list<ThreadID> *at_ptr);
/** Sets pointer to rename maps (per-thread structures). */
void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
@ -169,7 +169,7 @@ class DefaultRename
void takeOverFrom();
/** Squashes all instructions in a thread. */
void squash(const InstSeqNum &squash_seq_num, unsigned tid);
void squash(const InstSeqNum &squash_seq_num, ThreadID tid);
/** Ticks rename, which processes all input signals and attempts to rename
* as many instructions as possible.
@ -185,17 +185,17 @@ class DefaultRename
* change (ie switching from blocking to unblocking).
* @param tid Thread id to rename instructions from.
*/
void rename(bool &status_change, unsigned tid);
void rename(bool &status_change, ThreadID tid);
/** Renames instructions for the given thread. Also handles serializing
* instructions.
*/
void renameInsts(unsigned tid);
void renameInsts(ThreadID tid);
/** Inserts unused instructions from a given thread into the skid buffer,
* to be renamed once rename unblocks.
*/
void skidInsert(unsigned tid);
void skidInsert(ThreadID tid);
/** Separates instructions from decode into individual lists of instructions
* sorted by thread.
@ -212,49 +212,49 @@ class DefaultRename
* blocked.
* @return Returns true if there is a status change.
*/
bool block(unsigned tid);
bool block(ThreadID tid);
/** Switches rename to unblocking if the skid buffer is empty, and signals
* back that rename has unblocked.
* @return Returns true if there is a status change.
*/
bool unblock(unsigned tid);
bool unblock(ThreadID tid);
/** Executes actual squash, removing squashed instructions. */
void doSquash(const InstSeqNum &squash_seq_num, unsigned tid);
void doSquash(const InstSeqNum &squash_seq_num, ThreadID tid);
/** Removes a committed instruction's rename history. */
void removeFromHistory(InstSeqNum inst_seq_num, unsigned tid);
void removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid);
/** Renames the source registers of an instruction. */
inline void renameSrcRegs(DynInstPtr &inst, unsigned tid);
inline void renameSrcRegs(DynInstPtr &inst, ThreadID tid);
/** Renames the destination registers of an instruction. */
inline void renameDestRegs(DynInstPtr &inst, unsigned tid);
inline void renameDestRegs(DynInstPtr &inst, ThreadID tid);
/** Calculates the number of free ROB entries for a specific thread. */
inline int calcFreeROBEntries(unsigned tid);
inline int calcFreeROBEntries(ThreadID tid);
/** Calculates the number of free IQ entries for a specific thread. */
inline int calcFreeIQEntries(unsigned tid);
inline int calcFreeIQEntries(ThreadID tid);
/** Calculates the number of free LSQ entries for a specific thread. */
inline int calcFreeLSQEntries(unsigned tid);
inline int calcFreeLSQEntries(ThreadID tid);
/** Returns the number of valid instructions coming from decode. */
unsigned validInsts();
/** Reads signals telling rename to block/unblock. */
void readStallSignals(unsigned tid);
void readStallSignals(ThreadID tid);
/** Checks if any stages are telling rename to block. */
bool checkStall(unsigned tid);
bool checkStall(ThreadID tid);
/** Gets the number of free entries for a specific thread. */
void readFreeEntries(unsigned tid);
void readFreeEntries(ThreadID tid);
/** Checks the signals and updates the status. */
bool checkSignalsAndUpdate(unsigned tid);
bool checkSignalsAndUpdate(ThreadID tid);
/** Either serializes on the next instruction available in the InstQueue,
* or records that it must serialize on the next instruction to enter
@ -263,7 +263,7 @@ class DefaultRename
* thread that has the serializeAfter instruction.
* @param tid The thread id.
*/
void serializeAfter(InstQueue &inst_list, unsigned tid);
void serializeAfter(InstQueue &inst_list, ThreadID tid);
/** Holds the information for each destination register rename. It holds
* the instruction's sequence number, the arch register, the old physical
@ -332,7 +332,7 @@ class DefaultRename
FreeList *freeList;
/** Pointer to the list of active threads. */
std::list<unsigned> *activeThreads;
std::list<ThreadID> *activeThreads;
/** Pointer to the scoreboard. */
Scoreboard *scoreboard;
@ -418,7 +418,7 @@ class DefaultRename
bool resumeUnblocking;
/** The number of threads active in rename. */
unsigned numThreads;
ThreadID numThreads;
/** The maximum skid buffer size. */
unsigned skidBufferMax;

136
src/cpu/o3/rename_impl.hh
View file

@ -37,6 +37,8 @@
#include "cpu/o3/rename.hh"
#include "params/DerivO3CPU.hh"
using namespace std;
template <class Impl>
DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
: cpu(_cpu),
@ -52,22 +54,22 @@ DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
{
_status = Inactive;
for (int i=0; i< numThreads; i++) {
renameStatus[i] = Idle;
for (ThreadID tid = 0; tid < numThreads; tid++) {
renameStatus[tid] = Idle;
freeEntries[i].iqEntries = 0;
freeEntries[i].lsqEntries = 0;
freeEntries[i].robEntries = 0;
freeEntries[tid].iqEntries = 0;
freeEntries[tid].lsqEntries = 0;
freeEntries[tid].robEntries = 0;
stalls[i].iew = false;
stalls[i].commit = false;
serializeInst[i] = NULL;
stalls[tid].iew = false;
stalls[tid].commit = false;
serializeInst[tid] = NULL;
instsInProgress[i] = 0;
instsInProgress[tid] = 0;
emptyROB[i] = true;
emptyROB[tid] = true;
serializeOnNextInst[i] = false;
serializeOnNextInst[tid] = false;
}
// @todo: Make into a parameter.
@ -207,7 +209,7 @@ void
DefaultRename<Impl>::initStage()
{
// Grab the number of free entries directly from the stages.
for (int tid=0; tid < numThreads; tid++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
freeEntries[tid].iqEntries = iew_ptr->instQueue.numFreeEntries(tid);
freeEntries[tid].lsqEntries = iew_ptr->ldstQueue.numFreeEntries(tid);
freeEntries[tid].robEntries = commit_ptr->numROBFreeEntries(tid);
@ -217,7 +219,7 @@ DefaultRename<Impl>::initStage()
template<class Impl>
void
DefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
DefaultRename<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
{
activeThreads = at_ptr;
}
@ -227,9 +229,8 @@ template <class Impl>
void
DefaultRename<Impl>::setRenameMap(RenameMap rm_ptr[])
{
for (int i=0; i<numThreads; i++) {
renameMap[i] = &rm_ptr[i];
}
for (ThreadID tid = 0; tid < numThreads; tid++)
renameMap[tid] = &rm_ptr[tid];
}
template <class Impl>
@ -260,19 +261,19 @@ void
DefaultRename<Impl>::switchOut()
{
// Clear any state, fix up the rename map.
for (int i = 0; i < numThreads; i++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
typename std::list<RenameHistory>::iterator hb_it =
historyBuffer[i].begin();
historyBuffer[tid].begin();
while (!historyBuffer[i].empty()) {
assert(hb_it != historyBuffer[i].end());
while (!historyBuffer[tid].empty()) {
assert(hb_it != historyBuffer[tid].end());
DPRINTF(Rename, "[tid:%u]: Removing history entry with sequence "
"number %i.\n", i, (*hb_it).instSeqNum);
"number %i.\n", tid, (*hb_it).instSeqNum);
// Tell the rename map to set the architected register to the
// previous physical register that it was renamed to.
renameMap[i]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
renameMap[tid]->setEntry(hb_it->archReg, hb_it->prevPhysReg);
// Put the renamed physical register back on the free list.
freeList->addReg(hb_it->newPhysReg);
@ -282,10 +283,10 @@ DefaultRename<Impl>::switchOut()
scoreboard->setReg(hb_it->newPhysReg);
}
historyBuffer[i].erase(hb_it++);
historyBuffer[tid].erase(hb_it++);
}
insts[i].clear();
skidBuffer[i].clear();
insts[tid].clear();
skidBuffer[tid].clear();
}
}
@ -297,24 +298,24 @@ DefaultRename<Impl>::takeOverFrom()
initStage();
// Reset all state prior to taking over from the other CPU.
for (int i=0; i< numThreads; i++) {
renameStatus[i] = Idle;
for (ThreadID tid = 0; tid < numThreads; tid++) {
renameStatus[tid] = Idle;
stalls[i].iew = false;
stalls[i].commit = false;
serializeInst[i] = NULL;
stalls[tid].iew = false;
stalls[tid].commit = false;
serializeInst[tid] = NULL;
instsInProgress[i] = 0;
instsInProgress[tid] = 0;
emptyROB[i] = true;
emptyROB[tid] = true;
serializeOnNextInst[i] = false;
serializeOnNextInst[tid] = false;
}
}
template <class Impl>
void
DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, unsigned tid)
DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
{
DPRINTF(Rename, "[tid:%u]: Squashing instructions.\n",tid);
@ -380,12 +381,12 @@ DefaultRename<Impl>::tick()
sortInsts();
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
// Check stall and squash signals.
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
DPRINTF(Rename, "Processing [tid:%i]\n", tid);
@ -406,7 +407,7 @@ DefaultRename<Impl>::tick()
threads = activeThreads->begin();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
// If we committed this cycle then doneSeqNum will be > 0
if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
@ -419,7 +420,7 @@ DefaultRename<Impl>::tick()
}
// @todo: make into updateProgress function
for (int tid=0; tid < numThreads; tid++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
instsInProgress[tid] -= fromIEW->iewInfo[tid].dispatched;
assert(instsInProgress[tid] >=0);
@ -429,7 +430,7 @@ DefaultRename<Impl>::tick()
template<class Impl>
void
DefaultRename<Impl>::rename(bool &status_change, unsigned tid)
DefaultRename<Impl>::rename(bool &status_change, ThreadID tid)
{
// If status is Running or idle,
// call renameInsts()
@ -483,7 +484,7 @@ DefaultRename<Impl>::rename(bool &status_change, unsigned tid)
template <class Impl>
void
DefaultRename<Impl>::renameInsts(unsigned tid)
DefaultRename<Impl>::renameInsts(ThreadID tid)
{
// Instructions can be either in the skid buffer or the queue of
// instructions coming from decode, depending on the status.
@ -703,7 +704,7 @@ DefaultRename<Impl>::renameInsts(unsigned tid)
template<class Impl>
void
DefaultRename<Impl>::skidInsert(unsigned tid)
DefaultRename<Impl>::skidInsert(ThreadID tid)
{
DynInstPtr inst = NULL;
@ -742,8 +743,8 @@ DefaultRename<Impl>::sortInsts()
{
int insts_from_decode = fromDecode->size;
#ifdef DEBUG
for (int i=0; i < numThreads; i++)
assert(insts[i].empty());
for (ThreadID tid = 0; tid < numThreads; tid++)
assert(insts[tid].empty());
#endif
for (int i = 0; i < insts_from_decode; ++i) {
DynInstPtr inst = fromDecode->insts[i];
@ -755,11 +756,11 @@ template<class Impl>
bool
DefaultRename<Impl>::skidsEmpty()
{
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (!skidBuffer[tid].empty())
return false;
@ -774,11 +775,11 @@ DefaultRename<Impl>::updateStatus()
{
bool any_unblocking = false;
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (renameStatus[tid] == Unblocking) {
any_unblocking = true;
@ -809,7 +810,7 @@ DefaultRename<Impl>::updateStatus()
template <class Impl>
bool
DefaultRename<Impl>::block(unsigned tid)
DefaultRename<Impl>::block(ThreadID tid)
{
DPRINTF(Rename, "[tid:%u]: Blocking.\n", tid);
@ -843,7 +844,7 @@ DefaultRename<Impl>::block(unsigned tid)
template <class Impl>
bool
DefaultRename<Impl>::unblock(unsigned tid)
DefaultRename<Impl>::unblock(ThreadID tid)
{
DPRINTF(Rename, "[tid:%u]: Trying to unblock.\n", tid);
@ -864,7 +865,7 @@ DefaultRename<Impl>::unblock(unsigned tid)
template <class Impl>
void
DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid)
DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid)
{
typename std::list<RenameHistory>::iterator hb_it =
historyBuffer[tid].begin();
@ -904,7 +905,7 @@ DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid)
template<class Impl>
void
DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid)
DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, ThreadID tid)
{
DPRINTF(Rename, "[tid:%u]: Removing a committed instruction from the "
"history buffer %u (size=%i), until [sn:%lli].\n",
@ -945,7 +946,7 @@ DefaultRename<Impl>::removeFromHistory(InstSeqNum inst_seq_num, unsigned tid)
template <class Impl>
inline void
DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid)
DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
{
assert(renameMap[tid] != 0);
@ -996,7 +997,7 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid)
template <class Impl>
inline void
DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
{
typename RenameMap::RenameInfo rename_result;
@ -1057,7 +1058,7 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
template <class Impl>
inline int
DefaultRename<Impl>::calcFreeROBEntries(unsigned tid)
DefaultRename<Impl>::calcFreeROBEntries(ThreadID tid)
{
int num_free = freeEntries[tid].robEntries -
(instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
@ -1069,7 +1070,7 @@ DefaultRename<Impl>::calcFreeROBEntries(unsigned tid)
template <class Impl>
inline int
DefaultRename<Impl>::calcFreeIQEntries(unsigned tid)
DefaultRename<Impl>::calcFreeIQEntries(ThreadID tid)
{
int num_free = freeEntries[tid].iqEntries -
(instsInProgress[tid] - fromIEW->iewInfo[tid].dispatched);
@ -1081,7 +1082,7 @@ DefaultRename<Impl>::calcFreeIQEntries(unsigned tid)
template <class Impl>
inline int
DefaultRename<Impl>::calcFreeLSQEntries(unsigned tid)
DefaultRename<Impl>::calcFreeLSQEntries(ThreadID tid)
{
int num_free = freeEntries[tid].lsqEntries -
(instsInProgress[tid] - fromIEW->iewInfo[tid].dispatchedToLSQ);
@ -1107,7 +1108,7 @@ DefaultRename<Impl>::validInsts()
template <class Impl>
void
DefaultRename<Impl>::readStallSignals(unsigned tid)
DefaultRename<Impl>::readStallSignals(ThreadID tid)
{
if (fromIEW->iewBlock[tid]) {
stalls[tid].iew = true;
@ -1130,7 +1131,7 @@ DefaultRename<Impl>::readStallSignals(unsigned tid)
template <class Impl>
bool
DefaultRename<Impl>::checkStall(unsigned tid)
DefaultRename<Impl>::checkStall(ThreadID tid)
{
bool ret_val = false;
@ -1165,7 +1166,7 @@ DefaultRename<Impl>::checkStall(unsigned tid)
template <class Impl>
void
DefaultRename<Impl>::readFreeEntries(unsigned tid)
DefaultRename<Impl>::readFreeEntries(ThreadID tid)
{
bool updated = false;
if (fromIEW->iewInfo[tid].usedIQ) {
@ -1199,7 +1200,7 @@ DefaultRename<Impl>::readFreeEntries(unsigned tid)
template <class Impl>
bool
DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
{
// Check if there's a squash signal, squash if there is
// Check stall signals, block if necessary.
@ -1308,8 +1309,7 @@ DefaultRename<Impl>::checkSignalsAndUpdate(unsigned tid)
template<class Impl>
void
DefaultRename<Impl>::serializeAfter(InstQueue &inst_list,
unsigned tid)
DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)
{
if (inst_list.empty()) {
// Mark a bit to say that I must serialize on the next instruction.
@ -1347,11 +1347,11 @@ DefaultRename<Impl>::dumpHistory()
{
typename std::list<RenameHistory>::iterator buf_it;
for (int i = 0; i < numThreads; i++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
buf_it = historyBuffer[i].begin();
buf_it = historyBuffer[tid].begin();
while (buf_it != historyBuffer[i].end()) {
while (buf_it != historyBuffer[tid].end()) {
cprintf("Seq num: %i\nArch reg: %i New phys reg: %i Old phys "
"reg: %i\n", (*buf_it).instSeqNum, (int)(*buf_it).archReg,
(int)(*buf_it).newPhysReg, (int)(*buf_it).prevPhysReg);

46
src/cpu/o3/rob.hh
View file

@ -84,14 +84,14 @@ class ROB
*/
ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth,
std::string smtROBPolicy, unsigned _smtROBThreshold,
unsigned _numThreads);
ThreadID _numThreads);
std::string name() const;
/** Sets pointer to the list of active threads.
* @param at_ptr Pointer to the list of active threads.
*/
void setActiveThreads(std::list<unsigned>* at_ptr);
void setActiveThreads(std::list<ThreadID> *at_ptr);
/** Switches out the ROB. */
void switchOut();
@ -116,7 +116,7 @@ class ROB
* the ROB.
* @return Pointer to the DynInst that is at the head of the ROB.
*/
DynInstPtr readHeadInst(unsigned tid);
DynInstPtr readHeadInst(ThreadID tid);
/** Returns pointer to the tail instruction within the ROB. There is
* no guarantee as to the return value if the ROB is empty.
@ -128,7 +128,7 @@ class ROB
* the ROB.
* @return Pointer to the DynInst that is at the tail of the ROB.
*/
DynInstPtr readTailInst(unsigned tid);
DynInstPtr readTailInst(ThreadID tid);
/** Retires the head instruction, removing it from the ROB. */
// void retireHead();
@ -136,13 +136,13 @@ class ROB
/** Retires the head instruction of a specific thread, removing it from the
* ROB.
*/
void retireHead(unsigned tid);
void retireHead(ThreadID tid);
/** Is the oldest instruction across all threads ready. */
// bool isHeadReady();
/** Is the oldest instruction across a particular thread ready. */
bool isHeadReady(unsigned tid);
bool isHeadReady(ThreadID tid);
/** Is there any commitable head instruction across all threads ready. */
bool canCommit();
@ -151,20 +151,20 @@ class ROB
void resetEntries();
/** Number of entries needed For 'num_threads' amount of threads. */
int entryAmount(int num_threads);
int entryAmount(ThreadID num_threads);
/** Returns the number of total free entries in the ROB. */
unsigned numFreeEntries();
/** Returns the number of free entries in a specific ROB paritition. */
unsigned numFreeEntries(unsigned tid);
unsigned numFreeEntries(ThreadID tid);
/** Returns the maximum number of entries for a specific thread. */
unsigned getMaxEntries(unsigned tid)
unsigned getMaxEntries(ThreadID tid)
{ return maxEntries[tid]; }
/** Returns the number of entries being used by a specific thread. */
unsigned getThreadEntries(unsigned tid)
unsigned getThreadEntries(ThreadID tid)
{ return threadEntries[tid]; }
/** Returns if the ROB is full. */
@ -172,7 +172,7 @@ class ROB
{ return numInstsInROB == numEntries; }
/** Returns if a specific thread's partition is full. */
bool isFull(unsigned tid)
bool isFull(ThreadID tid)
{ return threadEntries[tid] == numEntries; }
/** Returns if the ROB is empty. */
@ -180,16 +180,16 @@ class ROB
{ return numInstsInROB == 0; }
/** Returns if a specific thread's partition is empty. */
bool isEmpty(unsigned tid)
bool isEmpty(ThreadID tid)
{ return threadEntries[tid] == 0; }
/** Executes the squash, marking squashed instructions. */
void doSquash(unsigned tid);
void doSquash(ThreadID tid);
/** Squashes all instructions younger than the given sequence number for
* the specific thread.
*/
void squash(InstSeqNum squash_num, unsigned tid);
void squash(InstSeqNum squash_num, ThreadID tid);
/** Updates the head instruction with the new oldest instruction. */
void updateHead();
@ -201,37 +201,37 @@ class ROB
// uint64_t readHeadPC();
/** Reads the PC of the head instruction of a specific thread. */
// uint64_t readHeadPC(unsigned tid);
// uint64_t readHeadPC(ThreadID tid);
/** Reads the next PC of the oldest head instruction. */
// uint64_t readHeadNextPC();
/** Reads the next PC of the head instruction of a specific thread. */
// uint64_t readHeadNextPC(unsigned tid);
// uint64_t readHeadNextPC(ThreadID tid);
/** Reads the sequence number of the oldest head instruction. */
// InstSeqNum readHeadSeqNum();
/** Reads the sequence number of the head instruction of a specific thread.
*/
// InstSeqNum readHeadSeqNum(unsigned tid);
// InstSeqNum readHeadSeqNum(ThreadID tid);
/** Reads the PC of the youngest tail instruction. */
// uint64_t readTailPC();
/** Reads the PC of the tail instruction of a specific thread. */
// uint64_t readTailPC(unsigned tid);
// uint64_t readTailPC(ThreadID tid);
/** Reads the sequence number of the youngest tail instruction. */
// InstSeqNum readTailSeqNum();
/** Reads the sequence number of tail instruction of a specific thread. */
// InstSeqNum readTailSeqNum(unsigned tid);
// InstSeqNum readTailSeqNum(ThreadID tid);
/** Checks if the ROB is still in the process of squashing instructions.
* @retval Whether or not the ROB is done squashing.
*/
bool isDoneSquashing(unsigned tid) const
bool isDoneSquashing(ThreadID tid) const
{ return doneSquashing[tid]; }
/** Checks if the ROB is still in the process of squashing instructions for
@ -249,14 +249,14 @@ class ROB
* threadEntries to get the instructions in the ROB unless you are
* double checking that variable.
*/
int countInsts(unsigned tid);
int countInsts(ThreadID tid);
private:
/** Pointer to the CPU. */
O3CPU *cpu;
/** Active Threads in CPU */
std::list<unsigned>* activeThreads;
std::list<ThreadID> *activeThreads;
/** Number of instructions in the ROB. */
unsigned numEntries;
@ -309,7 +309,7 @@ class ROB
bool doneSquashing[Impl::MaxThreads];
/** Number of active threads. */
unsigned numThreads;
ThreadID numThreads;
};
#endif //__CPU_O3_ROB_HH__

92
src/cpu/o3/rob_impl.hh
View file

@ -29,22 +29,24 @@
* Korey Sewell
*/
#include <list>
#include "config/full_system.hh"
#include "cpu/o3/rob.hh"
#include <list>
using namespace std;
template <class Impl>
ROB<Impl>::ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth,
std::string _smtROBPolicy, unsigned _smtROBThreshold,
unsigned _numThreads)
ThreadID _numThreads)
: cpu(_cpu),
numEntries(_numEntries),
squashWidth(_squashWidth),
numInstsInROB(0),
numThreads(_numThreads)
{
for (int tid=0; tid < numThreads; tid++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
squashedSeqNum[tid] = 0;
doneSquashing[tid] = true;
threadEntries[tid] = 0;
@ -61,8 +63,8 @@ ROB<Impl>::ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth,
robPolicy = Dynamic;
//Set Max Entries to Total ROB Capacity
for (int i = 0; i < numThreads; i++) {
maxEntries[i]=numEntries;
for (ThreadID tid = 0; tid < numThreads; tid++) {
maxEntries[tid] = numEntries;
}
} else if (policy == "partitioned") {
@ -73,8 +75,8 @@ ROB<Impl>::ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth,
int part_amt = numEntries / numThreads;
//Divide ROB up evenly
for (int i = 0; i < numThreads; i++) {
maxEntries[i]=part_amt;
for (ThreadID tid = 0; tid < numThreads; tid++) {
maxEntries[tid] = part_amt;
}
} else if (policy == "threshold") {
@ -84,8 +86,8 @@ ROB<Impl>::ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth,
int threshold = _smtROBThreshold;;
//Divide up by threshold amount
for (int i = 0; i < numThreads; i++) {
maxEntries[i]=threshold;
for (ThreadID tid = 0; tid < numThreads; tid++) {
maxEntries[tid] = threshold;
}
} else {
assert(0 && "Invalid ROB Sharing Policy.Options Are:{Dynamic,"
@ -93,8 +95,8 @@ ROB<Impl>::ROB(O3CPU *_cpu, unsigned _numEntries, unsigned _squashWidth,
}
// Set the per-thread iterators to the end of the instruction list.
for (int i=0; i < numThreads;i++) {
squashIt[i] = instList[i].end();
for (ThreadID tid = 0; tid < numThreads; tid++) {
squashIt[tid] = instList[tid].end();
}
// Initialize the "universal" ROB head & tail point to invalid
@ -112,7 +114,7 @@ ROB<Impl>::name() const
template <class Impl>
void
ROB<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
ROB<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
{
DPRINTF(ROB, "Setting active threads list pointer.\n");
activeThreads = at_ptr;
@ -122,7 +124,7 @@ template <class Impl>
void
ROB<Impl>::switchOut()
{
for (int tid = 0; tid < numThreads; tid++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
instList[tid].clear();
}
}
@ -131,7 +133,7 @@ template <class Impl>
void
ROB<Impl>::takeOverFrom()
{
for (int tid=0; tid < numThreads; tid++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
doneSquashing[tid] = true;
threadEntries[tid] = 0;
squashIt[tid] = instList[tid].end();
@ -151,11 +153,11 @@ ROB<Impl>::resetEntries()
if (robPolicy != Dynamic || numThreads > 1) {
int active_threads = activeThreads->size();
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (robPolicy == Partitioned) {
maxEntries[tid] = numEntries / active_threads;
@ -168,7 +170,7 @@ ROB<Impl>::resetEntries()
template <class Impl>
int
ROB<Impl>::entryAmount(int num_threads)
ROB<Impl>::entryAmount(ThreadID num_threads)
{
if (robPolicy == Partitioned) {
return numEntries / num_threads;
@ -181,17 +183,17 @@ template <class Impl>
int
ROB<Impl>::countInsts()
{
int total=0;
int total = 0;
for (int i=0;i < numThreads;i++)
total += countInsts(i);
for (ThreadID tid = 0; tid < numThreads; tid++)
total += countInsts(tid);
return total;
}
template <class Impl>
int
ROB<Impl>::countInsts(unsigned tid)
ROB<Impl>::countInsts(ThreadID tid)
{
return instList[tid].size();
}
@ -207,7 +209,7 @@ ROB<Impl>::insertInst(DynInstPtr &inst)
assert(numInstsInROB != numEntries);
int tid = inst->threadNumber;
ThreadID tid = inst->threadNumber;
instList[tid].push_back(inst);
@ -242,7 +244,7 @@ ROB<Impl>::retireHead()
//assert(numInstsInROB == countInsts());
assert(numInstsInROB > 0);
int tid = (*head)->threadNumber;
ThreadID tid = (*head)->threadNumber;
retireHead(tid);
@ -254,7 +256,7 @@ ROB<Impl>::retireHead()
template <class Impl>
void
ROB<Impl>::retireHead(unsigned tid)
ROB<Impl>::retireHead(ThreadID tid)
{
//assert(numInstsInROB == countInsts());
assert(numInstsInROB > 0);
@ -300,7 +302,7 @@ ROB<Impl>::isHeadReady()
*/
template <class Impl>
bool
ROB<Impl>::isHeadReady(unsigned tid)
ROB<Impl>::isHeadReady(ThreadID tid)
{
if (threadEntries[tid] != 0) {
return instList[tid].front()->readyToCommit();
@ -314,11 +316,11 @@ bool
ROB<Impl>::canCommit()
{
//@todo: set ActiveThreads through ROB or CPU
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (isHeadReady(tid)) {
return true;
@ -339,14 +341,14 @@ ROB<Impl>::numFreeEntries()
template <class Impl>
unsigned
ROB<Impl>::numFreeEntries(unsigned tid)
ROB<Impl>::numFreeEntries(ThreadID tid)
{
return maxEntries[tid] - threadEntries[tid];
}
template <class Impl>
void
ROB<Impl>::doSquash(unsigned tid)
ROB<Impl>::doSquash(ThreadID tid)
{
DPRINTF(ROB, "[tid:%u]: Squashing instructions until [sn:%i].\n",
tid, squashedSeqNum[tid]);
@ -429,11 +431,11 @@ ROB<Impl>::updateHead()
bool first_valid = true;
// @todo: set ActiveThreads through ROB or CPU
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (instList[tid].empty())
continue;
@ -470,11 +472,11 @@ ROB<Impl>::updateTail()
tail = instList[0].end();
bool first_valid = true;
std::list<unsigned>::iterator threads = activeThreads->begin();
std::list<unsigned>::iterator end = activeThreads->end();
list<ThreadID>::iterator threads = activeThreads->begin();
list<ThreadID>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (instList[tid].empty()) {
continue;
@ -503,7 +505,7 @@ ROB<Impl>::updateTail()
template <class Impl>
void
ROB<Impl>::squash(InstSeqNum squash_num,unsigned tid)
ROB<Impl>::squash(InstSeqNum squash_num, ThreadID tid)
{
if (isEmpty()) {
DPRINTF(ROB, "Does not need to squash due to being empty "
@ -546,7 +548,7 @@ ROB<Impl>::readHeadInst()
template <class Impl>
typename Impl::DynInstPtr
ROB<Impl>::readHeadInst(unsigned tid)
ROB<Impl>::readHeadInst(ThreadID tid)
{
if (threadEntries[tid] != 0) {
InstIt head_thread = instList[tid].begin();
@ -573,7 +575,7 @@ ROB<Impl>::readHeadPC()
template <class Impl>
uint64_t
ROB<Impl>::readHeadPC(unsigned tid)
ROB<Impl>::readHeadPC(ThreadID tid)
{
//assert(numInstsInROB == countInsts());
InstIt head_thread = instList[tid].begin();
@ -595,7 +597,7 @@ ROB<Impl>::readHeadNextPC()
template <class Impl>
uint64_t
ROB<Impl>::readHeadNextPC(unsigned tid)
ROB<Impl>::readHeadNextPC(ThreadID tid)
{
//assert(numInstsInROB == countInsts());
InstIt head_thread = instList[tid].begin();
@ -615,7 +617,7 @@ ROB<Impl>::readHeadSeqNum()
template <class Impl>
InstSeqNum
ROB<Impl>::readHeadSeqNum(unsigned tid)
ROB<Impl>::readHeadSeqNum(ThreadID tid)
{
InstIt head_thread = instList[tid].begin();
@ -634,7 +636,7 @@ ROB<Impl>::readTailInst()
*/
template <class Impl>
typename Impl::DynInstPtr
ROB<Impl>::readTailInst(unsigned tid)
ROB<Impl>::readTailInst(ThreadID tid)
{
//assert(tail_thread[tid] != instList[tid].end());
@ -658,7 +660,7 @@ ROB<Impl>::readTailPC()
template <class Impl>
uint64_t
ROB<Impl>::readTailPC(unsigned tid)
ROB<Impl>::readTailPC(ThreadID tid)
{
//assert(tail_thread[tid] != instList[tid].end());
@ -680,7 +682,7 @@ ROB<Impl>::readTailSeqNum()
template <class Impl>
InstSeqNum
ROB<Impl>::readTailSeqNum(unsigned tid)
ROB<Impl>::readTailSeqNum(ThreadID tid)
{
// Return the last sequence number that has not been squashed. Other
// stages can use it to squash any instructions younger than the current

5
src/cpu/o3/store_set.cc
View file

@ -186,8 +186,7 @@ StoreSet::insertLoad(Addr load_PC, InstSeqNum load_seq_num)
}
void
StoreSet::insertStore(Addr store_PC, InstSeqNum store_seq_num,
unsigned tid)
StoreSet::insertStore(Addr store_PC, InstSeqNum store_seq_num, ThreadID tid)
{
int index = calcIndex(store_PC);
@ -288,7 +287,7 @@ StoreSet::issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store)
}
void
StoreSet::squash(InstSeqNum squashed_num, unsigned tid)
StoreSet::squash(InstSeqNum squashed_num, ThreadID tid)
{
DPRINTF(StoreSet, "StoreSet: Squashing until inum %i\n",
squashed_num);

5
src/cpu/o3/store_set.hh
View file

@ -82,8 +82,7 @@ class StoreSet
/** Inserts a store into the store set predictor. Updates the
* LFST if the store has a valid SSID. */
void insertStore(Addr store_PC, InstSeqNum store_seq_num,
unsigned tid);
void insertStore(Addr store_PC, InstSeqNum store_seq_num, ThreadID tid);
/** Checks if the instruction with the given PC is dependent upon
* any store. @return Returns the sequence number of the store
@ -95,7 +94,7 @@ class StoreSet
void issued(Addr issued_PC, InstSeqNum issued_seq_num, bool is_store);
/** Squashes for a specific thread until the given sequence number. */
void squash(InstSeqNum squashed_num, unsigned tid);
void squash(InstSeqNum squashed_num, ThreadID tid);
/** Resets all tables. */
void clear();

2
src/cpu/o3/thread_context_impl.hh
View file

@ -226,7 +226,7 @@ O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
{
// This function will mess things up unless the ROB is empty and
// there are no instructions in the pipeline.
unsigned tid = thread->threadId();
ThreadID tid = thread->threadId();
PhysRegIndex renamed_reg;
// First loop through the integer registers.

88
src/cpu/ozone/back_end_impl.hh
View file

@ -649,28 +649,28 @@ BackEnd<Impl>::regStats()
{
using namespace Stats;
rob_cap_events
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ROB:cap_events")
.desc("number of cycles where ROB cap was active")
.flags(total)
;
rob_cap_inst_count
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ROB:cap_inst")
.desc("number of instructions held up by ROB cap")
.flags(total)
;
iq_cap_events
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() +".IQ:cap_events" )
.desc("number of cycles where IQ cap was active")
.flags(total)
;
iq_cap_inst_count
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".IQ:cap_inst")
.desc("number of instructions held up by IQ cap")
.flags(total)
@ -678,49 +678,49 @@ BackEnd<Impl>::regStats()
exe_inst
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ISSUE:count")
.desc("number of insts issued")
.flags(total)
;
exe_swp
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ISSUE:swp")
.desc("number of swp insts issued")
.flags(total)
;
exe_nop
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ISSUE:nop")
.desc("number of nop insts issued")
.flags(total)
;
exe_refs
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ISSUE:refs")
.desc("number of memory reference insts issued")
.flags(total)
;
exe_loads
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ISSUE:loads")
.desc("number of load insts issued")
.flags(total)
;
exe_branches
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ISSUE:branches")
.desc("Number of branches issued")
.flags(total)
;
issued_ops
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ISSUE:op_count")
.desc("number of insts issued")
.flags(total)
@ -737,28 +737,28 @@ BackEnd<Impl>::regStats()
// Other stats
//
lsq_forw_loads
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".LSQ:forw_loads")
.desc("number of loads forwarded via LSQ")
.flags(total)
;
inv_addr_loads
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ISSUE:addr_loads")
.desc("number of invalid-address loads")
.flags(total)
;
inv_addr_swpfs
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ISSUE:addr_swpfs")
.desc("number of invalid-address SW prefetches")
.flags(total)
;
lsq_blocked_loads
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".LSQ:blocked_loads")
.desc("number of ready loads not issued due to memory disambiguation")
.flags(total)
@ -793,28 +793,28 @@ BackEnd<Impl>::regStats()
}
writeback_count
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".WB:count")
.desc("cumulative count of insts written-back")
.flags(total)
;
producer_inst
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".WB:producers")
.desc("num instructions producing a value")
.flags(total)
;
consumer_inst
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".WB:consumers")
.desc("num instructions consuming a value")
.flags(total)
;
wb_penalized
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".WB:penalized")
.desc("number of instrctions required to write to 'other' IQ")
.flags(total)
@ -845,42 +845,42 @@ BackEnd<Impl>::regStats()
wb_rate = writeback_count / cpu->numCycles;
stat_com_inst
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:count")
.desc("Number of instructions committed")
.flags(total)
;
stat_com_swp
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:swp_count")
.desc("Number of s/w prefetches committed")
.flags(total)
;
stat_com_refs
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:refs")
.desc("Number of memory references committed")
.flags(total)
;
stat_com_loads
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:loads")
.desc("Number of loads committed")
.flags(total)
;
stat_com_membars
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:membars")
.desc("Number of memory barriers committed")
.flags(total)
;
stat_com_branches
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:branches")
.desc("Number of branches committed")
.flags(total)
@ -906,7 +906,7 @@ BackEnd<Impl>::regStats()
// we reached the BW limit
//
commit_eligible
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:bw_limited")
.desc("number of insts not committed due to BW limits")
.flags(total)
@ -923,7 +923,7 @@ BackEnd<Impl>::regStats()
;
ROB_count
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ROB:occupancy")
.desc(name() + ".ROB occupancy (cumulative)")
.flags(total)
@ -943,7 +943,7 @@ BackEnd<Impl>::regStats()
ROB_occ_rate = ROB_count / cpu->numCycles;
ROB_occ_dist
.init(cpu->number_of_threads,0,numROBEntries,2)
.init(cpu->numThreads, 0, numROBEntries, 2)
.name(name() + ".ROB:occ_dist")
.desc("ROB Occupancy per cycle")
.flags(total | cdf)
@ -1292,7 +1292,7 @@ BackEnd<Impl>::executeInsts()
// This probably needs to prioritize the redirects if a different
// scheduler is used. Currently the scheduler schedules the oldest
// instruction first, so the branch resolution order will be correct.
unsigned tid = inst->threadNumber;
ThreadID tid = inst->threadNumber;
if (!fetchRedirect[tid]) {
@ -1735,34 +1735,34 @@ template <class Impl>
void
BackEnd<Impl>::updateExeInstStats(DynInstPtr &inst)
{
int thread_number = inst->threadNumber;
ThreadID tid = inst->threadNumber;
//
// Pick off the software prefetches
//
#ifdef TARGET_ALPHA
if (inst->isDataPrefetch())
exe_swp[thread_number]++;
exe_swp[tid]++;
else
exe_inst[thread_number]++;
exe_inst[tid]++;
#else
exe_inst[thread_number]++;
exe_inst[tid]++;
#endif
//
// Control operations
//
if (inst->isControl())
exe_branches[thread_number]++;
exe_branches[tid]++;
//
// Memory operations
//
if (inst->isMemRef()) {
exe_refs[thread_number]++;
exe_refs[tid]++;
if (inst->isLoad())
exe_loads[thread_number]++;
exe_loads[tid]++;
}
}
@ -1770,40 +1770,40 @@ template <class Impl>
void
BackEnd<Impl>::updateComInstStats(DynInstPtr &inst)
{
unsigned thread = inst->threadNumber;
ThreadID tid = inst->threadNumber;
//
// Pick off the software prefetches
//
#ifdef TARGET_ALPHA
if (inst->isDataPrefetch()) {
stat_com_swp[thread]++;
stat_com_swp[tid]++;
} else {
stat_com_inst[thread]++;
stat_com_inst[tid]++;
}
#else
stat_com_inst[thread]++;
stat_com_inst[tid]++;
#endif
//
// Control Instructions
//
if (inst->isControl())
stat_com_branches[thread]++;
stat_com_branches[tid]++;
//
// Memory references
//
if (inst->isMemRef()) {
stat_com_refs[thread]++;
stat_com_refs[tid]++;
if (inst->isLoad()) {
stat_com_loads[thread]++;
stat_com_loads[tid]++;
}
}
if (inst->isMemBarrier()) {
stat_com_membars[thread]++;
stat_com_membars[tid]++;
}
}

4
src/cpu/ozone/cpu_builder.cc
View file

@ -59,11 +59,11 @@ DerivOzoneCPUParams::create()
#if FULL_SYSTEM
// Full-system only supports a single thread for the moment.
int actual_num_threads = 1;
ThreadID actual_num_threads = 1;
#else
// In non-full-system mode, we infer the number of threads from
// the workload if it's not explicitly specified.
int actual_num_threads =
ThreadID actual_num_threads =
numThreads.isValid() ? numThreads : workload.size();
if (workload.size() == 0) {

14
src/cpu/ozone/inst_queue.hh
View file

@ -130,7 +130,7 @@ class InstQueue
void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
/** Number of entries needed for given amount of threads. */
int entryAmount(int num_threads);
int entryAmount(ThreadID num_threads);
/** Resets max entries for all threads. */
void resetEntries();
@ -139,13 +139,13 @@ class InstQueue
unsigned numFreeEntries();
/** Returns number of free entries for a thread. */
unsigned numFreeEntries(unsigned tid);
unsigned numFreeEntries(ThreadID tid);
/** Returns whether or not the IQ is full. */
bool isFull();
/** Returns whether or not the IQ is full for a specific thread. */
bool isFull(unsigned tid);
bool isFull(ThreadID tid);
/** Returns if there are any ready instructions in the IQ. */
bool hasReadyInsts();
@ -179,7 +179,7 @@ class InstQueue
* Commits all instructions up to and including the given sequence number,
* for a specific thread.
*/
void commit(const InstSeqNum &inst, unsigned tid = 0);
void commit(const InstSeqNum &inst, ThreadID tid = 0);
/** Wakes all dependents of a completed instruction. */
void wakeDependents(DynInstPtr &completed_inst);
@ -206,10 +206,10 @@ class InstQueue
* Squashes instructions for a thread. Squashing information is obtained
* from the time buffer.
*/
void squash(unsigned tid); // Probably want the ISN
void squash(ThreadID tid); // Probably want the ISN
/** Returns the number of used entries for a thread. */
unsigned getCount(unsigned tid) { return count[tid]; };
unsigned getCount(ThreadID tid) { return count[tid]; };
/** Updates the number of free entries. */
void updateFreeEntries(int num) { freeEntries += num; }
@ -219,7 +219,7 @@ class InstQueue
private:
/** Does the actual squashing. */
void doSquash(unsigned tid);
void doSquash(ThreadID tid);
/////////////////////////
// Various pointers

60
src/cpu/ozone/inst_queue_impl.hh
View file

@ -83,8 +83,8 @@ InstQueue<Impl>::InstQueue(Params *params)
numThreads = 1;
//Initialize thread IQ counts
for (int i = 0; i <numThreads; i++) {
count[i] = 0;
for (ThreadID tid = 0; tid <numThreads; tid++) {
count[tid] = 0;
}
// Initialize the number of free IQ entries.
@ -103,9 +103,9 @@ InstQueue<Impl>::InstQueue(Params *params)
// regScoreboard.resize(numPhysRegs);
/*
//Initialize Mem Dependence Units
for (int i = 0; i < numThreads; i++) {
memDepUnit[i].init(params,i);
memDepUnit[i].setIQ(this);
for (ThreadID tid = 0; tid < numThreads; tid++) {
memDepUnit[tid].init(params, tid);
memDepUnit[tid].setIQ(this);
}
// Initialize all the head pointers to point to NULL, and all the
@ -121,8 +121,8 @@ InstQueue<Impl>::InstQueue(Params *params)
regScoreboard[i] = false;
}
*/
for (int i = 0; i < numThreads; ++i) {
squashedSeqNum[i] = 0;
for (ThreadID tid = 0; tid < numThreads; ++tid) {
squashedSeqNum[tid] = 0;
}
/*
for (int i = 0; i < Num_OpClasses; ++i) {
@ -141,8 +141,8 @@ InstQueue<Impl>::InstQueue(Params *params)
iqPolicy = Dynamic;
//Set Max Entries to Total ROB Capacity
for (int i = 0; i < numThreads; i++) {
maxEntries[i] = numEntries;
for (ThreadID tid = 0; tid < numThreads; tid++) {
maxEntries[tid] = numEntries;
}
} else if (policy == "partitioned") {
@ -152,8 +152,8 @@ InstQueue<Impl>::InstQueue(Params *params)
int part_amt = numEntries / numThreads;
//Divide ROB up evenly
for (int i = 0; i < numThreads; i++) {
maxEntries[i] = part_amt;
for (ThreadID tid = 0; tid < numThreads; tid++) {
maxEntries[tid] = part_amt;
}
DPRINTF(Fetch, "IQ sharing policy set to Partitioned:"
@ -167,8 +167,8 @@ InstQueue<Impl>::InstQueue(Params *params)
int thresholdIQ = (int)((double)threshold * numEntries);
//Divide up by threshold amount
for (int i = 0; i < numThreads; i++) {
maxEntries[i] = thresholdIQ;
for (ThreadID tid = 0; tid < numThreads; tid++) {
maxEntries[tid] = thresholdIQ;
}
DPRINTF(Fetch, "IQ sharing policy set to Threshold:"
@ -292,9 +292,9 @@ InstQueue<Impl>::regStats()
.desc("Number of squashed non-spec instructions that were removed")
.prereq(iqSquashedNonSpecRemoved);
/*
for ( int i=0; i < numThreads; i++) {
for (ThreadID tid = 0; tid < numThreads; tid++) {
// Tell mem dependence unit to reg stats as well.
memDepUnit[i].regStats();
memDepUnit[tid].regStats();
}
*/
}
@ -327,7 +327,7 @@ InstQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
template <class Impl>
int
InstQueue<Impl>::entryAmount(int num_threads)
InstQueue<Impl>::entryAmount(ThreadID num_threads)
{
if (iqPolicy == Partitioned) {
return numEntries / num_threads;
@ -348,7 +348,7 @@ InstQueue<Impl>::resetEntries()
std::list<unsigned>::iterator end = activeThreads->end();
while (threads != end) {
unsigned tid = *threads++;
ThreadID tid = *threads++;
if (iqPolicy == Partitioned) {
maxEntries[tid] = numEntries / active_threads;
@ -368,7 +368,7 @@ InstQueue<Impl>::numFreeEntries()
template <class Impl>
unsigned
InstQueue<Impl>::numFreeEntries(unsigned tid)
InstQueue<Impl>::numFreeEntries(ThreadID tid)
{
return maxEntries[tid] - count[tid];
}
@ -388,7 +388,7 @@ InstQueue<Impl>::isFull()
template <class Impl>
bool
InstQueue<Impl>::isFull(unsigned tid)
InstQueue<Impl>::isFull(ThreadID tid)
{
if (numFreeEntries(tid) == 0) {
return(true);
@ -735,7 +735,7 @@ InstQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
assert(inst_it != nonSpecInsts.end());
// unsigned tid = (*inst_it).second->threadNumber;
// ThreadID tid = (*inst_it).second->threadNumber;
// Mark this instruction as ready to issue.
(*inst_it).second->setCanIssue();
@ -752,7 +752,7 @@ InstQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
template <class Impl>
void
InstQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid)
InstQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid)
{
/*Need to go through each thread??*/
DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
@ -879,7 +879,7 @@ template <class Impl>
void
InstQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
{
int tid = completed_inst->threadNumber;
ThreadID tid = completed_inst->threadNumber;
DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n",
completed_inst->readPC(), completed_inst->seqNum);
@ -903,7 +903,7 @@ InstQueue<Impl>::violation(DynInstPtr &store,
*/
template <class Impl>
void
InstQueue<Impl>::squash(unsigned tid)
InstQueue<Impl>::squash(ThreadID tid)
{
DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
"the IQ.\n", tid);
@ -927,7 +927,7 @@ InstQueue<Impl>::squash(unsigned tid)
template <class Impl>
void
InstQueue<Impl>::doSquash(unsigned tid)
InstQueue<Impl>::doSquash(ThreadID tid)
{
// Make sure the squashed sequence number is valid.
assert(squashedSeqNum[tid] != 0);
@ -1200,10 +1200,10 @@ InstQueue<Impl>::countInsts()
#if 0
int total_insts = 0;
for (int i = 0; i < numThreads; ++i) {
ListIt count_it = instList[i].begin();
for (ThreadID tid = 0; tid < numThreads; ++tid) {
ListIt count_it = instList[tid].begin();
while (count_it != instList[i].end()) {
while (count_it != instList[tid].end()) {
if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
if (!(*count_it)->isIssued()) {
++total_insts;
@ -1300,13 +1300,13 @@ template <class Impl>
void
InstQueue<Impl>::dumpInsts()
{
for (int i = 0; i < numThreads; ++i) {
for (ThreadID tid = 0; tid < numThreads; ++tid) {
// int num = 0;
// int valid_num = 0;
/*
ListIt inst_list_it = instList[i].begin();
ListIt inst_list_it = instList[tid].begin();
while (inst_list_it != instList[i].end())
while (inst_list_it != instList[tid].end())
{
cprintf("Instruction:%i\n",
num);

76
src/cpu/ozone/lw_back_end_impl.hh
View file

@ -188,77 +188,77 @@ LWBackEnd<Impl>::regStats()
LSQ.regStats();
robCapEvents
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ROB:cap_events")
.desc("number of cycles where ROB cap was active")
.flags(total)
;
robCapInstCount
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ROB:cap_inst")
.desc("number of instructions held up by ROB cap")
.flags(total)
;
iqCapEvents
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() +".IQ:cap_events" )
.desc("number of cycles where IQ cap was active")
.flags(total)
;
iqCapInstCount
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".IQ:cap_inst")
.desc("number of instructions held up by IQ cap")
.flags(total)
;
exeInst
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ISSUE:count")
.desc("number of insts issued")
.flags(total)
;
exeSwp
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ISSUE:swp")
.desc("number of swp insts issued")
.flags(total)
;
exeNop
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ISSUE:nop")
.desc("number of nop insts issued")
.flags(total)
;
exeRefs
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ISSUE:refs")
.desc("number of memory reference insts issued")
.flags(total)
;
exeLoads
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ISSUE:loads")
.desc("number of load insts issued")
.flags(total)
;
exeBranches
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ISSUE:branches")
.desc("Number of branches issued")
.flags(total)
;
issuedOps
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ISSUE:op_count")
.desc("number of insts issued")
.flags(total)
@ -275,28 +275,28 @@ LWBackEnd<Impl>::regStats()
// Other stats
//
lsqForwLoads
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".LSQ:forw_loads")
.desc("number of loads forwarded via LSQ")
.flags(total)
;
invAddrLoads
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ISSUE:addr_loads")
.desc("number of invalid-address loads")
.flags(total)
;
invAddrSwpfs
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ISSUE:addr_swpfs")
.desc("number of invalid-address SW prefetches")
.flags(total)
;
lsqBlockedLoads
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".LSQ:blocked_loads")
.desc("number of ready loads not issued due to memory disambiguation")
.flags(total)
@ -332,28 +332,28 @@ LWBackEnd<Impl>::regStats()
}
*/
writebackCount
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".WB:count")
.desc("cumulative count of insts written-back")
.flags(total)
;
producerInst
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".WB:producers")
.desc("num instructions producing a value")
.flags(total)
;
consumerInst
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".WB:consumers")
.desc("num instructions consuming a value")
.flags(total)
;
wbPenalized
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".WB:penalized")
.desc("number of instrctions required to write to 'other' IQ")
.flags(total)
@ -384,42 +384,42 @@ LWBackEnd<Impl>::regStats()
wbRate = writebackCount / cpu->numCycles;
statComInst
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:count")
.desc("Number of instructions committed")
.flags(total)
;
statComSwp
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:swp_count")
.desc("Number of s/w prefetches committed")
.flags(total)
;
statComRefs
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:refs")
.desc("Number of memory references committed")
.flags(total)
;
statComLoads
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:loads")
.desc("Number of loads committed")
.flags(total)
;
statComMembars
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:membars")
.desc("Number of memory barriers committed")
.flags(total)
;
statComBranches
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:branches")
.desc("Number of branches committed")
.flags(total)
@ -445,7 +445,7 @@ LWBackEnd<Impl>::regStats()
// we reached the BW limit
//
commitEligible
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:bw_limited")
.desc("number of insts not committed due to BW limits")
.flags(total)
@ -457,13 +457,13 @@ LWBackEnd<Impl>::regStats()
;
squashedInsts
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:squashed_insts")
.desc("Number of instructions removed from inst list")
;
ROBSquashedInsts
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".COM:rob_squashed_insts")
.desc("Number of instructions removed from inst list when they reached the head of the ROB")
;
@ -474,7 +474,7 @@ LWBackEnd<Impl>::regStats()
;
ROBCount
.init(cpu->number_of_threads)
.init(cpu->numThreads)
.name(name() + ".ROB:occupancy")
.desc(name() + ".ROB occupancy (cumulative)")
.flags(total)
@ -494,7 +494,7 @@ LWBackEnd<Impl>::regStats()
ROBOccRate = ROBCount / cpu->numCycles;
/*
ROBOccDist
.init(cpu->number_of_threads,0,numROBEntries,2)
.init(cpu->numThreads, 0, numROBEntries, 2)
.name(name() + ".ROB:occ_dist")
.desc("ROB Occupancy per cycle")
.flags(total | cdf)
@ -1498,34 +1498,34 @@ template <class Impl>
void
LWBackEnd<Impl>::updateExeInstStats(DynInstPtr &inst)
{
int thread_number = inst->threadNumber;
ThreadID tid = inst->threadNumber;
//
// Pick off the software prefetches
//
#ifdef TARGET_ALPHA
if (inst->isDataPrefetch())
exeSwp[thread_number]++;
exeSwp[tid]++;
else
exeInst[thread_number]++;
exeInst[tid]++;
#else
exeInst[thread_number]++;
exeInst[tid]++;
#endif
//
// Control operations
//
if (inst->isControl())
exeBranches[thread_number]++;
exeBranches[tid]++;
//
// Memory operations
//
if (inst->isMemRef()) {
exeRefs[thread_number]++;
exeRefs[tid]++;
if (inst->isLoad())
exeLoads[thread_number]++;
exeLoads[tid]++;
}
}
@ -1533,7 +1533,7 @@ template <class Impl>
void
LWBackEnd<Impl>::updateComInstStats(DynInstPtr &inst)
{
unsigned tid = inst->threadNumber;
ThreadID tid = inst->threadNumber;
// keep an instruction count
thread->numInst++;

8
src/cpu/ozone/null_predictor.hh
View file

@ -68,7 +68,7 @@ class NullPredictor
* @param tid The thread id.
* @return Returns if the branch is taken or not.
*/
bool predict(DynInstPtr &inst, Addr &PC, unsigned tid)
bool predict(DynInstPtr &inst, Addr &PC, ThreadID tid)
{ return false; }
/**
@ -77,7 +77,7 @@ class NullPredictor
* @param done_sn The sequence number to commit any older updates up until.
* @param tid The thread id.
*/
void update(const InstSeqNum &done_sn, unsigned tid) { }
void update(const InstSeqNum &done_sn, ThreadID tid) { }
/**
* Squashes all outstanding updates until a given sequence number.
@ -85,7 +85,7 @@ class NullPredictor
* until.
* @param tid The thread id.
*/
void squash(const InstSeqNum &squashed_sn, unsigned tid) { }
void squash(const InstSeqNum &squashed_sn, ThreadID tid) { }
/**
* Squashes all outstanding updates until a given sequence number, and
@ -97,7 +97,7 @@ class NullPredictor
* @param tid The thread id.
*/
void squash(const InstSeqNum &squashed_sn, const Addr &corr_target,
bool actually_taken, unsigned tid)
bool actually_taken, ThreadID tid)
{ }
};

4
src/cpu/ozone/simple_cpu_builder.cc
View file

@ -62,11 +62,11 @@ SimpleOzoneCPUParams::create()
#if FULL_SYSTEM
// Full-system only supports a single thread for the moment.
int actual_num_threads = 1;
ThreadID actual_num_threads = 1;
#else
// In non-full-system mode, we infer the number of threads from
// the workload if it's not explicitly specified.
int actual_num_threads =
ThreadID actual_num_threads =
numThreads.isValid() ? numThreads : workload.size();
if (workload.size() == 0) {

6
src/cpu/simple/atomic.cc
View file

@ -80,7 +80,8 @@ AtomicSimpleCPU::init()
{
BaseCPU::init();
#if FULL_SYSTEM
for (int i = 0; i < threadContexts.size(); ++i) {
ThreadID size = threadContexts.size();
for (ThreadID i = 0; i < size; ++i) {
ThreadContext *tc = threadContexts[i];
// initialize CPU, including PC
@ -227,7 +228,8 @@ AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
// if any of this CPU's ThreadContexts are active, mark the CPU as
// running and schedule its tick event.
for (int i = 0; i < threadContexts.size(); ++i) {
ThreadID size = threadContexts.size();
for (ThreadID i = 0; i < size; ++i) {
ThreadContext *tc = threadContexts[i];
if (tc->status() == ThreadContext::Active && _status != Running) {
_status = Running;

2
src/cpu/simple/base.cc
View file

@ -200,7 +200,7 @@ BaseSimpleCPU::unserialize(Checkpoint *cp, const string &section)
}
void
change_thread_state(int thread_number, int activate, int priority)
change_thread_state(ThreadID tid, int activate, int priority)
{
}

5
src/cpu/simple/base.hh
View file

@ -399,13 +399,14 @@ class BaseSimpleCPU : public BaseCPU
thread->setStCondFailures(sc_failures);
}
MiscReg readRegOtherThread(int regIdx, int tid = -1)
MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
{
panic("Simple CPU models do not support multithreaded "
"register access.\n");
}
void setRegOtherThread(int regIdx, const MiscReg &val, int tid = -1)
void setRegOtherThread(int regIdx, const MiscReg &val,
ThreadID tid = InvalidThreadID)
{
panic("Simple CPU models do not support multithreaded "
"register access.\n");

8
src/cpu/simple/timing.cc
View file

@ -437,13 +437,13 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
{
Fault fault;
const int asid = 0;
const int thread_id = 0;
const ThreadID tid = 0;
const Addr pc = thread->readPC();
int block_size = dcachePort.peerBlockSize();
int data_size = sizeof(T);
RequestPtr req = new Request(asid, addr, data_size,
flags, pc, _cpuId, thread_id);
flags, pc, _cpuId, tid);
Addr split_addr = roundDown(addr + data_size - 1, block_size);
assert(split_addr <= addr || split_addr - addr < block_size);
@ -555,13 +555,13 @@ Fault
TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
const int asid = 0;
const int thread_id = 0;
const ThreadID tid = 0;
const Addr pc = thread->readPC();
int block_size = dcachePort.peerBlockSize();
int data_size = sizeof(T);
RequestPtr req = new Request(asid, addr, data_size,
flags, pc, _cpuId, thread_id);
flags, pc, _cpuId, tid);
Addr split_addr = roundDown(addr + data_size - 1, block_size);
assert(split_addr <= addr || split_addr - addr < block_size);

12
src/cpu/simple_thread.hh
View file

@ -337,22 +337,26 @@ class SimpleThread : public ThreadState
regs.setNextNPC(val);
}
MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0)
MiscReg
readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
{
return regs.readMiscRegNoEffect(misc_reg);
}
MiscReg readMiscReg(int misc_reg, unsigned tid = 0)
MiscReg
readMiscReg(int misc_reg, ThreadID tid = 0)
{
return regs.readMiscReg(misc_reg, tc);
}
void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0)
void
setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
{
return regs.setMiscRegNoEffect(misc_reg, val);
}
void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0)
void
setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
{
return regs.setMiscReg(misc_reg, val, tc);
}

4
src/cpu/smt.hh
View file

@ -52,10 +52,10 @@ extern int maxThreadsPerCPU;
/**
* Changes the status and priority of the thread with the given number.
* @param thread_number The thread to change.
* @param tid The thread to change.
* @param activate The new active status.
* @param priority The new priority.
*/
void change_thread_state(int thread_number, int activate, int priority);
void change_thread_state(ThreadID tid, int activate, int priority);
#endif // __SMT_HH__

11
src/cpu/thread_context.hh
View file

@ -234,9 +234,16 @@ class ThreadContext
virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid) { return 0; }
virtual uint64_t
readRegOtherThread(int misc_reg, ThreadID tid)
{
return 0;
}
virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { };
virtual void
setRegOtherThread(int misc_reg, const MiscReg &val, ThreadID tid)
{
}
// Also not necessarily the best location for these two. Hopefully will go
// away once we decide upon where st cond failures goes.

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