ruby: cleaned up unified MESI/MOESI configuration
This commit is contained in:
Derek Hower
parent
bd770274b0
commit
6fc2a4cadc
4 changed files with 60 additions and 70 deletions
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@ -26,6 +26,7 @@ num_memories = 1
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memory_size_mb = 1024
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num_dma = 1
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#default protocol
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protocol = "MESI_CMP_directory"
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# check for overrides
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@ -56,7 +57,7 @@ end
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net_ports = Array.new
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iface_ports = Array.new
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#assert(protocol == "MESI_CMP_directory", __FILE__+" cannot be used with protocol "+protocol);
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assert((protocol == "MESI_CMP_directory" or protocol == "MOESI_CMP_directory"), __FILE__+" cannot be used with protocol "+protocol);
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require protocol+".rb"
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@ -71,9 +72,7 @@ num_cores.times { |n|
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icache, dcache,
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sequencer,
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num_l2_banks)
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end
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if protocol == "MESI_CMP_directory"
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elsif protocol == "MESI_CMP_directory"
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net_ports << MESI_CMP_directory_L1CacheController.new("L1CacheController_"+n.to_s,
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"L1Cache",
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icache, dcache,
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@ -87,17 +86,14 @@ num_l2_banks.times { |n|
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net_ports << MOESI_CMP_directory_L2CacheController.new("L2CacheController_"+n.to_s,
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"L2Cache",
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cache)
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net_ports.last.request_latency = l2_cache_latency + 2
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net_ports.last.response_latency = l2_cache_latency + 2
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end
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if protocol == "MESI_CMP_directory"
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elsif protocol == "MESI_CMP_directory"
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net_ports << MESI_CMP_directory_L2CacheController.new("L2CacheController_"+n.to_s,
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"L2Cache",
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cache)
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end
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net_ports.last.request_latency = l2_cache_latency + 2
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net_ports.last.response_latency = l2_cache_latency + 2
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}
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num_memories.times { |n|
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directory = DirectoryMemory.new("DirectoryMemory_"+n.to_s, memory_size_mb/num_memories)
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@ -107,9 +103,7 @@ num_memories.times { |n|
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"Directory",
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directory,
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memory_control)
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end
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if protocol == "MESI_CMP_directory"
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elsif protocol == "MESI_CMP_directory"
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net_ports << MESI_CMP_directory_DirectoryController.new("DirectoryController_"+n.to_s,
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"Directory",
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directory,
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@ -124,9 +118,7 @@ num_dma.times { |n|
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net_ports << MOESI_CMP_directory_DMAController.new("DMAController_"+n.to_s,
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"DMA",
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dma_sequencer)
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end
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if protocol == "MESI_CMP_directory"
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elsif protocol == "MESI_CMP_directory"
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net_ports << MESI_CMP_directory_DMAController.new("DMAController_"+n.to_s,
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"DMA",
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dma_sequencer)
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@ -296,9 +296,6 @@ private
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end
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class CacheController < NetPort
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@@total_cache_controllers = Hash.new
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@ -438,27 +435,27 @@ class SetAssociativeCache < Cache
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cacti_args << 360 << 0 << 0 << 0 << 0 << 1 << 1 << 1 << 1 << 0 << 0
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cacti_args << 50 << 10 << 10 << 0 << 1 << 1
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# cacti_cmd = File.dirname(__FILE__) + "/cacti/cacti " + cacti_args.join(" ")
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cacti_cmd = File.dirname(__FILE__) + "/cacti/cacti " + cacti_args.join(" ")
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# IO.popen(cacti_cmd) { |pipe|
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# str1 = pipe.readline
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# str2 = pipe.readline
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# results = str2.split(", ")
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# if results.size != 61
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# print "CACTI ERROR: CACTI produced unexpected output.\n"
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# print "Are you using the version shipped with libruby?\n"
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# raise Exception
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# end
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# latency_ns = results[5].to_f
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# if (latency_ns == "1e+39")
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# print "CACTI ERROR: CACTI was unable to realistically model the cache ",@obj_name,"\n"
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# print "Either change the cache parameters or manually set the latency values\n"
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# raise Exception
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# end
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# clk_period_ns = 1e9 * (1.0 / (RubySystem.freq_mhz * 1e6))
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# latency_cycles = (latency_ns / clk_period_ns).ceil
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# @latency = latency_cycles
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# }
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IO.popen(cacti_cmd) { |pipe|
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str1 = pipe.readline
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str2 = pipe.readline
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results = str2.split(", ")
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if results.size != 61
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print "CACTI ERROR: CACTI produced unexpected output.\n"
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print "Are you using the version shipped with libruby?\n"
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raise Exception
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end
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latency_ns = results[5].to_f
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if (latency_ns == "1e+39")
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print "CACTI ERROR: CACTI was unable to realistically model the cache ",@obj_name,"\n"
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print "Either change the cache parameters or manually set the latency values\n"
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raise Exception
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end
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clk_period_ns = 1e9 * (1.0 / (RubySystem.freq_mhz * 1e6))
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latency_cycles = (latency_ns / clk_period_ns).ceil
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@latency = latency_cycles
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}
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elsif @latency.is_a?(Float)
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clk_period_ns = 1e9 * (1.0 / (RubySystem.freq_mhz * 1e6))
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latency_cycles = (@latency / clk_period_ns).ceil
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@ -757,5 +754,4 @@ class GarnetFlexiblePipeline < GarnetNetwork
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end
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end
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#added by SS
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require "defaults.rb"
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@ -9,7 +9,7 @@ class NetPort < LibRubyObject
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# buffer_size limits the size of all other buffers connecting to
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# SLICC Controllers. When 0, infinite buffering is used.
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default_param :buffer_size, Integer, 0
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default_param :buffer_size, Integer, 32
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# added by SS for TBE
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default_param :number_of_TBEs, Integer, 256
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@ -36,19 +36,19 @@ class Debug < LibRubyObject
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# 1. change protocol_trace = true
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# 2. enable debug in the Ruby Makefile
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# 3. set start_time = 1
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default_param :protocol_trace, Boolean, true
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default_param :protocol_trace, Boolean, false
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# a string for filtering debugging output (for all g_debug vars see Debug.h)
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default_param :filter_string, String, "none"
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default_param :filter_string, String, ""
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# filters debugging messages based on priority (low, med, high)
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default_param :verbosity_string, String, "none"
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default_param :verbosity_string, String, ""
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# filters debugging messages based on a ruby time
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default_param :start_time, Integer, 1
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# sends debugging messages to a output filename
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default_param :output_filename, String, "debug_ss"
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default_param :output_filename, String, ""
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end
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class Topology < LibRubyObject
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@ -167,6 +167,32 @@ class MOESI_CMP_directory_DMAController < DMAController
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default_param :response_latency, Integer, 14
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end
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class MESI_CMP_directory_L2CacheController < CacheController
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default_param :l2_request_latency, Integer, 2
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default_param :l2_response_latency, Integer, 2
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default_param :to_L1_latency, Integer, 1
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#if 0 then automatically calculated
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default_param :lowest_bit, Integer, 0
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default_param :highest_bit, Integer, 0
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end
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class MESI_CMP_directory_L1CacheController < L1CacheController
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default_param :l1_request_latency, Integer, 2
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default_param :l1_response_latency, Integer, 2
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default_param :to_L2_latency, Integer, 1
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end
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class MESI_CMP_directory_DirectoryController < DirectoryController
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default_param :to_mem_ctrl_latency, Integer, 1
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default_param :directory_latency, Integer, 6
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end
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class MESI_CMP_directory_DMAController < DMAController
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default_param :request_latency, Integer, 6
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end
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class RubySystem
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# Random seed used by the simulation. If set to "rand", the seed
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@ -206,29 +232,5 @@ class RubySystem
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end
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#added by SS
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class MESI_CMP_directory_L2CacheController < CacheController
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default_param :l2_request_latency, Integer, 2
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default_param :l2_response_latency, Integer, 2
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default_param :to_L1_latency, Integer, 1
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#if 0 then automatically calculated
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default_param :lowest_bit, Integer, 0
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default_param :highest_bit, Integer, 0
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end
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class MESI_CMP_directory_L1CacheController < L1CacheController
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default_param :l1_request_latency, Integer, 2
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default_param :l1_response_latency, Integer, 2
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default_param :to_L2_latency, Integer, 1
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end
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class MESI_CMP_directory_DirectoryController < DirectoryController
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default_param :to_mem_ctrl_latency, Integer, 1
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default_param :directory_latency, Integer, 6
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end
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class MESI_CMP_directory_DMAController < DMAController
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default_param :request_latency, Integer, 6
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end
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@ -35,7 +35,7 @@ nb_cores = 8
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cpus = [ MemTest() for i in xrange(nb_cores) ]
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import ruby_config
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ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", nb_cores)
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ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
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# system simulated
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system = System(cpu = cpus, funcmem = PhysicalMemory(),
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