X86: Fold the MiscRegFile all the way into the ISA object.
This commit is contained in:
Gabe Black
parent
60d47aa5f9
commit
9993ca8280
6 changed files with 318 additions and 569 deletions
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@ -95,7 +95,6 @@ if env['TARGET_ISA'] == 'x86':
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Source('insts/microregop.cc')
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Source('insts/static_inst.cc')
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Source('isa.cc')
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Source('miscregfile.cc')
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Source('pagetable.cc')
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Source('predecoder.cc')
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Source('predecoder_tables.cc')
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@ -28,41 +28,331 @@
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* Authors: Gabe Black
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*/
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#include "arch/x86/isa.hh"
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#include "arch/x86/floatregs.hh"
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#include "arch/x86/isa.hh"
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#include "arch/x86/tlb.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "sim/serialize.hh"
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namespace X86ISA
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{
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void
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ISA::updateHandyM5Reg(Efer efer, CR0 cr0,
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SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags)
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{
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HandyM5Reg m5reg;
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if (efer.lma) {
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m5reg.mode = LongMode;
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if (csAttr.longMode)
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m5reg.submode = SixtyFourBitMode;
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else
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m5reg.submode = CompatabilityMode;
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} else {
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m5reg.mode = LegacyMode;
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if (cr0.pe) {
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if (rflags.vm)
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m5reg.submode = Virtual8086Mode;
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else
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m5reg.submode = ProtectedMode;
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} else {
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m5reg.submode = RealMode;
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}
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}
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m5reg.cpl = csAttr.dpl;
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m5reg.paging = cr0.pg;
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m5reg.prot = cr0.pe;
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// Compute the default and alternate operand size.
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if (m5reg.submode == SixtyFourBitMode || csAttr.defaultSize) {
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m5reg.defOp = 2;
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m5reg.altOp = 1;
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} else {
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m5reg.defOp = 1;
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m5reg.altOp = 2;
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}
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// Compute the default and alternate address size.
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if (m5reg.submode == SixtyFourBitMode) {
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m5reg.defAddr = 3;
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m5reg.altAddr = 2;
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} else if (csAttr.defaultSize) {
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m5reg.defAddr = 2;
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m5reg.altAddr = 1;
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} else {
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m5reg.defAddr = 1;
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m5reg.altAddr = 2;
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}
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// Compute the stack size
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if (m5reg.submode == SixtyFourBitMode) {
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m5reg.stack = 3;
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} else if (ssAttr.defaultSize) {
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m5reg.stack = 2;
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} else {
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m5reg.stack = 1;
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}
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regVal[MISCREG_M5_REG] = m5reg;
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}
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void
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ISA::clear()
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{
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miscRegFile.clear();
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// Blank everything. 0 might not be an appropriate value for some things,
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// but it is for most.
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memset(regVal, 0, NumMiscRegs * sizeof(MiscReg));
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regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16);
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regVal[MISCREG_DR7] = 1 << 10;
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}
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MiscReg
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ISA::readMiscRegNoEffect(int miscReg)
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{
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return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
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// Make sure we're not dealing with an illegal control register.
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// Instructions should filter out these indexes, and nothing else should
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// attempt to read them directly.
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assert( miscReg != MISCREG_CR1 &&
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!(miscReg > MISCREG_CR4 &&
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miscReg < MISCREG_CR8) &&
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!(miscReg > MISCREG_CR8 &&
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miscReg <= MISCREG_CR15));
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return regVal[miscReg];
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}
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MiscReg
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ISA::readMiscReg(int miscReg, ThreadContext *tc)
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ISA::readMiscReg(int miscReg, ThreadContext * tc)
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{
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return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
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if (miscReg == MISCREG_TSC) {
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return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
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}
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return readMiscRegNoEffect(miscReg);
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}
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void
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ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
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ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
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{
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miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
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// Make sure we're not dealing with an illegal control register.
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// Instructions should filter out these indexes, and nothing else should
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// attempt to write to them directly.
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assert( miscReg != MISCREG_CR1 &&
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!(miscReg > MISCREG_CR4 &&
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miscReg < MISCREG_CR8) &&
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!(miscReg > MISCREG_CR8 &&
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miscReg <= MISCREG_CR15));
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regVal[miscReg] = val;
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}
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void
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ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
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ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
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{
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miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
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MiscReg newVal = val;
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switch(miscReg)
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{
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case MISCREG_CR0:
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{
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CR0 toggled = regVal[miscReg] ^ val;
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CR0 newCR0 = val;
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Efer efer = regVal[MISCREG_EFER];
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if (toggled.pg && efer.lme) {
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if (newCR0.pg) {
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//Turning on long mode
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efer.lma = 1;
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regVal[MISCREG_EFER] = efer;
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} else {
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//Turning off long mode
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efer.lma = 0;
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regVal[MISCREG_EFER] = efer;
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}
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}
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if (toggled.pg) {
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tc->getITBPtr()->invalidateAll();
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tc->getDTBPtr()->invalidateAll();
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}
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//This must always be 1.
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newCR0.et = 1;
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newVal = newCR0;
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updateHandyM5Reg(regVal[MISCREG_EFER],
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newCR0,
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regVal[MISCREG_CS_ATTR],
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regVal[MISCREG_SS_ATTR],
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regVal[MISCREG_RFLAGS]);
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}
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break;
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case MISCREG_CR2:
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break;
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case MISCREG_CR3:
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tc->getITBPtr()->invalidateNonGlobal();
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tc->getDTBPtr()->invalidateNonGlobal();
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break;
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case MISCREG_CR4:
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{
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CR4 toggled = regVal[miscReg] ^ val;
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if (toggled.pae || toggled.pse || toggled.pge) {
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tc->getITBPtr()->invalidateAll();
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tc->getDTBPtr()->invalidateAll();
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}
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}
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break;
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case MISCREG_CR8:
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break;
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case MISCREG_CS_ATTR:
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{
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SegAttr toggled = regVal[miscReg] ^ val;
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SegAttr newCSAttr = val;
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if (toggled.longMode) {
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if (newCSAttr.longMode) {
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regVal[MISCREG_ES_EFF_BASE] = 0;
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regVal[MISCREG_CS_EFF_BASE] = 0;
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regVal[MISCREG_SS_EFF_BASE] = 0;
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regVal[MISCREG_DS_EFF_BASE] = 0;
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} else {
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regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE];
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regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE];
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regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE];
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regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE];
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}
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}
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updateHandyM5Reg(regVal[MISCREG_EFER],
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regVal[MISCREG_CR0],
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newCSAttr,
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regVal[MISCREG_SS_ATTR],
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regVal[MISCREG_RFLAGS]);
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}
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break;
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case MISCREG_SS_ATTR:
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updateHandyM5Reg(regVal[MISCREG_EFER],
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regVal[MISCREG_CR0],
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regVal[MISCREG_CS_ATTR],
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val,
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regVal[MISCREG_RFLAGS]);
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break;
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// These segments always actually use their bases, or in other words
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// their effective bases must stay equal to their actual bases.
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case MISCREG_FS_BASE:
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case MISCREG_GS_BASE:
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case MISCREG_HS_BASE:
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case MISCREG_TSL_BASE:
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case MISCREG_TSG_BASE:
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case MISCREG_TR_BASE:
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case MISCREG_IDTR_BASE:
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regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_BASE_BASE)] = val;
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break;
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// These segments ignore their bases in 64 bit mode.
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// their effective bases must stay equal to their actual bases.
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case MISCREG_ES_BASE:
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case MISCREG_CS_BASE:
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case MISCREG_SS_BASE:
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case MISCREG_DS_BASE:
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{
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Efer efer = regVal[MISCREG_EFER];
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SegAttr csAttr = regVal[MISCREG_CS_ATTR];
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if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode.
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regVal[MISCREG_SEG_EFF_BASE(miscReg -
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MISCREG_SEG_BASE_BASE)] = val;
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}
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break;
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case MISCREG_TSC:
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regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle();
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return;
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case MISCREG_DR0:
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case MISCREG_DR1:
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case MISCREG_DR2:
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case MISCREG_DR3:
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/* These should eventually set up breakpoints. */
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break;
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case MISCREG_DR4:
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miscReg = MISCREG_DR6;
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/* Fall through to have the same effects as DR6. */
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case MISCREG_DR6:
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{
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DR6 dr6 = regVal[MISCREG_DR6];
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DR6 newDR6 = val;
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dr6.b0 = newDR6.b0;
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dr6.b1 = newDR6.b1;
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dr6.b2 = newDR6.b2;
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dr6.b3 = newDR6.b3;
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dr6.bd = newDR6.bd;
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dr6.bs = newDR6.bs;
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dr6.bt = newDR6.bt;
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newVal = dr6;
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}
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break;
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case MISCREG_DR5:
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miscReg = MISCREG_DR7;
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/* Fall through to have the same effects as DR7. */
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case MISCREG_DR7:
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{
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DR7 dr7 = regVal[MISCREG_DR7];
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DR7 newDR7 = val;
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dr7.l0 = newDR7.l0;
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dr7.g0 = newDR7.g0;
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if (dr7.l0 || dr7.g0) {
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panic("Debug register breakpoints not implemented.\n");
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} else {
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/* Disable breakpoint 0. */
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}
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dr7.l1 = newDR7.l1;
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dr7.g1 = newDR7.g1;
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if (dr7.l1 || dr7.g1) {
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panic("Debug register breakpoints not implemented.\n");
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} else {
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/* Disable breakpoint 1. */
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}
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dr7.l2 = newDR7.l2;
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dr7.g2 = newDR7.g2;
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if (dr7.l2 || dr7.g2) {
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panic("Debug register breakpoints not implemented.\n");
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} else {
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/* Disable breakpoint 2. */
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}
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dr7.l3 = newDR7.l3;
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dr7.g3 = newDR7.g3;
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if (dr7.l3 || dr7.g3) {
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panic("Debug register breakpoints not implemented.\n");
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} else {
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/* Disable breakpoint 3. */
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}
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dr7.gd = newDR7.gd;
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dr7.rw0 = newDR7.rw0;
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dr7.len0 = newDR7.len0;
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dr7.rw1 = newDR7.rw1;
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dr7.len1 = newDR7.len1;
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dr7.rw2 = newDR7.rw2;
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dr7.len2 = newDR7.len2;
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dr7.rw3 = newDR7.rw3;
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dr7.len3 = newDR7.len3;
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}
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break;
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case MISCREG_M5_REG:
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// Writing anything to the m5reg with side effects makes it update
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// based on the current values of the relevant registers. The actual
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// value written is discarded.
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updateHandyM5Reg(regVal[MISCREG_EFER],
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regVal[MISCREG_CR0],
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regVal[MISCREG_CS_ATTR],
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regVal[MISCREG_SS_ATTR],
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regVal[MISCREG_RFLAGS]);
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return;
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default:
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break;
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}
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setMiscRegNoEffect(miscReg, newVal);
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}
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void
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ISA::serialize(EventManager *em, std::ostream & os)
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{
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SERIALIZE_ARRAY(regVal, NumMiscRegs);
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}
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void
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ISA::unserialize(EventManager *em, Checkpoint * cp,
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const std::string & section)
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{
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UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
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}
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int
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@ -80,22 +370,10 @@ int
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ISA::flattenFloatIndex(int reg)
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{
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if (reg >= NUM_FLOATREGS) {
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int top = miscRegFile.readRegNoEffect(MISCREG_X87_TOP);
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int top = readMiscRegNoEffect(MISCREG_X87_TOP);
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reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top);
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}
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return reg;
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}
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void
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ISA::serialize(EventManager *em, std::ostream &os)
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{
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miscRegFile.serialize(os);
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}
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void
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ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion)
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{
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miscRegFile.unserialize(cp, section);
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}
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}
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@ -31,28 +31,39 @@
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#ifndef __ARCH_X86_ISA_HH__
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#define __ARCH_X86_ISA_HH__
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#include "arch/x86/miscregfile.hh"
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#include "arch/x86/types.hh"
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#include "arch/x86/miscregs.hh"
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#include "arch/x86/registers.hh"
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#include "base/types.hh"
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#include <string>
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#include <iostream>
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class Checkpoint;
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class EventManager;
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class ThreadContext;
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namespace X86ISA
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{
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class ISA
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{
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protected:
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MiscRegFile miscRegFile;
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MiscReg regVal[NUM_MISCREGS];
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void updateHandyM5Reg(Efer efer, CR0 cr0,
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SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags);
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public:
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void clear();
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ISA()
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{
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clear();
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}
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MiscReg readMiscRegNoEffect(int miscReg);
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MiscReg readMiscReg(int miscReg, ThreadContext *tc);
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void setMiscRegNoEffect(int miscReg, const MiscReg val);
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void setMiscReg(int miscReg, const MiscReg val,
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ThreadContext *tc);
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void setMiscRegNoEffect(int miscReg, MiscReg val);
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void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
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int flattenIntIndex(int reg);
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int flattenFloatIndex(int reg);
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@ -149,6 +149,7 @@ output exec {{
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#include <cmath>
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#include "arch/x86/cpuid.hh"
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#include "arch/x86/faults.hh"
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#include "arch/x86/miscregs.hh"
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#include "arch/x86/tlb.hh"
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#include "base/bigint.hh"
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@ -1,406 +0,0 @@
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/*
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* Copyright (c) 2003-2006, 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Gabe Black
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007-2008 The Hewlett-Packard Development Company
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use of this software in source and binary forms,
|
||||
* with or without modification, are permitted provided that the
|
||||
* following conditions are met:
|
||||
*
|
||||
* The software must be used only for Non-Commercial Use which means any
|
||||
* use which is NOT directed to receiving any direct monetary
|
||||
* compensation for, or commercial advantage from such use. Illustrative
|
||||
* examples of non-commercial use are academic research, personal study,
|
||||
* teaching, education and corporate research & development.
|
||||
* Illustrative examples of commercial use are distributing products for
|
||||
* commercial advantage and providing services using the software for
|
||||
* commercial advantage.
|
||||
*
|
||||
* If you wish to use this software or functionality therein that may be
|
||||
* covered by patents for commercial use, please contact:
|
||||
* Director of Intellectual Property Licensing
|
||||
* Office of Strategy and Technology
|
||||
* Hewlett-Packard Company
|
||||
* 1501 Page Mill Road
|
||||
* Palo Alto, California 94304
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer. Redistributions
|
||||
* in binary form must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution. Neither the name of
|
||||
* the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission. No right of
|
||||
* sublicense is granted herewith. Derivatives of the software and
|
||||
* output created using the software may be prepared, but only for
|
||||
* Non-Commercial Uses. Derivatives of the software may be shared with
|
||||
* others provided: (i) the others agree to abide by the list of
|
||||
* conditions herein which includes the Non-Commercial Use restrictions;
|
||||
* and (ii) such Derivatives of the software include the above copyright
|
||||
* notice to acknowledge the contribution from this software where
|
||||
* applicable, this list of conditions and the disclaimer below.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Gabe Black
|
||||
*/
|
||||
|
||||
#include "arch/x86/miscregfile.hh"
|
||||
#include "arch/x86/tlb.hh"
|
||||
#include "cpu/base.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
#include "sim/serialize.hh"
|
||||
|
||||
using namespace X86ISA;
|
||||
using namespace std;
|
||||
|
||||
class Checkpoint;
|
||||
|
||||
void MiscRegFile::updateHandyM5Reg(Efer efer, CR0 cr0,
|
||||
SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags)
|
||||
{
|
||||
HandyM5Reg m5reg;
|
||||
if (efer.lma) {
|
||||
m5reg.mode = LongMode;
|
||||
if (csAttr.longMode)
|
||||
m5reg.submode = SixtyFourBitMode;
|
||||
else
|
||||
m5reg.submode = CompatabilityMode;
|
||||
} else {
|
||||
m5reg.mode = LegacyMode;
|
||||
if (cr0.pe) {
|
||||
if (rflags.vm)
|
||||
m5reg.submode = Virtual8086Mode;
|
||||
else
|
||||
m5reg.submode = ProtectedMode;
|
||||
} else {
|
||||
m5reg.submode = RealMode;
|
||||
}
|
||||
}
|
||||
m5reg.cpl = csAttr.dpl;
|
||||
m5reg.paging = cr0.pg;
|
||||
m5reg.prot = cr0.pe;
|
||||
|
||||
// Compute the default and alternate operand size.
|
||||
if (m5reg.submode == SixtyFourBitMode || csAttr.defaultSize) {
|
||||
m5reg.defOp = 2;
|
||||
m5reg.altOp = 1;
|
||||
} else {
|
||||
m5reg.defOp = 1;
|
||||
m5reg.altOp = 2;
|
||||
}
|
||||
|
||||
// Compute the default and alternate address size.
|
||||
if (m5reg.submode == SixtyFourBitMode) {
|
||||
m5reg.defAddr = 3;
|
||||
m5reg.altAddr = 2;
|
||||
} else if (csAttr.defaultSize) {
|
||||
m5reg.defAddr = 2;
|
||||
m5reg.altAddr = 1;
|
||||
} else {
|
||||
m5reg.defAddr = 1;
|
||||
m5reg.altAddr = 2;
|
||||
}
|
||||
|
||||
// Compute the stack size
|
||||
if (m5reg.submode == SixtyFourBitMode) {
|
||||
m5reg.stack = 3;
|
||||
} else if (ssAttr.defaultSize) {
|
||||
m5reg.stack = 2;
|
||||
} else {
|
||||
m5reg.stack = 1;
|
||||
}
|
||||
|
||||
regVal[MISCREG_M5_REG] = m5reg;
|
||||
}
|
||||
|
||||
void MiscRegFile::clear()
|
||||
{
|
||||
// Blank everything. 0 might not be an appropriate value for some things,
|
||||
// but it is for most.
|
||||
memset(regVal, 0, NumMiscRegs * sizeof(MiscReg));
|
||||
regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16);
|
||||
regVal[MISCREG_DR7] = 1 << 10;
|
||||
}
|
||||
|
||||
MiscReg MiscRegFile::readRegNoEffect(MiscRegIndex miscReg)
|
||||
{
|
||||
// Make sure we're not dealing with an illegal control register.
|
||||
// Instructions should filter out these indexes, and nothing else should
|
||||
// attempt to read them directly.
|
||||
assert( miscReg != MISCREG_CR1 &&
|
||||
!(miscReg > MISCREG_CR4 &&
|
||||
miscReg < MISCREG_CR8) &&
|
||||
!(miscReg > MISCREG_CR8 &&
|
||||
miscReg <= MISCREG_CR15));
|
||||
|
||||
return regVal[miscReg];
|
||||
}
|
||||
|
||||
MiscReg MiscRegFile::readReg(MiscRegIndex miscReg, ThreadContext * tc)
|
||||
{
|
||||
if (miscReg == MISCREG_TSC) {
|
||||
return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
|
||||
}
|
||||
return readRegNoEffect(miscReg);
|
||||
}
|
||||
|
||||
void MiscRegFile::setRegNoEffect(MiscRegIndex miscReg, const MiscReg &val)
|
||||
{
|
||||
// Make sure we're not dealing with an illegal control register.
|
||||
// Instructions should filter out these indexes, and nothing else should
|
||||
// attempt to write to them directly.
|
||||
assert( miscReg != MISCREG_CR1 &&
|
||||
!(miscReg > MISCREG_CR4 &&
|
||||
miscReg < MISCREG_CR8) &&
|
||||
!(miscReg > MISCREG_CR8 &&
|
||||
miscReg <= MISCREG_CR15));
|
||||
regVal[miscReg] = val;
|
||||
}
|
||||
|
||||
void MiscRegFile::setReg(MiscRegIndex miscReg,
|
||||
const MiscReg &val, ThreadContext * tc)
|
||||
{
|
||||
MiscReg newVal = val;
|
||||
switch(miscReg)
|
||||
{
|
||||
case MISCREG_CR0:
|
||||
{
|
||||
CR0 toggled = regVal[miscReg] ^ val;
|
||||
CR0 newCR0 = val;
|
||||
Efer efer = regVal[MISCREG_EFER];
|
||||
if (toggled.pg && efer.lme) {
|
||||
if (newCR0.pg) {
|
||||
//Turning on long mode
|
||||
efer.lma = 1;
|
||||
regVal[MISCREG_EFER] = efer;
|
||||
} else {
|
||||
//Turning off long mode
|
||||
efer.lma = 0;
|
||||
regVal[MISCREG_EFER] = efer;
|
||||
}
|
||||
}
|
||||
if (toggled.pg) {
|
||||
tc->getITBPtr()->invalidateAll();
|
||||
tc->getDTBPtr()->invalidateAll();
|
||||
}
|
||||
//This must always be 1.
|
||||
newCR0.et = 1;
|
||||
newVal = newCR0;
|
||||
updateHandyM5Reg(regVal[MISCREG_EFER],
|
||||
newCR0,
|
||||
regVal[MISCREG_CS_ATTR],
|
||||
regVal[MISCREG_SS_ATTR],
|
||||
regVal[MISCREG_RFLAGS]);
|
||||
}
|
||||
break;
|
||||
case MISCREG_CR2:
|
||||
break;
|
||||
case MISCREG_CR3:
|
||||
tc->getITBPtr()->invalidateNonGlobal();
|
||||
tc->getDTBPtr()->invalidateNonGlobal();
|
||||
break;
|
||||
case MISCREG_CR4:
|
||||
{
|
||||
CR4 toggled = regVal[miscReg] ^ val;
|
||||
if (toggled.pae || toggled.pse || toggled.pge) {
|
||||
tc->getITBPtr()->invalidateAll();
|
||||
tc->getDTBPtr()->invalidateAll();
|
||||
}
|
||||
}
|
||||
break;
|
||||
case MISCREG_CR8:
|
||||
break;
|
||||
case MISCREG_CS_ATTR:
|
||||
{
|
||||
SegAttr toggled = regVal[miscReg] ^ val;
|
||||
SegAttr newCSAttr = val;
|
||||
if (toggled.longMode) {
|
||||
if (newCSAttr.longMode) {
|
||||
regVal[MISCREG_ES_EFF_BASE] = 0;
|
||||
regVal[MISCREG_CS_EFF_BASE] = 0;
|
||||
regVal[MISCREG_SS_EFF_BASE] = 0;
|
||||
regVal[MISCREG_DS_EFF_BASE] = 0;
|
||||
} else {
|
||||
regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE];
|
||||
regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE];
|
||||
regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE];
|
||||
regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE];
|
||||
}
|
||||
}
|
||||
updateHandyM5Reg(regVal[MISCREG_EFER],
|
||||
regVal[MISCREG_CR0],
|
||||
newCSAttr,
|
||||
regVal[MISCREG_SS_ATTR],
|
||||
regVal[MISCREG_RFLAGS]);
|
||||
}
|
||||
break;
|
||||
case MISCREG_SS_ATTR:
|
||||
updateHandyM5Reg(regVal[MISCREG_EFER],
|
||||
regVal[MISCREG_CR0],
|
||||
regVal[MISCREG_CS_ATTR],
|
||||
val,
|
||||
regVal[MISCREG_RFLAGS]);
|
||||
break;
|
||||
// These segments always actually use their bases, or in other words
|
||||
// their effective bases must stay equal to their actual bases.
|
||||
case MISCREG_FS_BASE:
|
||||
case MISCREG_GS_BASE:
|
||||
case MISCREG_HS_BASE:
|
||||
case MISCREG_TSL_BASE:
|
||||
case MISCREG_TSG_BASE:
|
||||
case MISCREG_TR_BASE:
|
||||
case MISCREG_IDTR_BASE:
|
||||
regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_BASE_BASE)] = val;
|
||||
break;
|
||||
// These segments ignore their bases in 64 bit mode.
|
||||
// their effective bases must stay equal to their actual bases.
|
||||
case MISCREG_ES_BASE:
|
||||
case MISCREG_CS_BASE:
|
||||
case MISCREG_SS_BASE:
|
||||
case MISCREG_DS_BASE:
|
||||
{
|
||||
Efer efer = regVal[MISCREG_EFER];
|
||||
SegAttr csAttr = regVal[MISCREG_CS_ATTR];
|
||||
if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode.
|
||||
regVal[MISCREG_SEG_EFF_BASE(miscReg -
|
||||
MISCREG_SEG_BASE_BASE)] = val;
|
||||
}
|
||||
break;
|
||||
case MISCREG_TSC:
|
||||
regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle();
|
||||
return;
|
||||
case MISCREG_DR0:
|
||||
case MISCREG_DR1:
|
||||
case MISCREG_DR2:
|
||||
case MISCREG_DR3:
|
||||
/* These should eventually set up breakpoints. */
|
||||
break;
|
||||
case MISCREG_DR4:
|
||||
miscReg = MISCREG_DR6;
|
||||
/* Fall through to have the same effects as DR6. */
|
||||
case MISCREG_DR6:
|
||||
{
|
||||
DR6 dr6 = regVal[MISCREG_DR6];
|
||||
DR6 newDR6 = val;
|
||||
dr6.b0 = newDR6.b0;
|
||||
dr6.b1 = newDR6.b1;
|
||||
dr6.b2 = newDR6.b2;
|
||||
dr6.b3 = newDR6.b3;
|
||||
dr6.bd = newDR6.bd;
|
||||
dr6.bs = newDR6.bs;
|
||||
dr6.bt = newDR6.bt;
|
||||
newVal = dr6;
|
||||
}
|
||||
break;
|
||||
case MISCREG_DR5:
|
||||
miscReg = MISCREG_DR7;
|
||||
/* Fall through to have the same effects as DR7. */
|
||||
case MISCREG_DR7:
|
||||
{
|
||||
DR7 dr7 = regVal[MISCREG_DR7];
|
||||
DR7 newDR7 = val;
|
||||
dr7.l0 = newDR7.l0;
|
||||
dr7.g0 = newDR7.g0;
|
||||
if (dr7.l0 || dr7.g0) {
|
||||
panic("Debug register breakpoints not implemented.\n");
|
||||
} else {
|
||||
/* Disable breakpoint 0. */
|
||||
}
|
||||
dr7.l1 = newDR7.l1;
|
||||
dr7.g1 = newDR7.g1;
|
||||
if (dr7.l1 || dr7.g1) {
|
||||
panic("Debug register breakpoints not implemented.\n");
|
||||
} else {
|
||||
/* Disable breakpoint 1. */
|
||||
}
|
||||
dr7.l2 = newDR7.l2;
|
||||
dr7.g2 = newDR7.g2;
|
||||
if (dr7.l2 || dr7.g2) {
|
||||
panic("Debug register breakpoints not implemented.\n");
|
||||
} else {
|
||||
/* Disable breakpoint 2. */
|
||||
}
|
||||
dr7.l3 = newDR7.l3;
|
||||
dr7.g3 = newDR7.g3;
|
||||
if (dr7.l3 || dr7.g3) {
|
||||
panic("Debug register breakpoints not implemented.\n");
|
||||
} else {
|
||||
/* Disable breakpoint 3. */
|
||||
}
|
||||
dr7.gd = newDR7.gd;
|
||||
dr7.rw0 = newDR7.rw0;
|
||||
dr7.len0 = newDR7.len0;
|
||||
dr7.rw1 = newDR7.rw1;
|
||||
dr7.len1 = newDR7.len1;
|
||||
dr7.rw2 = newDR7.rw2;
|
||||
dr7.len2 = newDR7.len2;
|
||||
dr7.rw3 = newDR7.rw3;
|
||||
dr7.len3 = newDR7.len3;
|
||||
}
|
||||
break;
|
||||
case MISCREG_M5_REG:
|
||||
// Writing anything to the m5reg with side effects makes it update
|
||||
// based on the current values of the relevant registers. The actual
|
||||
// value written is discarded.
|
||||
updateHandyM5Reg(regVal[MISCREG_EFER],
|
||||
regVal[MISCREG_CR0],
|
||||
regVal[MISCREG_CS_ATTR],
|
||||
regVal[MISCREG_SS_ATTR],
|
||||
regVal[MISCREG_RFLAGS]);
|
||||
return;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
setRegNoEffect(miscReg, newVal);
|
||||
}
|
||||
|
||||
void MiscRegFile::serialize(std::ostream & os)
|
||||
{
|
||||
SERIALIZE_ARRAY(regVal, NumMiscRegs);
|
||||
}
|
||||
|
||||
void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
|
||||
{
|
||||
UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
|
||||
}
|
||||
|
|
@ -1,134 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2003-2006 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Gabe Black
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2007-2008 The Hewlett-Packard Development Company
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use of this software in source and binary forms,
|
||||
* with or without modification, are permitted provided that the
|
||||
* following conditions are met:
|
||||
*
|
||||
* The software must be used only for Non-Commercial Use which means any
|
||||
* use which is NOT directed to receiving any direct monetary
|
||||
* compensation for, or commercial advantage from such use. Illustrative
|
||||
* examples of non-commercial use are academic research, personal study,
|
||||
* teaching, education and corporate research & development.
|
||||
* Illustrative examples of commercial use are distributing products for
|
||||
* commercial advantage and providing services using the software for
|
||||
* commercial advantage.
|
||||
*
|
||||
* If you wish to use this software or functionality therein that may be
|
||||
* covered by patents for commercial use, please contact:
|
||||
* Director of Intellectual Property Licensing
|
||||
* Office of Strategy and Technology
|
||||
* Hewlett-Packard Company
|
||||
* 1501 Page Mill Road
|
||||
* Palo Alto, California 94304
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer. Redistributions
|
||||
* in binary form must reproduce the above copyright notice, this list of
|
||||
* conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution. Neither the name of
|
||||
* the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission. No right of
|
||||
* sublicense is granted herewith. Derivatives of the software and
|
||||
* output created using the software may be prepared, but only for
|
||||
* Non-Commercial Uses. Derivatives of the software may be shared with
|
||||
* others provided: (i) the others agree to abide by the list of
|
||||
* conditions herein which includes the Non-Commercial Use restrictions;
|
||||
* and (ii) such Derivatives of the software include the above copyright
|
||||
* notice to acknowledge the contribution from this software where
|
||||
* applicable, this list of conditions and the disclaimer below.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Gabe Black
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_X86_MISCREGFILE_HH__
|
||||
#define __ARCH_X86_MISCREGFILE_HH__
|
||||
|
||||
#include <string>
|
||||
|
||||
#include "arch/x86/faults.hh"
|
||||
#include "arch/x86/miscregs.hh"
|
||||
#include "arch/x86/registers.hh"
|
||||
#include "base/types.hh"
|
||||
|
||||
class Checkpoint;
|
||||
|
||||
namespace X86ISA
|
||||
{
|
||||
class MiscRegFile
|
||||
{
|
||||
protected:
|
||||
MiscReg regVal[NUM_MISCREGS];
|
||||
void updateHandyM5Reg(Efer efer, CR0 cr0,
|
||||
SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags);
|
||||
|
||||
public:
|
||||
void clear();
|
||||
|
||||
MiscRegFile()
|
||||
{
|
||||
clear();
|
||||
}
|
||||
|
||||
MiscReg readRegNoEffect(MiscRegIndex miscReg);
|
||||
|
||||
MiscReg readReg(MiscRegIndex miscReg, ThreadContext *tc);
|
||||
|
||||
void setRegNoEffect(MiscRegIndex miscReg, const MiscReg &val);
|
||||
|
||||
void setReg(MiscRegIndex miscReg,
|
||||
const MiscReg &val, ThreadContext *tc);
|
||||
|
||||
void serialize(std::ostream & os);
|
||||
|
||||
void unserialize(Checkpoint * cp, const std::string §ion);
|
||||
|
||||
void copyMiscRegs(ThreadContext * tc);
|
||||
};
|
||||
}
|
||||
|
||||
#endif //__ARCH_X86_MISCREGFILE_HH__
|
||||
Loading…
Reference in a new issue