ARM: Fold the MiscRegFile all the way into the ISA object.
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5643a222e3
commit
e14c408b62
4 changed files with 37 additions and 178 deletions
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@ -39,7 +39,6 @@ if env['TARGET_ISA'] == 'arm':
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Source('insts/mem.cc')
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Source('insts/pred_inst.cc')
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Source('insts/static_inst.cc')
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Source('isa.cc')
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Source('pagetable.cc')
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Source('tlb.cc')
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Source('vtophys.cc')
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@ -1,79 +0,0 @@
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/*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/arm/isa.hh"
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#include "cpu/thread_context.hh"
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namespace ArmISA
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{
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void
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ISA::clear()
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{
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miscRegFile.clear();
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}
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MiscReg
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ISA::readMiscRegNoEffect(int miscReg)
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{
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return miscRegFile.readRegNoEffect(miscReg);
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}
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MiscReg
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ISA::readMiscReg(int miscReg, ThreadContext *tc)
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{
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return miscRegFile.readReg(miscReg, tc);
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}
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void
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ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
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{
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miscRegFile.setRegNoEffect(miscReg, val);
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}
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void
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ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
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{
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miscRegFile.setReg(miscReg, val, tc);
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}
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void
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ISA::serialize(std::ostream &os)
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{
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//miscRegFile.serialize(os);
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}
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void
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ISA::unserialize(Checkpoint *cp, const std::string §ion)
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{
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//miscRegFile.unserialize(cp, section);
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}
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}
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@ -31,9 +31,10 @@
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#ifndef __ARCH_ARM_ISA_HH__
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#define __ARCH_MRM_ISA_HH__
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#include "arch/arm/misc_regfile.hh"
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#include "arch/arm/registers.hh"
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#include "arch/arm/types.hh"
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class ThreadContext;
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class Checkpoint;
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class EventManager;
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@ -42,17 +43,41 @@ namespace ArmISA
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class ISA
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{
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protected:
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MiscRegFile miscRegFile;
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MiscReg miscRegs[NumMiscRegs];
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public:
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void clear();
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void clear()
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{
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// Unknown startup state currently
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}
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MiscReg readMiscRegNoEffect(int miscReg);
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MiscReg readMiscReg(int miscReg, ThreadContext *tc);
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MiscReg
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readMiscRegNoEffect(int misc_reg)
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{
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assert(misc_reg < NumMiscRegs);
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return miscRegs[misc_reg];
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}
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void setMiscRegNoEffect(int miscReg, const MiscReg val);
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void setMiscReg(int miscReg, const MiscReg val,
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ThreadContext *tc);
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MiscReg
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readMiscReg(int misc_reg, ThreadContext *tc)
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{
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assert(misc_reg < NumMiscRegs);
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return miscRegs[misc_reg];
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}
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void
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setMiscRegNoEffect(int misc_reg, const MiscReg &val)
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{
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assert(misc_reg < NumMiscRegs);
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miscRegs[misc_reg] = val;
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}
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void
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setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
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{
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assert(misc_reg < NumMiscRegs);
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miscRegs[misc_reg] = val;
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}
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int
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flattenIntIndex(int reg)
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@ -66,8 +91,10 @@ namespace ArmISA
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return reg;
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}
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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void serialize(std::ostream &os)
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{}
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void unserialize(Checkpoint *cp, const std::string §ion)
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{}
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ISA()
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{
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@ -1,88 +0,0 @@
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/*
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Stephen Hines
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*/
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#ifndef __ARCH_ARM_REGFILE_MISC_REGFILE_HH__
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#define __ARCH_ARM_REGFILE_MISC_REGFILE_HH__
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#include "arch/arm/registers.hh"
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#include "arch/arm/types.hh"
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#include "sim/faults.hh"
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class ThreadContext;
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namespace ArmISA
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{
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static inline std::string
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getMiscRegName(RegIndex)
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{
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return "";
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}
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class MiscRegFile {
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protected:
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MiscReg miscRegFile[NumMiscRegs];
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public:
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void clear()
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{
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// Unknown startup state in misc register file currently
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}
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void copyMiscRegs(ThreadContext *tc);
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MiscReg readRegNoEffect(int misc_reg)
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{
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assert(misc_reg < NumMiscRegs);
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return miscRegFile[misc_reg];
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}
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MiscReg readReg(int misc_reg, ThreadContext *tc)
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{
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assert(misc_reg < NumMiscRegs);
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return miscRegFile[misc_reg];
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}
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void setRegNoEffect(int misc_reg, const MiscReg &val)
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{
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assert(misc_reg < NumMiscRegs);
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miscRegFile[misc_reg] = val;
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}
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void setReg(int misc_reg, const MiscReg &val,
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ThreadContext *tc)
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{
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assert(misc_reg < NumMiscRegs);
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miscRegFile[misc_reg] = val;
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}
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};
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} // namespace ArmISA
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#endif
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