ARM: Make DataOps select from a set of ways to set the c and v flags.
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Gabe Black
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148c265cf3
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@ -83,31 +83,27 @@ format DataOp {
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1: decode MISC_OPCODE {
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0x9: decode PREPOST {
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0: decode OPCODE {
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0x0: mul({{ Rn = resTemp = Rm * Rs; }},
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{{ Cpsr<29:> }},
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{{ Cpsr<28:> }});
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0x1: mla({{ Rn = resTemp = Rm * Rs; }},
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{{ Cpsr<29:> }},
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{{ Cpsr<28:> }});
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0x0: mul({{ Rn = resTemp = Rm * Rs; }}, none);
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0x1: mla({{ Rn = resTemp = Rm * Rs; }}, none);
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0x2: WarnUnimpl::umall();
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0x4: umull({{
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resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
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Rd = (uint32_t)(resTemp & 0xffffffff);
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Rn = (uint32_t)(resTemp >> 32);
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}}, {{ 1 }}, {{ 1 }});
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}});
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0x5: WarnUnimpl::smlal();
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0x6: smull({{
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resTemp = ((int64_t)(int32_t)Rm)*
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((int64_t)(int32_t)Rs);
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Rd = (int32_t)(resTemp & 0xffffffff);
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Rn = (int32_t)(resTemp >> 32);
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}}, {{ 1 }}, {{ 1 }});
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}});
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0x7: umlal({{
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resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
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resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd);
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Rd = (uint32_t)(resTemp & 0xffffffff);
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Rn = (uint32_t)(resTemp >> 32);
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}}, {{ 1 }}, {{ 1 }});
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}});
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}
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1: decode PUBWL {
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0x10: WarnUnimpl::swp();
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@ -229,32 +225,16 @@ format DataOp {
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0: decode OPCODE {
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0x0: and({{ Rd = resTemp = Rn & op2; }});
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0x1: eor({{ Rd = resTemp = Rn ^ op2; }});
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0x2: sub({{ Rd = resTemp = Rn - op2; }},
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{{ arm_sub_carry(resTemp, Rn, op2) }},
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{{ arm_sub_overflow(resTemp, Rn, op2) }});
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0x3: rsb({{ Rd = resTemp = op2 - Rn; }},
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{{ arm_sub_carry(resTemp, op2, Rn) }},
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{{ arm_sub_overflow(resTemp, op2, Rn) }});
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0x4: add({{ Rd = resTemp = Rn + op2; }},
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{{ arm_add_carry(resTemp, Rn, op2) }},
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{{ arm_add_overflow(resTemp, Rn, op2) }});
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0x5: adc({{ Rd = resTemp = Rn + op2 + Cpsr<29:>; }},
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{{ arm_add_carry(resTemp, Rn, op2) }},
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{{ arm_add_overflow(resTemp, Rn, op2) }});
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0x6: sbc({{ Rd = resTemp = Rn - op2 - !Cpsr<29:>; }},
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{{ arm_sub_carry(resTemp, Rn, op2) }},
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{{ arm_sub_overflow(resTemp, Rn, op2) }});
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0x7: rsc({{ Rd = resTemp = op2 - Rn - !Cpsr<29:>; }},
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{{ arm_sub_carry(resTemp, op2, Rn) }},
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{{ arm_sub_overflow(resTemp, op2, Rn) }});
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0x2: sub({{ Rd = resTemp = Rn - op2; }}, sub);
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0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, rsb);
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0x4: add({{ Rd = resTemp = Rn + op2; }}, add);
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0x5: adc({{ Rd = resTemp = Rn + op2 + Cpsr<29:>; }}, add);
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0x6: sbc({{ Rd = resTemp = Rn - op2 - !Cpsr<29:>; }}, sub);
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0x7: rsc({{ Rd = resTemp = op2 - Rn - !Cpsr<29:>; }}, rsb);
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0x8: tst({{ resTemp = Rn & op2; }});
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0x9: teq({{ resTemp = Rn ^ op2; }});
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0xa: cmp({{ resTemp = Rn - op2; }},
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{{ arm_sub_carry(resTemp, Rn, op2) }},
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{{ arm_sub_overflow(resTemp, Rn, op2) }});
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0xb: cmn({{ resTemp = Rn + op2; }},
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{{ arm_add_carry(resTemp, Rn, op2) }},
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{{ arm_add_overflow(resTemp, Rn, op2) }});
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0xa: cmp({{ resTemp = Rn - op2; }}, sub);
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0xb: cmn({{ resTemp = Rn + op2; }}, add);
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0xc: orr({{ Rd = resTemp = Rn | op2; }});
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0xd: mov({{ Rd = resTemp = op2; }});
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0xe: bic({{ Rd = resTemp = Rn & ~op2; }});
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@ -318,32 +298,16 @@ format DataOp {
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format DataImmOp {
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0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }});
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0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }});
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0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }},
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{{ arm_sub_carry(resTemp, Rn, rotated_imm) }},
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{{ arm_sub_overflow(resTemp, Rn, rotated_imm) }});
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0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }},
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{{ arm_sub_carry(resTemp, rotated_imm, Rn) }},
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{{ arm_sub_overflow(resTemp, rotated_imm, Rn) }});
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0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }},
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{{ arm_add_carry(resTemp, Rn, rotated_imm) }},
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{{ arm_add_overflow(resTemp, Rn, rotated_imm) }});
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0x5: adci({{ Rd = resTemp = Rn + rotated_imm + Cpsr<29:>; }},
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{{ arm_add_carry(resTemp, Rn, rotated_imm) }},
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{{ arm_add_overflow(resTemp, Rn, rotated_imm) }});
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0x6: sbci({{ Rd = resTemp = Rn -rotated_imm - !Cpsr<29:>; }},
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{{ arm_sub_carry(resTemp, Rn, rotated_imm) }},
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{{ arm_sub_overflow(resTemp, Rn, rotated_imm) }});
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0x7: rsci({{ Rd = resTemp = rotated_imm - Rn - !Cpsr<29:>;}},
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{{ arm_sub_carry(resTemp, rotated_imm, Rn) }},
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{{ arm_sub_overflow(resTemp, rotated_imm, Rn) }});
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0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }}, sub);
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0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }}, rsb);
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0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }}, add);
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0x5: adci({{ Rd = resTemp = Rn + rotated_imm + Cpsr<29:>; }}, add);
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0x6: sbci({{ Rd = resTemp = Rn -rotated_imm - !Cpsr<29:>; }}, sub);
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0x7: rsci({{ Rd = resTemp = rotated_imm - Rn - !Cpsr<29:>;}}, rsb);
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0x8: tsti({{ resTemp = Rn & rotated_imm; }});
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0x9: teqi({{ resTemp = Rn ^ rotated_imm; }});
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0xa: cmpi({{ resTemp = Rn - rotated_imm; }},
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{{ arm_sub_carry(resTemp, Rn, rotated_imm) }},
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{{ arm_sub_overflow(resTemp, Rn, rotated_imm) }});
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0xb: cmni({{ resTemp = Rn + rotated_imm; }},
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{{ arm_add_carry(resTemp, Rn, rotated_imm) }},
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{{ arm_add_overflow(resTemp, Rn, rotated_imm) }});
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0xa: cmpi({{ resTemp = Rn - rotated_imm; }}, sub);
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0xb: cmni({{ resTemp = Rn + rotated_imm; }}, add);
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0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }});
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0xd: movi({{ Rd = resTemp = rotated_imm; }});
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0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }});
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@ -101,24 +101,54 @@ let {{
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}};
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def format DataOp(code, icValue = {{ }},
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ivValue = {{ Cpsr<28:> }}) {{
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let {{
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def getCcCode(flagtype):
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icReg = icImm = iv = ''
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if flagtype == "none":
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icReg = icImm = iv = '1'
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elif flagtype == "add":
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icReg = icImm = 'findCarry(32, resTemp, Rn, op2)'
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iv = 'findOverflow(32, resTemp, Rn, op2)'
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elif flagtype == "sub":
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icReg = icImm ='findCarry(32, resTemp, Rn, ~op2)'
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iv = 'findOverflow(32, resTemp, Rn, ~op2)'
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elif flagtype == "rsb":
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icReg = icImm = 'findCarry(32, resTemp, op2, ~Rn)'
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iv = 'findOverflow(32, resTemp, op2, ~Rn)'
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else:
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icReg = 'shift_carry_rs(Rm, Rs, shift, Cpsr<29:>)'
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icImm = 'shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)'
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iv = 'Cpsr<28:>'
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return (calcCcCode % {"icValue" : icReg, "ivValue" : iv},
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calcCcCode % {"icValue" : icImm, "ivValue" : iv})
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def getImmCcCode(flagtype):
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ivValue = icValue = ''
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if flagtype == "none":
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icValue = ivValue = '1'
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elif flagtype == "add":
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icValue = 'findCarry(32, resTemp, Rn, rotated_imm)'
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ivValue = 'findOverflow(32, resTemp, Rn, rotated_imm)'
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elif flagtype == "sub":
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icValue = 'findCarry(32, resTemp, Rn, ~rotated_imm)'
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ivValue = 'findOverflow(32, resTemp, Rn, ~rotated_imm)'
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elif flagtype == "rsb":
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icValue = 'findCarry(32, resTemp, rotated_imm, ~Rn)'
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ivValue = 'findOverflow(32, resTemp, rotated_imm, ~Rn)'
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else:
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icValue = '(rotate ? rotated_carry:Cpsr<29:>)'
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ivValue = 'Cpsr<28:>'
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return calcCcCode % vars()
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}};
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def format DataOp(code, flagtype = logic) {{
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(regCcCode, immCcCode) = getCcCode(flagtype)
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regCode = '''uint32_t op2 = shift_rm_rs(Rm, Rs,
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shift, Cpsr<29:0>);
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op2 = op2;''' + code
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immCode = '''uint32_t op2 = shift_rm_imm(Rm, shift_size,
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shift, Cpsr<29:0>);
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op2 = op2;''' + code
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if icValue == " ":
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icValueReg = 'shift_carry_rs(Rm, Rs, shift, Cpsr<29:>)'
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icValueImm = 'shift_carry_imm(Rm, shift_size, shift, Cpsr<29:>)'
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else:
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icValueReg = icValue
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icValueImm = icValue
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regCcCode = calcCcCode % {"icValue" : icValueReg,
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"ivValue" : ivValue}
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immCcCode = calcCcCode % {"icValue" : icValueImm,
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"ivValue" : ivValue}
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regIop = InstObjParams(name, Name, 'PredIntOp',
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{"code": regCode,
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"predicate_test": predicateTest})
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@ -146,15 +176,13 @@ def format DataOp(code, icValue = {{ }},
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decode_block = DataDecode.subst(regIop)
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}};
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def format DataImmOp(code,
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icValue = {{ (rotate ? rotated_carry:Cpsr<29:>) }},
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ivValue = {{ Cpsr<28:> }}) {{
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def format DataImmOp(code, flagtype = logic) {{
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code += "resTemp = resTemp;"
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iop = InstObjParams(name, Name, 'PredImmOp',
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{"code": code,
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"predicate_test": predicateTest})
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ccIop = InstObjParams(name, Name + "Cc", 'PredImmOp',
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{"code": code + calcCcCode % vars(),
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{"code": code + getImmCcCode(flagtype),
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"predicate_test": predicateTest})
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header_output = BasicDeclare.subst(iop) + \
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BasicDeclare.subst(ccIop)
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@ -69,6 +69,7 @@ output exec {{
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#include "arch/arm/faults.hh"
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#include "arch/arm/isa_traits.hh"
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#include "arch/arm/utility.hh"
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#include "base/condcodes.hh"
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#include <cmath>
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#if defined(linux)
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