645 lines
29 KiB
C++
645 lines
29 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2007-2008 The Florida State University
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Stephen Hines
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////////////////////////////////////////////////////////////////////
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//
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// The actual ARM ISA decoder
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// --------------------------
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// The following instructions are specified in the ARM ISA
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// Specification. Decoding closely follows the style specified
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// in the ARM ISA specification document starting with Table B.1 or 3-1
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//
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//
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decode COND_CODE default Unknown::unknown() {
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0xf: decode COND_CODE {
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0x0: decode OPCODE {
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// Just a simple trick to allow us to specify our new uops here
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0x0: PredImmOp::addi_uop({{ Raddr = Rn + rotated_imm; }},
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'IsMicroop');
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0x1: PredImmOp::subi_uop({{ Raddr = Rn - rotated_imm; }},
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'IsMicroop');
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0x2: ArmLoadMemory::ldr_uop({{ Rd = Mem; }},
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{{ EA = Raddr + disp; }},
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inst_flags = [IsMicroop]);
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0x3: ArmStoreMemory::str_uop({{ Mem = Rd; }},
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{{ EA = Raddr + disp; }},
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inst_flags = [IsMicroop]);
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0x4: PredImmOp::addi_rd_uop({{ Rd = Rn + rotated_imm; }},
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'IsMicroop');
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0x5: PredImmOp::subi_rd_uop({{ Rd = Rn - rotated_imm; }},
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'IsMicroop');
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}
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0x1: decode OPCODE {
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0x0: PredIntOp::mvtd_uop({{ Fd.ud = ((uint64_t) Rhi << 32)|Rlo; }},
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'IsMicroop');
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0x1: PredIntOp::mvfd_uop({{ Rhi = (Fd.ud >> 32) & 0xffffffff;
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Rlo = Fd.ud & 0xffffffff; }},
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'IsMicroop');
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0x2: ArmLoadMemory::ldhi_uop({{ Rhi = Mem; }},
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{{ EA = Rn + disp; }},
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inst_flags = [IsMicroop]);
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0x3: ArmLoadMemory::ldlo_uop({{ Rlo = Mem; }},
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{{ EA = Rn + disp; }},
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inst_flags = [IsMicroop]);
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0x4: ArmStoreMemory::sthi_uop({{ Mem = Rhi; }},
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{{ EA = Rn + disp; }},
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inst_flags = [IsMicroop]);
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0x5: ArmStoreMemory::stlo_uop({{ Mem = Rlo; }},
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{{ EA = Rn + disp; }},
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inst_flags = [IsMicroop]);
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}
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default: Unknown::unknown(); // TODO: Ignore other NV space for now
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}
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default: decode ENCODING {
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format DataOp {
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0x0: decode SEVEN_AND_FOUR {
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1: decode MISC_OPCODE {
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0x9: decode PREPOST {
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0: decode OPCODE {
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0x0: mul({{ Rn = resTemp = Rm * Rs; }}, none);
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0x1: mla({{ Rn = resTemp = Rm * Rs; }}, none);
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0x2: WarnUnimpl::umall();
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0x4: umull({{
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resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
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Rd = (uint32_t)(resTemp & 0xffffffff);
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Rn = (uint32_t)(resTemp >> 32);
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}});
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0x5: WarnUnimpl::smlal();
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0x6: smull({{
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resTemp = ((int64_t)(int32_t)Rm)*
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((int64_t)(int32_t)Rs);
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Rd = (int32_t)(resTemp & 0xffffffff);
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Rn = (int32_t)(resTemp >> 32);
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}});
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0x7: umlal({{
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resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
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resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd);
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Rd = (uint32_t)(resTemp & 0xffffffff);
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Rn = (uint32_t)(resTemp >> 32);
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}});
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}
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1: decode PUBWL {
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0x10: WarnUnimpl::swp();
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0x14: WarnUnimpl::swpb();
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0x18: WarnUnimpl::strex();
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0x19: WarnUnimpl::ldrex();
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}
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}
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0xb: decode PUBWL {
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format ArmStoreMemory {
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0x0, 0x8: strh_({{ Mem.uh = Rd.uh;
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Rn = Rn + Rm; }},
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{{ EA = Rn; }});
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0x4, 0xc: strh_il({{ Mem.uh = Rd.uh;
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Rn = Rn + hilo; }},
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{{ EA = Rn; }});
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0x10, 0x18: strh_p({{ Mem.uh = Rd.uh; }},
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{{ EA = Rn + Rm; }});
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0x12, 0x1a: strh_pw({{ Mem.uh = Rd.uh;
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Rn = Rn + Rm; }},
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{{ EA = Rn + Rm; }});
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0x14, 0x1c: strh_pil({{ Mem.uh = Rd.uh; }},
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{{ EA = Rn + hilo; }});
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0x16, 0x1e: strh_piwl({{ Mem.uh = Rd.uh;
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Rn = Rn + hilo; }},
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{{ EA = Rn + hilo; }});
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}
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format ArmLoadMemory {
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0x1, 0x9: ldrh_l({{ Rd.uh = Mem.uh;
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Rn = Rn + Rm; }},
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{{ EA = Rn; }});
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0x5, 0xd: ldrh_il({{ Rd.uh = Mem.uh;
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Rn = Rn + hilo; }},
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{{ EA = Rn; }});
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0x11, 0x19: ldrh_pl({{ Rd.uh = Mem.uh; }},
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{{ EA = Rn + Rm; }});
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0x13, 0x1b: ldrh_pwl({{ Rd.uh = Mem.uh;
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Rn = Rn + Rm; }},
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{{ EA = Rn + Rm; }});
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0x15, 0x1d: ldrh_pil({{ Rd.uh = Mem.uh; }},
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{{ EA = Rn + hilo; }});
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0x17, 0x1f: ldrh_piwl({{ Rd.uh = Mem.uh;
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Rn = Rn + hilo; }},
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{{ EA = Rn + hilo; }});
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}
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}
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format ArmLoadMemory {
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0xd: decode PUBWL {
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0x1: ldrsb_l({{ Rd = Mem.sb;
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Rn = Rn + Rm; }},
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{{ EA = Rn; }});
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0x5: ldrsb_il({{ Rd = Mem.sb;
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Rn = Rn + hilo; }},
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{{ EA = Rn; }});
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0x9: ldrsb_ul({{ Rd = Mem.sb;
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Rn = Rn - Rm; }},
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{{ EA = Rn; }});
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0xd: ldrsb_uil({{ Rd = Mem.sb;
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Rn = Rn - hilo; }},
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{{ EA = Rn; }});
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0x11: ldrsb_pl({{ Rd = Mem.sb; }},
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{{ EA = Rn + Rm; }});
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0x13: ldrsb_pwl({{ Rd = Mem.sb;
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Rn = Rn + Rm; }},
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{{ EA = Rn + Rm; }});
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0x15: ldrsb_pil({{ Rd = Mem.sb; }},
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{{ EA = Rn + hilo; }});
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0x17: ldrsb_piwl({{ Rd = Mem.sb;
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Rn = Rn + hilo; }},
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{{ EA = Rn + hilo; }});
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0x19: ldrsb_pul({{ Rd = Mem.sb; }},
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{{ EA = Rn - Rm; }});
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0x1b: ldrsb_puwl({{ Rd = Mem.sb;
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Rn = Rn - Rm; }},
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{{ EA = Rn - Rm; }});
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0x1d: ldrsb_puil({{ Rd = Mem.sb; }},
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{{ EA = Rn - hilo; }});
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0x1f: ldrsb_puiwl({{ Rd = Mem.sb;
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Rn = Rn - hilo; }},
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{{ EA = Rn - hilo; }});
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}
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0xf: decode PUBWL {
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0x1: ldrsh_l({{ Rd = Mem.sh;
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Rn = Rn + Rm; }},
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{{ EA = Rn; }});
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0x5: ldrsh_il({{ Rd = Mem.sh;
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Rn = Rn + hilo; }},
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{{ EA = Rn; }});
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0x9: ldrsh_ul({{ Rd = Mem.sh;
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Rn = Rn - Rm; }},
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{{ EA = Rn; }});
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0xd: ldrsh_uil({{ Rd = Mem.sh;
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Rn = Rn - hilo; }},
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{{ EA = Rn; }});
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0x11: ldrsh_pl({{ Rd = Mem.sh; }},
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{{ EA = Rn + Rm; }});
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0x13: ldrsh_pwl({{ Rd = Mem.sh;
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Rn = Rn + Rm; }},
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{{ EA = Rn + Rm; }});
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0x15: ldrsh_pil({{ Rd = Mem.sh; }},
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{{ EA = Rn + hilo; }});
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0x17: ldrsh_piwl({{ Rd = Mem.sh;
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Rn = Rn + hilo; }},
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{{ EA = Rn + hilo; }});
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0x19: ldrsh_pul({{ Rd = Mem.sh; }},
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{{ EA = Rn - Rm; }});
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0x1b: ldrsh_puwl({{ Rd = Mem.sh;
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Rn = Rn - Rm; }},
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{{ EA = Rn - Rm; }});
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0x1d: ldrsh_puil({{ Rd = Mem.sh; }},
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{{ EA = Rn - hilo; }});
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0x1f: ldrsh_puiwl({{ Rd = Mem.sh;
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Rn = Rn - hilo; }},
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{{ EA = Rn - hilo; }});
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}
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}
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}
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0: decode IS_MISC {
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0: decode OPCODE {
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0x0: and({{ Rd = resTemp = Rn & op2; }});
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0x1: eor({{ Rd = resTemp = Rn ^ op2; }});
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0x2: sub({{ Rd = resTemp = Rn - op2; }}, sub);
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0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, rsb);
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0x4: add({{ Rd = resTemp = Rn + op2; }}, add);
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0x5: adc({{ Rd = resTemp = Rn + op2 + Cpsr<29:>; }}, add);
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0x6: sbc({{ Rd = resTemp = Rn - op2 - !Cpsr<29:>; }}, sub);
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0x7: rsc({{ Rd = resTemp = op2 - Rn - !Cpsr<29:>; }}, rsb);
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0x8: tst({{ resTemp = Rn & op2; }});
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0x9: teq({{ resTemp = Rn ^ op2; }});
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0xa: cmp({{ resTemp = Rn - op2; }}, sub);
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0xb: cmn({{ resTemp = Rn + op2; }}, add);
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0xc: orr({{ Rd = resTemp = Rn | op2; }});
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0xd: mov({{ Rd = resTemp = op2; }});
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0xe: bic({{ Rd = resTemp = Rn & ~op2; }});
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0xf: mvn({{ Rd = resTemp = ~op2; }});
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}
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1: decode MISC_OPCODE {
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0x0: decode OPCODE {
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0x8: WarnUnimpl::mrs_cpsr();
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0x9: WarnUnimpl::msr_cpsr();
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0xa: WarnUnimpl::mrs_spsr();
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0xb: WarnUnimpl::msr_spsr();
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}
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0x1: decode OPCODE {
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0x9: BranchExchange::bx({{ }});
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0xb: PredOp::clz({{
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unsigned lsb = findLsbSet(Rm);
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Rd = (lsb > 31) ? 32 : lsb;
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}});
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}
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0x2: decode OPCODE {
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0x9: WarnUnimpl::bxj();
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}
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0x3: decode OPCODE {
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0x9: BranchExchange::blx({{ }}, Link);
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}
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0x5: decode OPCODE {
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0x8: WarnUnimpl::qadd();
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0x9: WarnUnimpl::qsub();
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0xa: WarnUnimpl::qdadd();
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0xb: WarnUnimpl::qdsub();
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}
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0x8: decode OPCODE {
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0x8: WarnUnimpl::smlabb();
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0x9: WarnUnimpl::smlalbb();
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0xa: WarnUnimpl::smlawb();
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0xb: WarnUnimpl::smulbb();
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}
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0xa: decode OPCODE {
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0x8: WarnUnimpl::smlatb();
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0x9: WarnUnimpl::smulwb();
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0xa: WarnUnimpl::smlaltb();
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0xb: WarnUnimpl::smultb();
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}
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0xc: decode OPCODE {
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0x8: WarnUnimpl::smlabt();
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0x9: WarnUnimpl::smlawt();
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0xa: WarnUnimpl::smlalbt();
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0xb: WarnUnimpl::smulbt();
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}
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0xe: decode OPCODE {
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0x8: WarnUnimpl::smlatt();
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0x9: WarnUnimpl::smulwt();
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0xa: WarnUnimpl::smlaltt();
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0xb: WarnUnimpl::smultt();
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}
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}
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}
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}
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0x1: decode IS_MISC {
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0: decode OPCODE {
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format DataImmOp {
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0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }});
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0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }});
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0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }}, sub);
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0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }}, rsb);
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0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }}, add);
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0x5: adci({{ Rd = resTemp = Rn + rotated_imm + Cpsr<29:>; }}, add);
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0x6: sbci({{ Rd = resTemp = Rn -rotated_imm - !Cpsr<29:>; }}, sub);
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0x7: rsci({{ Rd = resTemp = rotated_imm - Rn - !Cpsr<29:>;}}, rsb);
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0x8: tsti({{ resTemp = Rn & rotated_imm; }});
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0x9: teqi({{ resTemp = Rn ^ rotated_imm; }});
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0xa: cmpi({{ resTemp = Rn - rotated_imm; }}, sub);
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0xb: cmni({{ resTemp = Rn + rotated_imm; }}, add);
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0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }});
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0xd: movi({{ Rd = resTemp = rotated_imm; }});
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0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }});
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0xf: mvni({{ Rd = resTemp = ~rotated_imm; }});
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}
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}
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1: decode OPCODE {
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// The following two instructions aren't supposed to be defined
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0x8: WarnUnimpl::undefined_instruction();
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0x9: WarnUnimpl::undefined_instruction();
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0xa: WarnUnimpl::mrs_i_cpsr();
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0xb: WarnUnimpl::mrs_i_spsr();
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}
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}
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0x2: decode PUBWL {
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// CAREFUL:
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// Can always do EA + disp, since we negate disp using the UP flag
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// Post-indexed variants
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0x00,0x08: ArmStoreMemory::str_({{ Mem = Rd;
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Rn = Rn + disp; }},
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{{ EA = Rn; }});
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0x01,0x09: ArmLoadMemory::ldr_l({{ Rn = Rn + disp;
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Rd = Mem; }},
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{{ EA = Rn; }});
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0x04,0x0c: ArmStoreMemory::strb_b({{ Mem.ub = Rd.ub;
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Rn = Rn + disp; }},
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{{ EA = Rn; }});
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0x05,0x0d: ArmLoadMemory::ldrb_bl({{ Rn = Rn + disp;
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Rd.ub = Mem.ub; }},
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{{ EA = Rn; }});
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// Pre-indexed variants
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0x10,0x18: ArmStoreMemory::str_p({{ Mem = Rd; }});
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0x11,0x19: ArmLoadMemory::ldr_pl({{ Rd = Mem; }});
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0x12,0x1a: ArmStoreMemory::str_pw({{ Mem = Rd;
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Rn = Rn + disp; }});
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0x13,0x1b: ArmLoadMemory::ldr_pwl({{ Rn = Rn + disp;
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Rd = Mem; }});
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0x14,0x1c: ArmStoreMemory::strb_pb({{ Mem.ub = Rd.ub; }});
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0x15,0x1d: ArmLoadMemory::ldrb_pbl({{ Rd.ub = Mem.ub; }});
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0x16,0x1e: ArmStoreMemory::strb_pbw({{ Mem.ub = Rd.ub;
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Rn = Rn + disp; }});
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0x17,0x1f: ArmLoadMemory::ldrb_pbwl({{ Rn = Rn + disp;
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Rd.ub = Mem.ub; }});
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}
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0x3: decode OPCODE_4 {
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0: decode PUBWL {
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0x00,0x08: ArmStoreMemory::strr_({{
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Mem = Rd;
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Rn = Rn + Rm_Imm; }},
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{{ EA = Rn; }});
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0x01,0x09: ArmLoadMemory::ldrr_l({{
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Rd = Mem;
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Rn = Rn + Rm_Imm; }},
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{{ EA = Rn; }});
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0x04,0x0c: ArmStoreMemory::strr_b({{
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Mem.ub = Rd.ub;
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Rn = Rn + Rm_Imm; }},
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{{ EA = Rn; }});
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0x05,0x0d: ArmLoadMemory::ldrr_bl({{
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Rd.ub = Mem.ub;
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Rn = Rn + Rm_Imm; }},
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{{ EA = Rn; }});
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0x10,0x18: ArmStoreMemory::strr_p({{
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Mem = Rd; }},
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{{ EA = Rn + Rm_Imm; }});
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0x11,0x19: ArmLoadMemory::ldrr_pl({{
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Rd = Mem; }},
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{{ EA = Rn + Rm_Imm; }});
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0x12,0x1a: ArmStoreMemory::strr_pw({{
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Mem = Rd;
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Rn = Rn + Rm_Imm; }},
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{{ EA = Rn + Rm_Imm; }});
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0x13,0x1b: ArmLoadMemory::ldrr_pwl({{
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Rd = Mem;
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Rn = Rn + Rm_Imm; }},
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{{ EA = Rn + Rm_Imm; }});
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0x14,0x1c: ArmStoreMemory::strr_pb({{
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Mem.ub = Rd.ub; }},
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{{ EA = Rn + Rm_Imm; }});
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0x15,0x1d: ArmLoadMemory::ldrr_pbl({{
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Rd.ub = Mem.ub; }},
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{{ EA = Rn + Rm_Imm; }});
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0x16,0x1e: ArmStoreMemory::strr_pbw({{
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Mem.ub = Rd.ub;
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Rn = Rn + Rm_Imm; }},
|
|
{{ EA = Rn + Rm_Imm; }});
|
|
0x17,0x1f: ArmLoadMemory::ldrr_pbwl({{
|
|
Rd.ub = Mem.ub;
|
|
Rn = Rn + Rm_Imm; }},
|
|
{{ EA = Rn + Rm_Imm; }});
|
|
}
|
|
1: decode MEDIA_OPCODE {
|
|
0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions();
|
|
0x8: decode MISC_OPCODE {
|
|
0x1, 0x9: WarnUnimpl::pkhbt();
|
|
0x7: WarnUnimpl::sxtab16();
|
|
0xb: WarnUnimpl::sel();
|
|
0x5, 0xd: WarnUnimpl::pkhtb();
|
|
0x3: WarnUnimpl::sign_zero_extend_add();
|
|
}
|
|
0xa, 0xb: decode SHIFT {
|
|
0x0, 0x2: WarnUnimpl::ssat();
|
|
0x1: WarnUnimpl::ssat16();
|
|
}
|
|
0xe, 0xf: decode SHIFT {
|
|
0x0, 0x2: WarnUnimpl::usat();
|
|
0x1: WarnUnimpl::usat16();
|
|
}
|
|
0x10: decode RN {
|
|
0xf: decode MISC_OPCODE {
|
|
0x1: WarnUnimpl::smuad();
|
|
0x3: WarnUnimpl::smuadx();
|
|
0x5: WarnUnimpl::smusd();
|
|
0x7: WarnUnimpl::smusdx();
|
|
}
|
|
default: decode MISC_OPCODE {
|
|
0x1: WarnUnimpl::smlad();
|
|
0x3: WarnUnimpl::smladx();
|
|
0x5: WarnUnimpl::smlsd();
|
|
0x7: WarnUnimpl::smlsdx();
|
|
}
|
|
}
|
|
0x14: decode MISC_OPCODE {
|
|
0x1: WarnUnimpl::smlald();
|
|
0x3: WarnUnimpl::smlaldx();
|
|
0x5: WarnUnimpl::smlsld();
|
|
0x7: WarnUnimpl::smlsldx();
|
|
}
|
|
0x15: decode RN {
|
|
0xf: decode MISC_OPCODE {
|
|
0x1: WarnUnimpl::smmul();
|
|
0x3: WarnUnimpl::smmulr();
|
|
}
|
|
default: decode MISC_OPCODE {
|
|
0x1: WarnUnimpl::smmla();
|
|
0x3: WarnUnimpl::smmlar();
|
|
0xd: WarnUnimpl::smmls();
|
|
0xf: WarnUnimpl::smmlsr();
|
|
}
|
|
}
|
|
0x18: decode RN {
|
|
0xf: WarnUnimpl::usada8();
|
|
default: WarnUnimpl::usad8();
|
|
}
|
|
}
|
|
}
|
|
0x4: decode PUSWL {
|
|
// Right now we only handle cases when S (PSRUSER) is not set
|
|
default: ArmMacroStore::ldmstm({{ }});
|
|
}
|
|
0x5: decode OPCODE_24 {
|
|
// Branch (and Link) Instructions
|
|
0: Branch::b({{ }});
|
|
1: Branch::bl({{ }}, Link);
|
|
}
|
|
0x6: decode CPNUM {
|
|
0x1: decode PUNWL {
|
|
0x02,0x0a: decode OPCODE_15 {
|
|
0: ArmStoreMemory::stfs_({{ Mem.sf = Fd.sf;
|
|
Rn = Rn + disp8; }},
|
|
{{ EA = Rn; }});
|
|
1: ArmMacroFPAOp::stfd_({{ }});
|
|
}
|
|
0x03,0x0b: decode OPCODE_15 {
|
|
0: ArmLoadMemory::ldfs_({{ Fd.sf = Mem.sf;
|
|
Rn = Rn + disp8; }},
|
|
{{ EA = Rn; }});
|
|
1: ArmMacroFPAOp::ldfd_({{ }});
|
|
}
|
|
0x06,0x0e: decode OPCODE_15 {
|
|
0: ArmMacroFPAOp::stfe_nw({{ }});
|
|
}
|
|
0x07,0x0f: decode OPCODE_15 {
|
|
0: ArmMacroFPAOp::ldfe_nw({{ }});
|
|
}
|
|
0x10,0x18: decode OPCODE_15 {
|
|
0: ArmStoreMemory::stfs_p({{ Mem.sf = Fd.sf; }},
|
|
{{ EA = Rn + disp8; }});
|
|
1: ArmMacroFPAOp::stfd_p({{ }});
|
|
}
|
|
0x11,0x19: decode OPCODE_15 {
|
|
0: ArmLoadMemory::ldfs_p({{ Fd.sf = Mem.sf; }},
|
|
{{ EA = Rn + disp8; }});
|
|
1: ArmMacroFPAOp::ldfd_p({{ }});
|
|
}
|
|
0x12,0x1a: decode OPCODE_15 {
|
|
0: ArmStoreMemory::stfs_pw({{ Mem.sf = Fd.sf;
|
|
Rn = Rn + disp8; }},
|
|
{{ EA = Rn + disp8; }});
|
|
1: ArmMacroFPAOp::stfd_pw({{ }});
|
|
}
|
|
0x13,0x1b: decode OPCODE_15 {
|
|
0: ArmLoadMemory::ldfs_pw({{ Fd.sf = Mem.sf;
|
|
Rn = Rn + disp8; }},
|
|
{{ EA = Rn + disp8; }});
|
|
1: ArmMacroFPAOp::ldfd_pw({{ }});
|
|
}
|
|
0x14,0x1c: decode OPCODE_15 {
|
|
0: ArmMacroFPAOp::stfe_pn({{ }});
|
|
}
|
|
0x15,0x1d: decode OPCODE_15 {
|
|
0: ArmMacroFPAOp::ldfe_pn({{ }});
|
|
}
|
|
0x16,0x1e: decode OPCODE_15 {
|
|
0: ArmMacroFPAOp::stfe_pnw({{ }});
|
|
}
|
|
0x17,0x1f: decode OPCODE_15 {
|
|
0: ArmMacroFPAOp::ldfe_pnw({{ }});
|
|
}
|
|
}
|
|
0x2: decode PUNWL {
|
|
// could really just decode as a single instruction
|
|
0x00,0x04,0x08,0x0c: ArmMacroFMOp::sfm_({{ }});
|
|
0x01,0x05,0x09,0x0d: ArmMacroFMOp::lfm_({{ }});
|
|
0x02,0x06,0x0a,0x0e: ArmMacroFMOp::sfm_w({{ }});
|
|
0x03,0x07,0x0b,0x0f: ArmMacroFMOp::lfm_w({{ }});
|
|
0x10,0x14,0x18,0x1c: ArmMacroFMOp::sfm_p({{ }});
|
|
0x11,0x15,0x19,0x1d: ArmMacroFMOp::lfm_p({{ }});
|
|
0x12,0x16,0x1a,0x1e: ArmMacroFMOp::sfm_pw({{ }});
|
|
0x13,0x17,0x1b,0x1f: ArmMacroFMOp::lfm_pw({{ }});
|
|
}
|
|
}
|
|
0x7: decode OPCODE_24 {
|
|
0: decode CPNUM {
|
|
// Coprocessor Instructions
|
|
0x1: decode OPCODE_4 {
|
|
format FloatOp {
|
|
// Basic FPA Instructions
|
|
0: decode OPCODE_23_20 {
|
|
0x0: decode OPCODE_15 {
|
|
0: adf({{ Fd.sf = Fn.sf + Fm.sf; }});
|
|
1: mvf({{ Fd.sf = Fm.sf; }});
|
|
}
|
|
0x1: decode OPCODE_15 {
|
|
0: muf({{ Fd.sf = Fn.sf * Fm.sf; }});
|
|
1: mnf({{ Fd.sf = -Fm.sf; }});
|
|
}
|
|
0x2: decode OPCODE_15 {
|
|
0: suf({{ Fd.sf = Fn.sf - Fm.sf; }});
|
|
1: abs({{ Fd.sf = fabs(Fm.sf); }});
|
|
}
|
|
0x3: decode OPCODE_15 {
|
|
0: rsf({{ Fd.sf = Fm.sf - Fn.sf; }});
|
|
1: rnd({{ Fd.sf = rint(Fm.sf); }});
|
|
}
|
|
0x4: decode OPCODE_15 {
|
|
0: dvf({{ Fd.sf = Fn.sf / Fm.sf; }});
|
|
1: sqt({{ Fd.sf = sqrt(Fm.sf); }});
|
|
}
|
|
0x5: decode OPCODE_15 {
|
|
0: rdf({{ Fd.sf = Fm.sf / Fn.sf; }});
|
|
1: log({{ Fd.sf = log10(Fm.sf); }});
|
|
}
|
|
0x6: decode OPCODE_15 {
|
|
0: pow({{ Fd.sf = pow(Fm.sf, Fn.sf); }});
|
|
1: lgn({{ Fd.sf = log(Fm.sf); }});
|
|
}
|
|
0x7: decode OPCODE_15 {
|
|
0: rpw({{ Fd.sf = pow(Fn.sf, Fm.sf); }});
|
|
1: exp({{ Fd.sf = exp(Fm.sf); }});
|
|
}
|
|
0x8: decode OPCODE_15 {
|
|
0: rmf({{ Fd.sf = drem(Fn.sf, Fm.sf); }});
|
|
1: sin({{ Fd.sf = sin(Fm.sf); }});
|
|
}
|
|
0x9: decode OPCODE_15 {
|
|
0: fml({{ Fd.sf = Fn.sf * Fm.sf; }});
|
|
1: cos({{ Fd.sf = cos(Fm.sf); }});
|
|
}
|
|
0xa: decode OPCODE_15 {
|
|
0: fdv({{ Fd.sf = Fn.sf / Fm.sf; }});
|
|
1: tan({{ Fd.sf = tan(Fm.sf); }});
|
|
}
|
|
0xb: decode OPCODE_15 {
|
|
0: frd({{ Fd.sf = Fm.sf / Fn.sf; }});
|
|
1: asn({{ Fd.sf = asin(Fm.sf); }});
|
|
}
|
|
0xc: decode OPCODE_15 {
|
|
0: pol({{ Fd.sf = atan2(Fn.sf, Fm.sf); }});
|
|
1: acs({{ Fd.sf = acos(Fm.sf); }});
|
|
}
|
|
0xd: decode OPCODE_15 {
|
|
1: atn({{ Fd.sf = atan(Fm.sf); }});
|
|
}
|
|
0xe: decode OPCODE_15 {
|
|
// Unnormalised Round
|
|
1: FailUnimpl::urd();
|
|
}
|
|
0xf: decode OPCODE_15 {
|
|
// Normalise
|
|
1: FailUnimpl::nrm();
|
|
}
|
|
}
|
|
1: decode OPCODE_15_12 {
|
|
0xf: decode OPCODE_23_21 {
|
|
format FloatCmp {
|
|
0x4: cmf({{ Fn.df }}, {{ Fm.df }});
|
|
0x5: cnf({{ Fn.df }}, {{ -Fm.df }});
|
|
0x6: cmfe({{ Fn.df }}, {{ Fm.df}});
|
|
0x7: cnfe({{ Fn.df }}, {{ -Fm.df}});
|
|
}
|
|
}
|
|
default: decode OPCODE_23_20 {
|
|
0x0: decode OPCODE_7 {
|
|
0: flts({{ Fn.sf = (float) Rd.sw; }});
|
|
1: fltd({{ Fn.df = (double) Rd.sw; }});
|
|
}
|
|
0x1: decode OPCODE_7 {
|
|
0: fixs({{ Rd = (uint32_t) Fm.sf; }});
|
|
1: fixd({{ Rd = (uint32_t) Fm.df; }});
|
|
}
|
|
0x2: wfs({{ Fpsr = Rd; }});
|
|
0x3: rfs({{ Rd = Fpsr; }});
|
|
0x4: FailUnimpl::wfc();
|
|
0x5: FailUnimpl::rfc();
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
format PredOp {
|
|
// ARM System Call (SoftWare Interrupt)
|
|
1: swi({{ if (testPredicate(Cpsr, condCode))
|
|
{
|
|
xc->syscall(IMMED_23_0);
|
|
}
|
|
}});
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|