88 lines
2.7 KiB
C++
88 lines
2.7 KiB
C++
// -*- mode:c++ -*-
|
|
|
|
// Copyright (c) 2007-2008 The Florida State University
|
|
// All rights reserved.
|
|
//
|
|
// Redistribution and use in source and binary forms, with or without
|
|
// modification, are permitted provided that the following conditions are
|
|
// met: redistributions of source code must retain the above copyright
|
|
// notice, this list of conditions and the following disclaimer;
|
|
// redistributions in binary form must reproduce the above copyright
|
|
// notice, this list of conditions and the following disclaimer in the
|
|
// documentation and/or other materials provided with the distribution;
|
|
// neither the name of the copyright holders nor the names of its
|
|
// contributors may be used to endorse or promote products derived from
|
|
// this software without specific prior written permission.
|
|
//
|
|
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
//
|
|
// Authors: Stephen Hines
|
|
|
|
////////////////////////////////////////////////////////////////////
|
|
//
|
|
// Output include file directives.
|
|
//
|
|
|
|
output header {{
|
|
#include <sstream>
|
|
#include <iostream>
|
|
#include <iomanip>
|
|
|
|
#include "arch/arm/insts/branch.hh"
|
|
#include "arch/arm/insts/macromem.hh"
|
|
#include "arch/arm/insts/mem.hh"
|
|
#include "arch/arm/insts/pred_inst.hh"
|
|
#include "arch/arm/insts/static_inst.hh"
|
|
#include "arch/arm/isa_traits.hh"
|
|
#include "cpu/static_inst.hh"
|
|
#include "mem/packet.hh"
|
|
}};
|
|
|
|
output decoder {{
|
|
#include <cmath>
|
|
#if defined(linux)
|
|
#include <fenv.h>
|
|
#endif
|
|
|
|
#include "arch/arm/faults.hh"
|
|
#include "arch/arm/isa_traits.hh"
|
|
#include "arch/arm/utility.hh"
|
|
#include "base/cprintf.hh"
|
|
#include "base/loader/symtab.hh"
|
|
#include "cpu/thread_context.hh"
|
|
|
|
using namespace ArmISA;
|
|
using std::isnan;
|
|
}};
|
|
|
|
output exec {{
|
|
#include "arch/arm/faults.hh"
|
|
#include "arch/arm/isa_traits.hh"
|
|
#include "arch/arm/utility.hh"
|
|
#include "base/condcodes.hh"
|
|
|
|
#include <cmath>
|
|
#if defined(linux)
|
|
#include <fenv.h>
|
|
#endif
|
|
|
|
#include "cpu/base.hh"
|
|
#include "cpu/exetrace.hh"
|
|
#include "mem/packet.hh"
|
|
#include "mem/packet_access.hh"
|
|
#include "sim/sim_exit.hh"
|
|
|
|
using namespace ArmISA;
|
|
using std::isnan;
|
|
}};
|
|
|