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Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its

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python type of a latency.  In addition, the multiple definitions of profile in the different cpu models caused
problems for intialization of the interval value. If a child class's profile value was defined, the parent
BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the
multiple redifitions of profile in the child CPU classes.
This commit is contained in:
Richard Strong 2008-08-18 10:50:58 -07:00
parent 6248e12704
commit 8d018aef0f
8 changed files with 3 additions and 15 deletions
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2
src/cpu/CheckerCPU.py
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@ -40,5 +40,3 @@ class CheckerCPU(BaseCPU):
"If a load result is incorrect, only print a warning and do not exit")
function_trace = Param.Bool(False, "Enable function trace")
function_trace_start = Param.Tick(0, "Cycle to start function trace")
if build_env['FULL_SYSTEM']:
profile = Param.Latency('0ns', "trace the kernel stack")

2
src/cpu/base.cc
View file

@ -357,7 +357,7 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
#if FULL_SYSTEM
BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, int _interval)
BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
: Event(&mainEventQueue), cpu(_cpu), interval(_interval)
{ }

4
src/cpu/base.hh
View file

@ -122,10 +122,10 @@ class BaseCPU : public MemObject
{
private:
BaseCPU *cpu;
int interval;
Tick interval;
public:
ProfileEvent(BaseCPU *cpu, int interval);
ProfileEvent(BaseCPU *cpu, Tick interval);
void process();
};
ProfileEvent *profileEvent;

2
src/cpu/o3/O3Checker.py
View file

@ -39,5 +39,3 @@ class O3Checker(BaseCPU):
"If a load result is incorrect, only print a warning and do not exit")
function_trace = Param.Bool(False, "Enable function trace")
function_trace_start = Param.Tick(0, "Cycle to start function trace")
if build_env['FULL_SYSTEM']:
profile = Param.Latency('0ns', "trace the kernel stack")

2
src/cpu/ozone/OzoneCPU.py
View file

@ -40,8 +40,6 @@ class DerivOzoneCPU(BaseCPU):
if build_env['USE_CHECKER']:
checker = Param.BaseCPU("Checker CPU")
if build_env['FULL_SYSTEM']:
profile = Param.Latency('0ns', "trace the kernel stack")
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")

2
src/cpu/ozone/OzoneChecker.py
View file

@ -39,5 +39,3 @@ class OzoneChecker(BaseCPU):
"If a load result is incorrect, only print a warning and do not exit")
function_trace = Param.Bool(False, "Enable function trace")
function_trace_start = Param.Tick(0, "Cycle to start function trace")
if build_env['FULL_SYSTEM']:
profile = Param.Latency('0ns', "trace the kernel stack")

2
src/cpu/simple/AtomicSimpleCPU.py
View file

@ -37,8 +37,6 @@ class AtomicSimpleCPU(BaseSimpleCPU):
simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
function_trace = Param.Bool(False, "Enable function trace")
function_trace_start = Param.Tick(0, "Cycle to start function trace")
if build_env['FULL_SYSTEM']:
profile = Param.Latency('0ns', "trace the kernel stack")
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
physmem_port = Port("Physical Memory Port")

2
src/cpu/simple/TimingSimpleCPU.py
View file

@ -34,8 +34,6 @@ class TimingSimpleCPU(BaseSimpleCPU):
type = 'TimingSimpleCPU'
function_trace = Param.Bool(False, "Enable function trace")
function_trace_start = Param.Tick(0, "Cycle to start function trace")
if build_env['FULL_SYSTEM']:
profile = Param.Latency('0ns', "trace the kernel stack")
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
_mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']