ruby: MESI_CMP_directory updated to the new config system
This commit is contained in:
Brad Beckmann
parent
3e286d825d
commit
faa76fc248
6 changed files with 215 additions and 105 deletions
151
configs/ruby/MESI_CMP_directory.py
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151
configs/ruby/MESI_CMP_directory.py
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@ -0,0 +1,151 @@
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Brad Beckmann
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import math
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath
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#
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# Note: the L1 Cache latency is only used by the sequencer on fast path hits
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#
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class L1Cache(RubyCache):
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latency = 3
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#
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# Note: the L2 Cache latency is not currently used
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#
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class L2Cache(RubyCache):
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latency = 15
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def create_system(options, phys_mem, piobus, dma_devices):
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if buildEnv['PROTOCOL'] != 'MESI_CMP_directory':
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panic("This script requires the MESI_CMP_directory protocol to be built.")
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cpu_sequencers = []
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#
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# The ruby network creation expects the list of nodes in the system to be
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# consistent with the NetDest list. Therefore the l1 controller nodes must be
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# listed before the directory nodes and directory nodes before dma nodes, etc.
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#
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l1_cntrl_nodes = []
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l2_cntrl_nodes = []
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dir_cntrl_nodes = []
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dma_cntrl_nodes = []
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#
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# Must create the individual controllers before the network to ensure the
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# controller constructors are called before the network constructor
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#
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for i in xrange(options.num_cpus):
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#
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# First create the Ruby objects associated with this cpu
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#
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l1i_cache = L1Cache(size = options.l1i_size,
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assoc = options.l1i_assoc)
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l1d_cache = L1Cache(size = options.l1d_size,
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assoc = options.l1d_assoc)
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cpu_seq = RubySequencer(icache = l1i_cache,
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dcache = l1d_cache,
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physMemPort = phys_mem.port,
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physmem = phys_mem)
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if piobus != None:
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cpu_seq.pio_port = piobus.port
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l1_cntrl = L1Cache_Controller(version = i,
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sequencer = cpu_seq,
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L1IcacheMemory = l1i_cache,
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L1DcacheMemory = l1d_cache,
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l2_select_num_bits = \
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math.log(options.num_l2caches, 2))
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#
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# Add controllers and sequencers to the appropriate lists
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#
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cpu_sequencers.append(cpu_seq)
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l1_cntrl_nodes.append(l1_cntrl)
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for i in xrange(options.num_l2caches):
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#
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# First create the Ruby objects associated with this cpu
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#
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l2_cache = L2Cache(size = options.l2_size,
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assoc = options.l2_assoc)
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l2_cntrl = L2Cache_Controller(version = i,
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L2cacheMemory = l2_cache)
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l2_cntrl_nodes.append(l2_cntrl)
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phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
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mem_module_size = phys_mem_size / options.num_dirs
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for i in xrange(options.num_dirs):
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#
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# Create the Ruby objects associated with the directory controller
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#
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mem_cntrl = RubyMemoryControl(version = i)
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dir_size = MemorySize('0B')
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dir_size.value = mem_module_size
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dir_cntrl = Directory_Controller(version = i,
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directory = \
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RubyDirectoryMemory(version = i,
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size = dir_size),
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memBuffer = mem_cntrl)
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dir_cntrl_nodes.append(dir_cntrl)
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for i, dma_device in enumerate(dma_devices):
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#
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# Create the Ruby objects associated with the dma controller
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#
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dma_seq = DMASequencer(version = i,
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physMemPort = phys_mem.port,
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physmem = phys_mem)
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dma_cntrl = DMA_Controller(version = i,
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dma_sequencer = dma_seq)
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dma_cntrl.dma_sequencer.port = dma_device.dma
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dma_cntrl_nodes.append(dma_cntrl)
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all_cntrls = l1_cntrl_nodes + \
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l2_cntrl_nodes + \
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dir_cntrl_nodes + \
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dma_cntrl_nodes
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return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
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@ -33,6 +33,7 @@ from m5.defines import buildEnv
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from m5.util import addToPath
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import MOESI_hammer
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import MESI_CMP_directory
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import MOESI_CMP_directory
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import MI_example
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import MOESI_CMP_token
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@ -47,6 +48,12 @@ def create_system(options, physmem, piobus = None, dma_devices = []):
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physmem, \
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piobus, \
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dma_devices)
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elif protocol == "MESI_CMP_directory":
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(cpu_sequencers, dir_cntrls, all_cntrls) = \
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MESI_CMP_directory.create_system(options, \
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physmem, \
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piobus, \
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dma_devices)
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elif protocol == "MOESI_CMP_directory":
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(cpu_sequencers, dir_cntrls, all_cntrls) = \
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MOESI_CMP_directory.create_system(options, \
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@ -28,11 +28,13 @@
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*/
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machine(L1Cache, "MSI Directory L1 Cache CMP")
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: int l1_request_latency,
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int l1_response_latency,
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int to_l2_latency,
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int l2_select_low_bit,
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int l2_select_num_bits
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: Sequencer * sequencer,
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CacheMemory * L1IcacheMemory,
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CacheMemory * L1DcacheMemory,
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int l2_select_num_bits,
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int l1_request_latency = 2,
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int l1_response_latency = 2,
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int to_l2_latency = 1
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{
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@ -118,16 +120,6 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
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int pendingAcks, default="0", desc="number of pending acks";
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}
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external_type(CacheMemory) {
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bool cacheAvail(Address);
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Address cacheProbe(Address);
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void allocate(Address, Entry);
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void deallocate(Address);
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Entry lookup(Address);
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void changePermission(Address, AccessPermission);
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bool isTagPresent(Address);
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}
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external_type(TBETable) {
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TBE lookup(Address);
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void allocate(Address);
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@ -137,30 +129,17 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
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TBETable L1_TBEs, template_hack="<L1Cache_TBE>";
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// CacheMemory L1IcacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1I"', abstract_chip_ptr="true";
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// CacheMemory L1DcacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1D"', abstract_chip_ptr="true";
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CacheMemory L1IcacheMemory, factory='RubySystem::getCache(m_cfg["icache"])';
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CacheMemory L1DcacheMemory, factory='RubySystem::getCache(m_cfg["dcache"])';
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// MessageBuffer mandatoryQueue, ordered="false", rank="100", abstract_chip_ptr="true";
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// Sequencer sequencer, abstract_chip_ptr="true", constructor_hack="i";
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MessageBuffer mandatoryQueue, ordered="false";
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Sequencer sequencer, factory='RubySystem::getSequencer(m_cfg["sequencer"])';
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int cache_state_to_int(State state);
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int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
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// inclusive cache returns L1 entries only
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Entry getL1CacheEntry(Address addr), return_by_ref="yes" {
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if (L1DcacheMemory.isTagPresent(addr)) {
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return L1DcacheMemory[addr];
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return static_cast(Entry, L1DcacheMemory[addr]);
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} else {
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return L1IcacheMemory[addr];
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return static_cast(Entry, L1IcacheMemory[addr]);
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}
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}
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@ -33,9 +33,10 @@
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*/
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machine(L2Cache, "MESI Directory L2 Cache CMP")
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: int l2_request_latency,
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int l2_response_latency,
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int to_l1_latency
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: CacheMemory * L2cacheMemory,
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int l2_request_latency = 2,
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int l2_response_latency = 2,
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int to_l1_latency = 1
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{
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// L2 BANK QUEUES
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@ -145,17 +146,6 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
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int pendingAcks, desc="number of pending acks for invalidates during writeback";
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}
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external_type(CacheMemory) {
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bool cacheAvail(Address);
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Address cacheProbe(Address);
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void allocate(Address, Entry);
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void deallocate(Address);
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Entry lookup(Address);
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void changePermission(Address, AccessPermission);
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bool isTagPresent(Address);
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void setMRU(Address);
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}
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external_type(TBETable) {
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TBE lookup(Address);
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void allocate(Address);
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@ -165,14 +155,9 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
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TBETable L2_TBEs, template_hack="<L2Cache_TBE>";
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// CacheMemory L2cacheMemory, template_hack="<L2Cache_Entry>", constructor_hack='L2_CACHE_NUM_SETS_BITS,L2_CACHE_ASSOC,MachineType_L2Cache,int_to_string(i)';
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CacheMemory L2cacheMemory, factory='RubySystem::getCache(m_cfg["cache"])';
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// inclusive cache, returns L2 entries only
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Entry getL2CacheEntry(Address addr), return_by_ref="yes" {
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return L2cacheMemory[addr];
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return static_cast(Entry, L2cacheMemory[addr]);
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}
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void changeL2Permission(Address addr, AccessPermission permission) {
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@ -190,13 +175,13 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
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}
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bool isOneSharerLeft(Address addr, MachineID requestor) {
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assert(L2cacheMemory[addr].Sharers.isElement(requestor));
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return (L2cacheMemory[addr].Sharers.count() == 1);
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assert(getL2CacheEntry(addr).Sharers.isElement(requestor));
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return (getL2CacheEntry(addr).Sharers.count() == 1);
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}
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bool isSharer(Address addr, MachineID requestor) {
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if (L2cacheMemory.isTagPresent(addr)) {
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return L2cacheMemory[addr].Sharers.isElement(requestor);
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return getL2CacheEntry(addr).Sharers.isElement(requestor);
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} else {
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return false;
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}
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@ -206,7 +191,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
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//DEBUG_EXPR(machineID);
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//DEBUG_EXPR(requestor);
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//DEBUG_EXPR(addr);
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L2cacheMemory[addr].Sharers.add(requestor);
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getL2CacheEntry(addr).Sharers.add(requestor);
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}
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State getState(Address addr) {
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@ -361,7 +346,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
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trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Address, in_msg.Requestor), in_msg.Address);
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} else {
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// No room in the L2, so we need to make room before handling the request
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if (L2cacheMemory[ L2cacheMemory.cacheProbe(in_msg.Address) ].Dirty ) {
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if (getL2CacheEntry( L2cacheMemory.cacheProbe(in_msg.Address) ).Dirty ) {
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trigger(Event:L2_Replacement, L2cacheMemory.cacheProbe(in_msg.Address));
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} else {
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trigger(Event:L2_Replacement_clean, L2cacheMemory.cacheProbe(in_msg.Address));
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@ -393,7 +378,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
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out_msg.Address := address;
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out_msg.Type := in_msg.Type;
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out_msg.Requestor := in_msg.Requestor;
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out_msg.Destination.add(L2cacheMemory[address].Exclusive);
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out_msg.Destination.add(getL2CacheEntry(address).Exclusive);
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out_msg.MessageSize := MessageSizeType:Request_Control;
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}
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}
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@ -537,7 +522,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
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out_msg.Address := address;
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out_msg.Type := CoherenceRequestType:INV;
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out_msg.Requestor := machineID;
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out_msg.Destination := L2cacheMemory[address].Sharers;
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out_msg.Destination := getL2CacheEntry(address).Sharers;
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out_msg.MessageSize := MessageSizeType:Request_Control;
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}
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}
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@ -548,7 +533,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
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out_msg.Address := address;
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out_msg.Type := CoherenceRequestType:INV;
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out_msg.Requestor := in_msg.Requestor;
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out_msg.Destination := L2cacheMemory[address].Sharers;
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out_msg.Destination := getL2CacheEntry(address).Sharers;
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out_msg.MessageSize := MessageSizeType:Request_Control;
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}
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}
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@ -561,7 +546,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
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out_msg.Address := address;
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out_msg.Type := CoherenceRequestType:INV;
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out_msg.Requestor := in_msg.Requestor;
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out_msg.Destination := L2cacheMemory[address].Sharers;
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out_msg.Destination := getL2CacheEntry(address).Sharers;
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out_msg.Destination.remove(in_msg.Requestor);
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out_msg.MessageSize := MessageSizeType:Request_Control;
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}
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@ -713,28 +698,28 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
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action(kk_removeRequestSharer, "\k", desc="Remove L1 Request sharer from list") {
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peek(L1RequestIntraChipL2Network_in, RequestMsg) {
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L2cacheMemory[address].Sharers.remove(in_msg.Requestor);
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getL2CacheEntry(address).Sharers.remove(in_msg.Requestor);
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}
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}
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action(ll_clearSharers, "\l", desc="Remove all L1 sharers from list") {
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peek(L1RequestIntraChipL2Network_in, RequestMsg) {
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L2cacheMemory[address].Sharers.clear();
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getL2CacheEntry(address).Sharers.clear();
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}
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}
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action(mm_markExclusive, "\m", desc="set the exclusive owner") {
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peek(L1RequestIntraChipL2Network_in, RequestMsg) {
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L2cacheMemory[address].Sharers.clear();
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L2cacheMemory[address].Exclusive := in_msg.Requestor;
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getL2CacheEntry(address).Sharers.clear();
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getL2CacheEntry(address).Exclusive := in_msg.Requestor;
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addSharer(address, in_msg.Requestor);
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}
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}
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action(mmu_markExclusiveFromUnblock, "\mu", desc="set the exclusive owner") {
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peek(L1unblockNetwork_in, ResponseMsg) {
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L2cacheMemory[address].Sharers.clear();
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L2cacheMemory[address].Exclusive := in_msg.Sender;
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getL2CacheEntry(address).Sharers.clear();
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getL2CacheEntry(address).Exclusive := in_msg.Sender;
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addSharer(address, in_msg.Sender);
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}
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}
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@ -36,8 +36,10 @@
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machine(Directory, "MESI_CMP_filter_directory protocol")
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: int to_mem_ctrl_latency,
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int directory_latency
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: DirectoryMemory * directory,
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MemoryControl * memBuffer,
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int to_mem_ctrl_latency = 1,
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int directory_latency = 6
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{
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MessageBuffer requestToDir, network="From", virtual_network="0", ordered="false";
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@ -78,23 +80,13 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
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// TYPES
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// DirectoryEntry
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structure(Entry, desc="...") {
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structure(Entry, desc="...", interface="AbstractEntry") {
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State DirectoryState, desc="Directory state";
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DataBlock DataBlk, desc="data for the block";
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NetDest Sharers, desc="Sharers for this block";
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NetDest Owner, desc="Owner of this block";
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}
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external_type(DirectoryMemory) {
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Entry lookup(Address);
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bool isPresent(Address);
|
||||
}
|
||||
|
||||
// to simulate detailed DRAM
|
||||
external_type(MemoryControl, inport="yes", outport="yes") {
|
||||
|
||||
}
|
||||
|
||||
// TBE entries for DMA requests
|
||||
structure(TBE, desc="TBE entries for outstanding DMA requests") {
|
||||
Address PhysicalAddress, desc="physical address";
|
||||
|
|
@ -113,21 +105,17 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
|||
|
||||
// ** OBJECTS **
|
||||
|
||||
// DirectoryMemory directory, constructor_hack="i";
|
||||
// MemoryControl memBuffer, constructor_hack="i";
|
||||
|
||||
DirectoryMemory directory, factory='RubySystem::getDirectory(m_cfg["directory"])';
|
||||
|
||||
MemoryControl memBuffer, factory='RubySystem::getMemoryControl(m_cfg["memory_control"])';
|
||||
|
||||
|
||||
TBETable TBEs, template_hack="<Directory_TBE>";
|
||||
|
||||
Entry getDirectoryEntry(Address addr), return_by_ref="yes" {
|
||||
return static_cast(Entry, directory[addr]);
|
||||
}
|
||||
|
||||
State getState(Address addr) {
|
||||
if (TBEs.isPresent(addr)) {
|
||||
return TBEs[addr].TBEState;
|
||||
} else if (directory.isPresent(addr)) {
|
||||
return directory[addr].DirectoryState;
|
||||
return getDirectoryEntry(addr).DirectoryState;
|
||||
} else {
|
||||
return State:I;
|
||||
}
|
||||
|
|
@ -143,14 +131,14 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
|||
if (directory.isPresent(addr)) {
|
||||
|
||||
if (state == State:I) {
|
||||
assert(directory[addr].Owner.count() == 0);
|
||||
assert(directory[addr].Sharers.count() == 0);
|
||||
assert(getDirectoryEntry(addr).Owner.count() == 0);
|
||||
assert(getDirectoryEntry(addr).Sharers.count() == 0);
|
||||
} else if (state == State:M) {
|
||||
assert(directory[addr].Owner.count() == 1);
|
||||
assert(directory[addr].Sharers.count() == 0);
|
||||
assert(getDirectoryEntry(addr).Owner.count() == 1);
|
||||
assert(getDirectoryEntry(addr).Sharers.count() == 0);
|
||||
}
|
||||
|
||||
directory[addr].DirectoryState := state;
|
||||
getDirectoryEntry(addr).DirectoryState := state;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -281,7 +269,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
|||
out_msg.OriginalRequestorMachId := in_msg.Requestor;
|
||||
out_msg.MessageSize := in_msg.MessageSize;
|
||||
out_msg.Prefetch := in_msg.Prefetch;
|
||||
out_msg.DataBlk := directory[in_msg.Address].DataBlk;
|
||||
out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk;
|
||||
|
||||
DEBUG_EXPR(out_msg);
|
||||
}
|
||||
|
|
@ -306,7 +294,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
|||
|
||||
action(m_writeDataToMemory, "m", desc="Write dirty writeback to memory") {
|
||||
peek(responseNetwork_in, ResponseMsg) {
|
||||
directory[in_msg.Address].DataBlk := in_msg.DataBlk;
|
||||
getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk;
|
||||
DEBUG_EXPR(in_msg.Address);
|
||||
DEBUG_EXPR(in_msg.DataBlk);
|
||||
}
|
||||
|
|
@ -320,7 +308,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
|||
out_msg.Sender := machineID;
|
||||
out_msg.OriginalRequestorMachId := machineID;
|
||||
out_msg.MessageSize := in_msg.MessageSize;
|
||||
out_msg.DataBlk := directory[address].DataBlk;
|
||||
out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
|
||||
DEBUG_EXPR(out_msg);
|
||||
}
|
||||
}
|
||||
|
|
@ -344,7 +332,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
|||
|
||||
action(dw_writeDMAData, "dw", desc="DMA Write data to memory") {
|
||||
peek(requestNetwork_in, RequestMsg) {
|
||||
directory[address].DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len);
|
||||
getDirectoryEntry(address).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -386,8 +374,8 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
|||
|
||||
action(e_ownerIsRequestor, "e", desc="The owner is now the requestor") {
|
||||
peek(requestNetwork_in, RequestMsg) {
|
||||
directory[address].Owner.clear();
|
||||
directory[address].Owner.add(in_msg.Requestor);
|
||||
getDirectoryEntry(address).Owner.clear();
|
||||
getDirectoryEntry(address).Owner.add(in_msg.Requestor);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -398,7 +386,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
|||
out_msg.Address := address;
|
||||
out_msg.Type := CoherenceResponseType:INV;
|
||||
out_msg.Sender := machineID;
|
||||
out_msg.Destination := directory[address].Owner;
|
||||
out_msg.Destination := getDirectoryEntry(address).Owner;
|
||||
out_msg.MessageSize := MessageSizeType:Response_Control;
|
||||
}
|
||||
}
|
||||
|
|
@ -418,7 +406,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
|||
}
|
||||
|
||||
action(c_clearOwner, "c", desc="Clear the owner field") {
|
||||
directory[address].Owner.clear();
|
||||
getDirectoryEntry(address).Owner.clear();
|
||||
}
|
||||
|
||||
action(v_allocateTBE, "v", desc="Allocate TBE") {
|
||||
|
|
@ -431,8 +419,8 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
|
|||
}
|
||||
|
||||
action(dwt_writeDMADataFromTBE, "dwt", desc="DMA Write data to memory from TBE") {
|
||||
//directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, TBEs[address].Offset, TBEs[address].Len);
|
||||
directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
|
||||
//getDirectoryEntry(address).DataBlk.copyPartial(TBEs[address].DataBlk, TBEs[address].Offset, TBEs[address].Len);
|
||||
getDirectoryEntry(address).DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(TBEs[address].PhysicalAddress), TBEs[address].Len);
|
||||
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
|
||||
machine(DMA, "DMA Controller")
|
||||
: int request_latency
|
||||
: DMASequencer * dma_sequencer,
|
||||
int request_latency = 6
|
||||
{
|
||||
|
||||
MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", no_vector="true";
|
||||
|
|
@ -25,7 +26,6 @@ machine(DMA, "DMA Controller")
|
|||
}
|
||||
|
||||
MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
|
||||
DMASequencer dma_sequencer, factory='RubySystem::getDMASequencer(m_cfg["dma_sequencer"])', no_vector="true";
|
||||
State cur_state, no_vector="true";
|
||||
|
||||
State getState(Address addr) {
|
||||
|
|
|
|||
Loading…
Reference in a new issue