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Get rid of old RegContext code.

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This commit is contained in:
Gabe Black 2008-10-12 17:57:46 -07:00
parent cefb768131
commit f245358343
17 changed files with 0 additions and 106 deletions
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7
src/arch/alpha/regfile.hh
View file

@ -206,13 +206,6 @@ class RegFile {
void serialize(EventManager *em, std::ostream &os);
void unserialize(EventManager *em, Checkpoint *cp,
const std::string &section);
void
changeContext(RegContextParam param, RegContextVal val)
{
//This would be an alternative place to call/implement
//the swapPALShadow function
}
};
static inline int

7
src/arch/alpha/types.hh
View file

@ -57,13 +57,6 @@ union AnyReg
MiscReg ctrlreg;
};
enum RegContextParam
{
CONTEXT_PALMODE
};
typedef bool RegContextVal;
enum annotes
{
ANNOTE_NONE = 0,

6
src/arch/mips/regfile.cc
View file

@ -188,12 +188,6 @@ RegFile::unserialize(Checkpoint *cp, const std::string &section)
}
void RegFile::changeContext(RegContextParam param, RegContextVal val)
{
panic("Change Context Not Implemented for MipsISA");
}
static inline int flattenIntIndex(ThreadContext * tc, int reg)
{
return reg;

4
src/arch/mips/regfile/regfile.hh
View file

@ -104,10 +104,6 @@ namespace MipsISA
void unserialize(EventManager *em, Checkpoint *cp,
const std::string &section);
void changeContext(RegContextParam param, RegContextVal val)
{
}
};
} // namespace MipsISA

3
src/arch/mips/types.hh
View file

@ -60,9 +60,6 @@ namespace MipsISA
MiscReg ctrlreg;
} AnyReg;
typedef int RegContextParam;
typedef int RegContextVal;
//used in FP convert & round function
enum ConvertType{
SINGLE_TO_DOUBLE,

3
src/arch/sparc/miscregfile.cc
View file

@ -551,11 +551,8 @@ void MiscRegFile::setReg(int miscReg,
new_val = val >= NWindows ? NWindows - 1 : val;
if (val >= NWindows)
new_val = NWindows - 1;
tc->changeRegFileContext(CONTEXT_CWP, new_val);
break;
case MISCREG_GL:
tc->changeRegFileContext(CONTEXT_GLOBALS, val);
break;
case MISCREG_PIL:
case MISCREG_SOFTINT:

15
src/arch/sparc/regfile.cc
View file

@ -241,21 +241,6 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
UNSERIALIZE_SCALAR(nnpc);
}
void RegFile::changeContext(RegContextParam param, RegContextVal val)
{
switch(param)
{
case CONTEXT_CWP:
intRegFile.setCWP(val);
break;
case CONTEXT_GLOBALS:
intRegFile.setGlobals(val);
break;
default:
panic("Tried to set illegal context parameter in the SPARC regfile.\n");
}
}
void SparcISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
{

2
src/arch/sparc/regfile.hh
View file

@ -117,8 +117,6 @@ namespace SparcISA
const std::string &section);
public:
void changeContext(RegContextParam param, RegContextVal val);
};
int flattenIntIndex(ThreadContext * tc, int reg);

8
src/arch/sparc/types.hh
View file

@ -51,14 +51,6 @@ namespace SparcISA
MiscReg ctrlreg;
} AnyReg;
enum RegContextParam
{
CONTEXT_CWP,
CONTEXT_GLOBALS
};
typedef int RegContextVal;
typedef uint16_t RegIndex;
struct CoreSpecific {

5
src/arch/x86/regfile.cc
View file

@ -248,11 +248,6 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
UNSERIALIZE_SCALAR(nextRip);
}
void RegFile::changeContext(RegContextParam param, RegContextVal val)
{
panic("changeContext not implemented for x86!\n");
}
void X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
{
panic("copyMiscRegs not implemented for x86!\n");

2
src/arch/x86/regfile.hh
View file

@ -145,8 +145,6 @@ namespace X86ISA
const std::string &section);
public:
void changeContext(RegContextParam param, RegContextVal val);
};
int flattenIntIndex(ThreadContext * tc, int reg);

11
src/arch/x86/types.hh
View file

@ -246,17 +246,6 @@ namespace X86ISA
MiscReg ctrlReg;
} AnyReg;
//XXX This is very hypothetical. X87 instructions would need to
//change their "context" constantly. It's also not clear how
//this would be handled as far as out of order execution.
//Maybe x87 instructions are in order?
enum RegContextParam
{
CONTEXT_X87_TOP
};
typedef int RegContextVal;
typedef uint16_t RegIndex;
struct CoreSpecific {

6
src/cpu/checker/thread_context.hh
View file

@ -294,12 +294,6 @@ class CheckerThreadContext : public ThreadContext
Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
#endif
void changeRegFileContext(TheISA::RegContextParam param,
TheISA::RegContextVal val)
{
actualTC->changeRegFileContext(param, val);
checkerTC->changeRegFileContext(param, val);
}
};
#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__

9
src/cpu/o3/thread_context.hh
View file

@ -281,15 +281,6 @@ class O3ThreadContext : public ThreadContext
this->cpu->setNextNPC(val, this->thread->readTid());
}
virtual void changeRegFileContext(TheISA::RegContextParam param,
TheISA::RegContextVal val)
{
#if THE_ISA != SPARC_ISA
panic("changeRegFileContext not implemented.");
#endif
}
/** This function exits the thread context in the CPU and returns
* 1 if the CPU has no more active threads (meaning it's OK to exit);
* Used in syscall-emulation mode when a thread executes the 'exit'

3
src/cpu/ozone/cpu.hh
View file

@ -271,9 +271,6 @@ class OzoneCPU : public BaseCPU
void setFuncExeInst(Counter new_val)
{ thread->funcExeInst = new_val; }
#endif
void changeRegFileContext(TheISA::RegContextParam param,
TheISA::RegContextVal val)
{ panic("Not supported on Alpha!"); }
};
// Ozone specific thread context

6
src/cpu/simple_thread.hh
View file

@ -405,12 +405,6 @@ class SimpleThread : public ThreadState
process->syscall(callnum, tc);
}
#endif
void changeRegFileContext(TheISA::RegContextParam param,
TheISA::RegContextVal val)
{
regs.changeContext(param, val);
}
};

9
src/cpu/thread_context.hh
View file

@ -272,9 +272,6 @@ class ThreadContext
virtual int exit() { return 1; };
#endif
virtual void changeRegFileContext(TheISA::RegContextParam param,
TheISA::RegContextVal val) = 0;
/** function to compare two thread contexts (for debugging) */
static void compare(ThreadContext *one, ThreadContext *two);
};
@ -467,12 +464,6 @@ class ProxyThreadContext : public ThreadContext
Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
#endif
void changeRegFileContext(TheISA::RegContextParam param,
TheISA::RegContextVal val)
{
actualTC->changeRegFileContext(param, val);
}
};
#endif