X86: Add a wrattr microop.

2009-02-25 10:17:38 -08:00 · 2009-02-25 10:17:38 -08:00 · fcad6e3b13
parent e4ede69b2f
commit fcad6e3b13
1 changed files with 5 additions and 0 deletions
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@ -1009,6 +1009,11 @@ let {{
            SegSelDest = psrc1;
        '''

+    class WrAttr(SegOp):
+        code = '''
+            SegAttrDest = psrc1;
+        '''
+
    class Rdbase(SegOp):
        code = '''
            DestReg = SegBaseSrc1;