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ISA: Get rid of the get*RegName functions.

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This commit is contained in:
Gabe Black 2009-02-25 10:22:31 -08:00
parent 3b01535ec1
commit 437b02884d
20 changed files with 29 additions and 132 deletions
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6
src/arch/alpha/floatregfile.hh
View file

@ -42,12 +42,6 @@ class Checkpoint;
namespace AlphaISA {
static inline std::string
getFloatRegName(RegIndex)
{
return "";
}
class FloatRegFile
{
public:

6
src/arch/alpha/intregfile.hh
View file

@ -41,12 +41,6 @@ class Checkpoint;
namespace AlphaISA {
static inline std::string
getIntRegName(RegIndex)
{
return "";
}
// redirected register map, really only used for the full system case.
extern const int reg_redir[NumIntRegs];

6
src/arch/alpha/miscregfile.hh
View file

@ -53,12 +53,6 @@ enum MiscRegIndex
MISCREG_INTR
};
static inline std::string
getMiscRegName(RegIndex)
{
return "";
}
class MiscRegFile
{
public:

5
src/arch/mips/regfile/float_regfile.hh
View file

@ -44,11 +44,6 @@ class Checkpoint;
namespace MipsISA
{
static inline std::string getFloatRegName(RegIndex)
{
return "";
}
const uint32_t MIPS32_QNAN = 0x7fbfffff;
const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff);

5
src/arch/mips/regfile/int_regfile.hh
View file

@ -42,11 +42,6 @@ class Checkpoint;
namespace MipsISA
{
static inline std::string getIntRegName(RegIndex)
{
return "";
}
enum MiscIntRegNums {
LO = NumIntArchRegs,
HI,

16
src/arch/mips/regfile/misc_regfile.cc
View file

@ -437,12 +437,6 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
}
inline std::string
MipsISA::getMiscRegName(unsigned reg_idx)
{
return MiscRegFile::miscRegNames[reg_idx];
}
inline unsigned
MiscRegFile::getVPENum(unsigned tid)
{
@ -457,7 +451,7 @@ MiscRegFile::readRegNoEffect(int reg_idx, unsigned tid)
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg),
misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
miscRegFile[misc_reg][reg_sel]);
return miscRegFile[misc_reg][reg_sel];
}
@ -474,7 +468,7 @@ MiscRegFile::readReg(int reg_idx,
? tid : getVPENum(tid);
DPRINTF(MipsPRA,
"Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg),
misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg],
miscRegFile[misc_reg][reg_sel]);
@ -494,7 +488,7 @@ MiscRegFile::setRegNoEffect(int reg_idx, const MiscReg &val, unsigned tid)
DPRINTF(MipsPRA,
"[tid:%i]: Setting (direct set) CP0 Register:%u "
"Select:%u (%s) to %#x.\n",
tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val);
tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
miscRegFile[misc_reg][reg_sel] = val;
}
@ -507,7 +501,7 @@ MiscRegFile::setRegMask(int reg_idx, const MiscReg &val, unsigned tid)
? tid : getVPENum(tid);
DPRINTF(MipsPRA,
"[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",
tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val);
tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
miscRegFile_WriteMask[misc_reg][reg_sel] = val;
}
@ -527,7 +521,7 @@ MiscRegFile::setReg(int reg_idx, const MiscReg &val,
DPRINTF(MipsPRA,
"[tid:%i]: Setting CP0 Register:%u "
"Select:%u (%s) to %#x, with effect.\n",
tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val);
tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val);

2
src/arch/mips/regfile/misc_regfile.hh
View file

@ -162,8 +162,6 @@ namespace MipsISA
static std::string miscRegNames[NumMiscRegs];
};
inline std::string getMiscRegName(unsigned reg_idx);
} // namespace MipsISA
#endif

14
src/arch/sparc/floatregfile.cc
View file

@ -41,20 +41,6 @@ using namespace std;
class Checkpoint;
string SparcISA::getFloatRegName(RegIndex index)
{
static std::string floatRegName[NumFloatRegs] =
{"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
"f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
"f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
"f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
"f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63"};
return floatRegName[index];
}
void FloatRegFile::clear()
{
memset(regSpace, 0, sizeof(regSpace));

2
src/arch/sparc/floatregfile.hh
View file

@ -42,8 +42,6 @@ class Checkpoint;
namespace SparcISA
{
std::string getFloatRegName(RegIndex);
const int NumFloatArchRegs = 64;
const int NumFloatRegs = 64;

10
src/arch/sparc/intregfile.cc
View file

@ -41,16 +41,6 @@ using namespace std;
class Checkpoint;
string SparcISA::getIntRegName(RegIndex index)
{
static std::string intRegName[NumIntArchRegs] =
{"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
"o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
"i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7"};
return intRegName[index];
}
void IntRegFile::clear()
{
memset(regs, 0, sizeof(IntReg) * NumIntRegs);

3
src/arch/sparc/intregfile.hh
View file

@ -42,9 +42,6 @@ class Checkpoint;
namespace SparcISA
{
//This function translates integer register file indices into names
std::string getIntRegName(RegIndex);
const int NumIntArchRegs = 32;
const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;

28
src/arch/sparc/miscregfile.cc
View file

@ -42,27 +42,6 @@ using namespace std;
class Checkpoint;
//These functions map register indices to names
string SparcISA::getMiscRegName(RegIndex index)
{
static::string miscRegName[NumMiscRegs] =
{/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
"gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
"stick", "stick_cmpr",
"tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
"pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
"wstate",*/ "gl",
"hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
"hstick_cmpr",
"fsr", "prictx", "secctx", "partId", "lsuCtrlReg",
"scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
"scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
"devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
"nresErrorHead", "nresErrorTail", "TlbData" };
return miscRegName[index];
}
enum RegMask
{
PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12)
@ -328,8 +307,7 @@ MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
//isn't, instead of panicing.
return 0;
panic("Accessing Fullsystem register %s in SE mode\n",
getMiscRegName(miscReg));
panic("Accessing Fullsystem register %d in SE mode\n", miscReg);
#endif
}
@ -583,8 +561,8 @@ void MiscRegFile::setReg(int miscReg,
//HPSTATE is special because normal trap processing saves HPSTATE when
//it goes into a trap, and restores it when it returns.
return;
panic("Accessing Fullsystem register %s to %#x in SE mode\n",
getMiscRegName(miscReg), val);
panic("Accessing Fullsystem register %d to %#x in SE mode\n",
miscReg, val);
#endif
}
setRegNoEffect(miscReg, new_val);

3
src/arch/sparc/miscregfile.hh
View file

@ -43,9 +43,6 @@ class Checkpoint;
namespace SparcISA
{
//These functions map register indices to names
std::string getMiscRegName(RegIndex);
enum MiscRegIndex
{
/** Ancillary State Registers */

21
src/arch/sparc/ua2005.cc
View file

@ -35,6 +35,7 @@
#include "sim/system.hh"
using namespace SparcISA;
using namespace std;
void
@ -61,6 +62,26 @@ MiscRegFile::checkSoftInt(ThreadContext *tc)
}
}
//These functions map register indices to names
static inline string
getMiscRegName(RegIndex index)
{
static string miscRegName[NumMiscRegs] =
{/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
"gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
"stick", "stick_cmpr",
"tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
"pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
"wstate",*/ "gl",
"hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
"hstick_cmpr",
"fsr", "prictx", "secctx", "partId", "lsuCtrlReg",
"scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
"scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
"devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
"nresErrorHead", "nresErrorTail", "TlbData" };
return miscRegName[index];
}
void
MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)

9
src/arch/x86/floatregfile.cc
View file

@ -96,15 +96,6 @@ using namespace std;
class Checkpoint;
string X86ISA::getFloatRegName(RegIndex index)
{
static std::string floatRegName[NumFloatRegs] =
{"mmx0", "mmx1", "mmx2", "mmx3", "mmx4", "mmx5", "mmx6", "mmx7",
"xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
"xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"};
return floatRegName[index];
}
void FloatRegFile::clear()
{
memset(q, 0, sizeof(FloatReg) * NumFloatRegs);

2
src/arch/x86/floatregfile.hh
View file

@ -98,8 +98,6 @@ class Checkpoint;
namespace X86ISA
{
std::string getFloatRegName(RegIndex);
//Each 128 bit xmm register is broken into two effective 64 bit registers.
const int NumFloatRegs =
NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs;

11
src/arch/x86/intregfile.cc
View file

@ -97,17 +97,6 @@ using namespace std;
class Checkpoint;
string X86ISA::getIntRegName(RegIndex index)
{
//These might appear to be out of order, but they match
//the encoding for the registers. Who knows why the indexes
//are out of order
static std::string intRegName[NumIntArchRegs] =
{"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
return intRegName[index];
}
int IntRegFile::flattenIndex(int reg)
{
return reg;

3
src/arch/x86/intregfile.hh
View file

@ -100,9 +100,6 @@ namespace X86ISA
{
class Regfile;
//This function translates integer register file indices into names
std::string getIntRegName(RegIndex);
const int NumIntArchRegs = NUM_INTREGS;
const int NumIntRegs =
NumIntArchRegs + NumMicroIntRegs +

6
src/arch/x86/miscregfile.cc
View file

@ -96,12 +96,6 @@ using namespace std;
class Checkpoint;
//These functions map register indices to names
string X86ISA::getMiscRegName(RegIndex index)
{
panic("No misc registers in x86 yet!\n");
}
void MiscRegFile::clear()
{
// Blank everything. 0 might not be an appropriate value for some things,

3
src/arch/x86/miscregfile.hh
View file

@ -99,9 +99,6 @@ class Checkpoint;
namespace X86ISA
{
std::string getMiscRegName(RegIndex);
//These will have to be updated in the future.
const int NumMiscArchRegs = NUM_MISCREGS;
const int NumMiscRegs = NUM_MISCREGS;