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This commit is contained in:
Nathan Binkert 2008-08-11 14:47:49 -07:00
parent 9cf8ad3a17
commit 1b1a7e33e7
4 changed files with 133 additions and 93 deletions
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143
src/arch/mips/regfile/misc_regfile.cc
View file

@ -45,39 +45,49 @@
using namespace std;
std::string MiscRegFile::miscRegNames[NumMiscRegs] =
{"Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "",
"Random", "VPEControl", "VPEConf0", "VPEConf1", "YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt",
"EntryLo0", "TCStatus", "TCBind", "TCRestart", "TCHalt", "TCContext", "TCSchedule", "TCScheFBack",
"EntryLo1", "", "", "", "", "", "", "",
"Context", "ContextConfig", "", "", "", "", "", "",
"PageMask", "PageGrain", "", "", "", "", "", "",
"Wired", "SRSConf0", "SRCConf1", "SRSConf2", "SRSConf3", "SRSConf4", "", "",
"HWREna", "", "", "", "", "", "", "",
"BadVAddr", "", "", "", "", "", "", "",
"Count", "", "", "", "", "", "", "",
"EntryHi", "", "", "", "", "", "", "",
"Compare", "", "", "", "", "", "", "",
"Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "",
"Cause", "", "", "", "", "", "", "",
"EPC", "", "", "", "", "", "", "",
"PRId", "EBase", "", "", "", "", "", "",
"Config", "Config1", "Config2", "Config3", "", "", "", "",
"LLAddr", "", "", "", "", "", "", "",
"WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3", "WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7",
"WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3", "WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7",
"XCContext64", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"Debug", "TraceControl1", "TraceControl2", "UserTraceData", "TraceBPC", "", "", "",
"DEPC", "", "", "", "", "", "", "",
"PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3", "PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7",
"ErrCtl", "", "", "", "", "", "", "",
"CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "",
"TagLo0", "DataLo1", "TagLo2", "DataLo3", "TagLo4", "DataLo5", "TagLo6", "DataLo7",
"TagHi0", "DataHi1", "TagHi2", "DataHi3", "TagHi4", "DataHi5", "TagHi6", "DataHi7",
"ErrorEPC", "", "", "", "", "", "", "",
"DESAVE", "", "", "", "", "", "", "",
"LLFlag"
{
"Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "",
"Random", "VPEControl", "VPEConf0", "VPEConf1",
"YQMask", "VPESchedule", "VPEScheFBack", "VPEOpt",
"EntryLo0", "TCStatus", "TCBind", "TCRestart",
"TCHalt", "TCContext", "TCSchedule", "TCScheFBack",
"EntryLo1", "", "", "", "", "", "", "",
"Context", "ContextConfig", "", "", "", "", "", "",
"PageMask", "PageGrain", "", "", "", "", "", "",
"Wired", "SRSConf0", "SRCConf1", "SRSConf2",
"SRSConf3", "SRSConf4", "", "",
"HWREna", "", "", "", "", "", "", "",
"BadVAddr", "", "", "", "", "", "", "",
"Count", "", "", "", "", "", "", "",
"EntryHi", "", "", "", "", "", "", "",
"Compare", "", "", "", "", "", "", "",
"Status", "IntCtl", "SRSCtl", "SRSMap", "", "", "", "",
"Cause", "", "", "", "", "", "", "",
"EPC", "", "", "", "", "", "", "",
"PRId", "EBase", "", "", "", "", "", "",
"Config", "Config1", "Config2", "Config3", "", "", "", "",
"LLAddr", "", "", "", "", "", "", "",
"WatchLo0", "WatchLo1", "WatchLo2", "WatchLo3",
"WatchLo4", "WatchLo5", "WatchLo6", "WatchLo7",
"WatchHi0", "WatchHi1", "WatchHi2", "WatchHi3",
"WatchHi4", "WatchHi5", "WatchHi6", "WatchHi7",
"XCContext64", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"Debug", "TraceControl1", "TraceControl2", "UserTraceData",
"TraceBPC", "", "", "",
"DEPC", "", "", "", "", "", "", "",
"PerfCnt0", "PerfCnt1", "PerfCnt2", "PerfCnt3",
"PerfCnt4", "PerfCnt5", "PerfCnt6", "PerfCnt7",
"ErrCtl", "", "", "", "", "", "", "",
"CacheErr0", "CacheErr1", "CacheErr2", "CacheErr3", "", "", "", "",
"TagLo0", "DataLo1", "TagLo2", "DataLo3",
"TagLo4", "DataLo5", "TagLo6", "DataLo7",
"TagHi0", "DataHi1", "TagHi2", "DataHi3",
"TagHi4", "DataHi5", "TagHi6", "DataHi7",
"ErrorEPC", "", "", "", "", "", "", "",
"DESAVE", "", "", "", "", "", "", "",
"LLFlag"
};
MiscRegFile::MiscRegFile()
@ -212,7 +222,8 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
// Config1
MiscReg cfg1 = readRegNoEffect(Config1);
replaceBits(cfg1, Config1_MMUSize_HI, Config1_MMUSize_LO, cp.CP0_Config1_MMU);
replaceBits(cfg1, Config1_MMUSize_HI, Config1_MMUSize_LO,
cp.CP0_Config1_MMU);
replaceBits(cfg1, Config1_IS_HI, Config1_IS_LO, cp.CP0_Config1_IS);
replaceBits(cfg1, Config1_IL_HI, Config1_IL_LO, cp.CP0_Config1_IL);
replaceBits(cfg1, Config1_IA_HI, Config1_IA_LO, cp.CP0_Config1_IA);
@ -334,12 +345,18 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
// Status
MiscReg stat = readRegNoEffect(Status);
// Only CU0 and IE are modified on a reset - everything else needs to be controlled
// on a per CPU model basis
// replaceBits(stat, Status_CU0_HI,Status_CU0_LO, 1); // Enable CP0 on reset
// Only CU0 and IE are modified on a reset - everything else needs
// to be controlled on a per CPU model basis
// Enable CP0 on reset
// replaceBits(stat, Status_CU0_HI,Status_CU0_LO, 1);
// Enable ERL bit on a reset
replaceBits(stat, Status_ERL_HI, Status_ERL_LO, 1);
// Enable BEV bit on a reset
replaceBits(stat, Status_BEV_HI, Status_BEV_LO, 1);
replaceBits(stat, Status_ERL_HI, Status_ERL_LO, 1); // Enable ERL bit on a reset
replaceBits(stat, Status_BEV_HI, Status_BEV_LO, 1); // Enable BEV bit on a reset
setRegNoEffect(Status, stat);
// Now, create Write Mask for the Status register
MiscReg stat_Mask = 0xFF78FF17;
@ -440,7 +457,8 @@ MiscRegFile::readRegNoEffect(int reg_idx, unsigned tid)
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) (%lx).\n",
misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg),miscRegFile[misc_reg][reg_sel]);
misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg),
miscRegFile[misc_reg][reg_sel]);
return miscRegFile[misc_reg][reg_sel];
}
@ -454,8 +472,10 @@ MiscRegFile::readReg(int reg_idx,
int misc_reg = reg_idx - Ctrl_Base_DepTag;
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
DPRINTF(MipsPRA, "Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg),miscRegFile[misc_reg][reg_sel]);
DPRINTF(MipsPRA,
"Reading CP0 Register:%u Select:%u (%s) with effect (%lx).\n",
misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg),
miscRegFile[misc_reg][reg_sel]);
switch (misc_reg)
@ -471,7 +491,9 @@ MiscRegFile::setRegNoEffect(int reg_idx, const MiscReg &val, unsigned tid)
int misc_reg = reg_idx - Ctrl_Base_DepTag;
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
DPRINTF(MipsPRA, "[tid:%i]: Setting (direct set) CP0 Register:%u Select:%u (%s) to %#x.\n",
DPRINTF(MipsPRA,
"[tid:%i]: Setting (direct set) CP0 Register:%u "
"Select:%u (%s) to %#x.\n",
tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val);
miscRegFile[misc_reg][reg_sel] = val;
@ -483,7 +505,9 @@ MiscRegFile::setRegMask(int reg_idx, const MiscReg &val, unsigned tid)
int misc_reg = reg_idx - Ctrl_Base_DepTag;
unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
DPRINTF(MipsPRA,"[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val);
DPRINTF(MipsPRA,
"[tid:%i]: Setting CP0 Register: %u Select: %u (%s) to %#x\n",
tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val);
miscRegFile_WriteMask[misc_reg][reg_sel] = val;
}
@ -500,7 +524,9 @@ MiscRegFile::setReg(int reg_idx, const MiscReg &val,
int reg_sel = (bankType[misc_reg] == perThreadContext)
? tid : getVPENum(tid);
DPRINTF(MipsPRA, "[tid:%i]: Setting CP0 Register:%u Select:%u (%s) to %#x, with effect.\n",
DPRINTF(MipsPRA,
"[tid:%i]: Setting CP0 Register:%u "
"Select:%u (%s) to %#x, with effect.\n",
tid, misc_reg / 8, misc_reg % 8, getMiscRegName(misc_reg), val);
MiscReg cp0_val = filterCP0Write(misc_reg, reg_sel, val);
@ -509,16 +535,28 @@ MiscRegFile::setReg(int reg_idx, const MiscReg &val,
scheduleCP0Update(1);
}
/** This method doesn't need to adjust the Control Register Offset since
it has already been done in the calling method (setRegWithEffect) */
MiscReg MiscRegFile::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
/**
* This method doesn't need to adjust the Control Register Offset
* since it has already been done in the calling method
* (setRegWithEffect)
*/
MiscReg
MiscRegFile::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val)
{
MiscReg retVal = val;
retVal &= miscRegFile_WriteMask[misc_reg][reg_sel]; // Mask off read-only regions
// Mask off read-only regions
retVal &= miscRegFile_WriteMask[misc_reg][reg_sel];
MiscReg curVal = miscRegFile[misc_reg][reg_sel];
curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]); // Mask off current alue with inverse mask (clear writeable bits)
// Mask off current alue with inverse mask (clear writeable bits)
curVal &= (~miscRegFile_WriteMask[misc_reg][reg_sel]);
retVal |= curVal; // Combine the two
DPRINTF(MipsPRA,"filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, current val: %lx, written val: %x\n",miscRegFile_WriteMask[misc_reg][reg_sel],~miscRegFile_WriteMask[misc_reg][reg_sel],val,miscRegFile[misc_reg][reg_sel],retVal);
DPRINTF(MipsPRA,
"filterCP0Write: Mask: %lx, Inverse Mask: %lx, write Val: %x, "
"current val: %lx, written val: %x\n",
miscRegFile_WriteMask[misc_reg][reg_sel],
~miscRegFile_WriteMask[misc_reg][reg_sel],
val, miscRegFile[misc_reg][reg_sel], retVal);
return retVal;
}
void
@ -563,7 +601,8 @@ MiscRegFile::updateCPU()
}
MiscRegFile::CP0Event::CP0Event(CP0 *_cp0, BaseCPU *_cpu, CP0EventType e_type)
: Event(&mainEventQueue, CPU_Tick_Pri), cp0(_cp0), cpu(_cpu), cp0EventType(e_type)
: Event(&mainEventQueue, CPU_Tick_Pri), cp0(_cp0), cpu(_cpu),
cp0EventType(e_type)
{ }
void

6
src/arch/mips/regfile/misc_regfile.hh
View file

@ -75,7 +75,8 @@ namespace MipsISA
void clear(unsigned tid_or_vpn = 0);
void reset(std::string core_name, unsigned num_threads, unsigned num_vpes, BaseCPU *_cpu);
void reset(std::string core_name, unsigned num_threads,
unsigned num_vpes, BaseCPU *_cpu);
void expandForMultithreading(unsigned num_threads, unsigned num_vpes);
@ -98,7 +99,8 @@ namespace MipsISA
MiscReg filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val);
void setRegMask(int misc_reg, const MiscReg &val, unsigned tid = 0);
void setRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0);
void setRegNoEffect(int misc_reg, const MiscReg &val,
unsigned tid = 0);
//template <class TC>
void setReg(int misc_reg, const MiscReg &val,

13
src/arch/sparc/miscregfile.cc
View file

@ -322,12 +322,14 @@ MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
return readFSReg(miscReg, tc);
#else
case MISCREG_HPSTATE:
//HPSTATE is special because because sometimes in privilege checks for instructions
//it will read HPSTATE to make sure the priv. level is ok
//So, we'll just have to tell it it isn't, instead of panicing.
//HPSTATE is special because because sometimes in privilege
//checks for instructions it will read HPSTATE to make sure
//the priv. level is ok So, we'll just have to tell it it
//isn't, instead of panicing.
return 0;
panic("Accessing Fullsystem register %s in SE mode\n",getMiscRegName(miscReg));
panic("Accessing Fullsystem register %s in SE mode\n",
getMiscRegName(miscReg));
#endif
}
@ -584,7 +586,8 @@ void MiscRegFile::setReg(int miscReg,
//HPSTATE is special because normal trap processing saves HPSTATE when
//it goes into a trap, and restores it when it returns.
return;
panic("Accessing Fullsystem register %s to %#x in SE mode\n", getMiscRegName(miscReg), val);
panic("Accessing Fullsystem register %s to %#x in SE mode\n",
getMiscRegName(miscReg), val);
#endif
}
setRegNoEffect(miscReg, new_val);

64
src/arch/sparc/ua2005.cc
View file

@ -40,22 +40,24 @@ using namespace SparcISA;
void
MiscRegFile::checkSoftInt(ThreadContext *tc)
{
BaseCPU *cpu = tc->getCpuPtr();
// If PIL < 14, copy over the tm and sm bits
if (pil < 14 && softint & 0x10000)
tc->getCpuPtr()->post_interrupt(IT_SOFT_INT,16);
cpu->post_interrupt(IT_SOFT_INT, 16);
else
tc->getCpuPtr()->clear_interrupt(IT_SOFT_INT,16);
cpu->clear_interrupt(IT_SOFT_INT, 16);
if (pil < 14 && softint & 0x1)
tc->getCpuPtr()->post_interrupt(IT_SOFT_INT,0);
cpu->post_interrupt(IT_SOFT_INT, 0);
else
tc->getCpuPtr()->clear_interrupt(IT_SOFT_INT,0);
cpu->clear_interrupt(IT_SOFT_INT, 0);
// Copy over any of the other bits that are set
for (int bit = 15; bit > 0; --bit) {
if (1 << bit & softint && bit > pil)
tc->getCpuPtr()->post_interrupt(IT_SOFT_INT,bit);
cpu->post_interrupt(IT_SOFT_INT, bit);
else
tc->getCpuPtr()->clear_interrupt(IT_SOFT_INT,bit);
cpu->clear_interrupt(IT_SOFT_INT, bit);
}
}
@ -63,6 +65,8 @@ MiscRegFile::checkSoftInt(ThreadContext *tc)
void
MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
{
BaseCPU *cpu = tc->getCpuPtr();
int64_t time;
switch (miscReg) {
/* Full system only ASRs */
@ -85,7 +89,7 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
if (!(tick_cmpr & ~mask(63)) && time > 0) {
if (tickCompare->scheduled())
tickCompare->deschedule();
tickCompare->schedule(time * tc->getCpuPtr()->ticks(1));
tickCompare->schedule(time * cpu->ticks(1));
}
panic("writing to TICK compare register %#X\n", val);
break;
@ -97,11 +101,11 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
sTickCompare->deschedule();
time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
tc->getCpuPtr()->instCount();
cpu->instCount();
if (!(stick_cmpr & ~mask(63)) && time > 0) {
if (sTickCompare->scheduled())
sTickCompare->deschedule();
sTickCompare->schedule(time * tc->getCpuPtr()->ticks(1) + curTick);
sTickCompare->schedule(time * cpu->ticks(1) + curTick);
}
DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
break;
@ -120,9 +124,9 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
case MISCREG_HINTP:
setRegNoEffect(miscReg, val);
if (hintp)
tc->getCpuPtr()->post_interrupt(IT_HINTP,0);
cpu->post_interrupt(IT_HINTP, 0);
else
tc->getCpuPtr()->clear_interrupt(IT_HINTP,0);
cpu->clear_interrupt(IT_HINTP, 0);
break;
case MISCREG_HTBA:
@ -134,25 +138,25 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
case MISCREG_QUEUE_CPU_MONDO_TAIL:
setRegNoEffect(miscReg, val);
if (cpu_mondo_head != cpu_mondo_tail)
tc->getCpuPtr()->post_interrupt(IT_CPU_MONDO,0);
cpu->post_interrupt(IT_CPU_MONDO, 0);
else
tc->getCpuPtr()->clear_interrupt(IT_CPU_MONDO,0);
cpu->clear_interrupt(IT_CPU_MONDO, 0);
break;
case MISCREG_QUEUE_DEV_MONDO_HEAD:
case MISCREG_QUEUE_DEV_MONDO_TAIL:
setRegNoEffect(miscReg, val);
if (dev_mondo_head != dev_mondo_tail)
tc->getCpuPtr()->post_interrupt(IT_DEV_MONDO,0);
cpu->post_interrupt(IT_DEV_MONDO, 0);
else
tc->getCpuPtr()->clear_interrupt(IT_DEV_MONDO,0);
cpu->clear_interrupt(IT_DEV_MONDO, 0);
break;
case MISCREG_QUEUE_RES_ERROR_HEAD:
case MISCREG_QUEUE_RES_ERROR_TAIL:
setRegNoEffect(miscReg, val);
if (res_error_head != res_error_tail)
tc->getCpuPtr()->post_interrupt(IT_RES_ERROR,0);
cpu->post_interrupt(IT_RES_ERROR, 0);
else
tc->getCpuPtr()->clear_interrupt(IT_RES_ERROR,0);
cpu->clear_interrupt(IT_RES_ERROR, 0);
break;
case MISCREG_QUEUE_NRES_ERROR_HEAD:
case MISCREG_QUEUE_NRES_ERROR_TAIL:
@ -167,11 +171,11 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
hSTickCompare->deschedule();
time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
tc->getCpuPtr()->instCount();
cpu->instCount();
if (!(hstick_cmpr & ~mask(63)) && time > 0) {
if (hSTickCompare->scheduled())
hSTickCompare->deschedule();
hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->ticks(1));
hSTickCompare->schedule(curTick + time * cpu->ticks(1));
}
DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
break;
@ -181,9 +185,9 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
setRegNoEffect(miscReg, val | HPSTATE::id);
#if FULL_SYSTEM
if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
tc->getCpuPtr()->post_interrupt(IT_TRAP_LEVEL_ZERO,0);
cpu->post_interrupt(IT_TRAP_LEVEL_ZERO, 0);
else
tc->getCpuPtr()->clear_interrupt(IT_TRAP_LEVEL_ZERO,0);
cpu->clear_interrupt(IT_TRAP_LEVEL_ZERO, 0);
#endif
break;
case MISCREG_HTSTATE:
@ -200,11 +204,12 @@ MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
tc->suspend();
if (tc->getKernelStats())
tc->getKernelStats()->quiesce();
}
}
break;
default:
panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
panic("Invalid write to FS misc register %s\n",
getMiscRegName(miscReg));
}
}
@ -250,7 +255,8 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc)
sys = tc->getSystemPtr();
temp = readRegNoEffect(miscReg) & (STS::active | STS::speculative);
// Check that the CPU array is fully populated (by calling getNumCPus())
// Check that the CPU array is fully populated
// (by calling getNumCPus())
assert(sys->getNumCPUs() > tc->readCpuId());
temp |= tc->readCpuId() << STS::shft_id;
@ -280,16 +286,6 @@ MiscRegFile::readFSReg(int miscReg, ThreadContext * tc)
panic("Invalid read to FS misc register\n");
}
}
/*
In Niagra STICK==TICK so this isn't needed
case MISCREG_STICK:
SparcSystem *sys;
sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
assert(sys != NULL);
return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
*/
void
MiscRegFile::processTickCompare(ThreadContext *tc)