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X86: Implement the load machine status word instruction (LMSW).

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This commit is contained in:
Gabe Black 2009-04-19 03:17:14 -07:00
parent b4ad233c0c
commit d86cd1d2a0
2 changed files with 38 additions and 2 deletions
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4
src/arch/x86/isa/decoder/two_byte_opcodes.isa
View file

@ -126,7 +126,7 @@
0x7: invlpga();
}
0x4: smsw_Rv();
0x6: lmsw_Rv();
0x6: Inst::LMSW(Rv);
0x7: decode MODRM_RM {
0x0: Inst::SWAPGS();
0x1: rdtscp();
@ -156,7 +156,7 @@
}
}
0x4: smsw_Mw();
0x6: lmsw_Mw();
0x6: Inst::LMSW(Mw);
0x7: Inst::INVLPG(M);
default: Inst::UD2();
}

36
src/arch/x86/isa/insts/system/control_registers.py
View file

@ -32,4 +32,40 @@ def macroop CLTS {
andi t1, t1, 0xF7, dataSize=1
wrcr 0, t1, dataSize=8
};
def macroop LMSW_R {
rdcr t1, 0, dataSize=8
# This logic sets MP, EM, and TS to whatever is in the operand. It will
# set PE but not clear it.
limm t2, "~ULL(0xe)", dataSize=8
and t1, t1, t2, dataSize=8
andi t2, reg, 0xf, dataSize=8
or t1, t1, t2, dataSize=8
wrcr 0, t1, dataSize=8
};
def macroop LMSW_M {
ld t3, seg, sib, disp, dataSize=2
rdcr t1, 0, dataSize=8
# This logic sets MP, EM, and TS to whatever is in the operand. It will
# set PE but not clear it.
limm t2, "~ULL(0xe)", dataSize=8
and t1, t1, t2, dataSize=8
andi t2, t3, 0xf, dataSize=8
or t1, t1, t2, dataSize=8
wrcr 0, t1, dataSize=8
};
def macroop LMSW_P {
rdip t7, dataSize=asz
ld t3, seg, riprel, disp, dataSize=2
rdcr t1, 0, dataSize=8
# This logic sets MP, EM, and TS to whatever is in the operand. It will
# set PE but not clear it.
limm t2, "~ULL(0xe)", dataSize=8
and t1, t1, t2, dataSize=8
andi t2, t3, 0xf, dataSize=8
or t1, t1, t2, dataSize=8
wrcr 0, t1, dataSize=8
};
'''