gem5/src
Vince Weaver 8f6744c19c X86: add ULL to 1's being shifted in 64-bit values
Some of the micro-ops weren't casting 1 to ULL before shifting,
which can cause problems.  On the perl makerand input this
caused some values to be negative that shouldn't have been.

The casts are done as ULL(1) instead of 1ULL to match others
in the m5 code base.
2009-11-11 17:49:09 -05:00
..
arch X86: add ULL to 1's being shifted in 64-bit values 2009-11-11 17:49:09 -05:00
base build: fix compile problems pointed out by gcc 4.4 2009-11-04 16:57:01 -08:00
cpu Mem: Eliminate the NO_FAULT request flag. 2009-11-10 21:10:18 -08:00
dev build: fix compile problems pointed out by gcc 4.4 2009-11-04 16:57:01 -08:00
doxygen Fix up doxygen. 2006-08-14 19:25:07 -04:00
kern build: fix compile problems pointed out by gcc 4.4 2009-11-04 16:57:01 -08:00
mem Mem: Eliminate the NO_FAULT request flag. 2009-11-10 21:10:18 -08:00
python ply grammar: Fixup Tokenizer class so you can get lexer arguments 2009-09-23 18:28:29 -07:00
sim syscall: missing initializer in getcwd call 2009-11-09 10:02:55 -05:00
unittest includes: sort includes again 2009-05-17 14:34:52 -07:00
Doxyfile Fix up doxygen. 2006-08-14 19:25:07 -04:00
SConscript scons: deal with generated .py files properly 2009-11-08 17:35:49 -08:00