Fix up doxygen.
--HG-- rename : docs/footer.html => src/doxygen/footer.html rename : docs/stl.hh => src/doxygen/stl.hh extra : convert_revision : 2b2e5637930843c1be07deaa708fd4126213cda2
This commit is contained in:
parent
a04552ce86
commit
5bd07f98ed
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@ -30,7 +30,7 @@ PROJECT_NUMBER =
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# If a relative path is entered, it will be relative to the location
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# where doxygen was started. If left blank the current directory will be used.
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OUTPUT_DIRECTORY = docs/doxygen
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OUTPUT_DIRECTORY = doxygen
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# The OUTPUT_LANGUAGE tag is used to specify the language in which all
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# documentation generated by doxygen is written. Doxygen will use this
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@ -570,7 +570,7 @@ HTML_HEADER =
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# each generated HTML page. If it is left blank doxygen will generate a
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# standard footer.
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HTML_FOOTER = docs/footer.html
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HTML_FOOTER = doxygen/footer.html
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# The HTML_STYLESHEET tag can be used to specify a user-defined cascading
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# style sheet that is used by each HTML page. It can be used to
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@ -37,7 +37,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
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int64_t time;
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SparcSystem *sys;
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switch (miscReg) {
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/** Full system only ASRs */
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/* Full system only ASRs */
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case MISCREG_SOFTINT:
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if (isNonPriv())
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return new PrivilegedOpcode;
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@ -94,7 +94,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
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sTickCompare.schedule(time * Clock::Int::ns);
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return NoFault;
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/** Fullsystem only Priv registers. */
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/* Fullsystem only Priv registers. */
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case MISCREG_PIL:
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if (FULL_SYSTEM) {
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setReg(miscReg, val);
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@ -104,7 +104,7 @@ SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
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} else
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panic("PIL not implemented for syscall emulation\n");
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/** Hyper privileged registers */
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/* Hyper privileged registers */
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case MISCREG_HPSTATE:
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case MISCREG_HINTP:
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setReg(miscReg, val);
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@ -147,7 +147,7 @@ MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc)
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{
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switch (miscReg) {
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/** Privileged registers. */
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/* Privileged registers. */
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case MISCREG_SOFTINT:
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if (isNonPriv()) {
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fault = new PrivilegedOpcode;
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@ -177,7 +177,7 @@ MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc)
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return readReg(miscReg);
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/** Hyper privileged registers */
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/* Hyper privileged registers */
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case MISCREG_HPSTATE:
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case MISCREG_HINTP:
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return readReg(miscReg);
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@ -72,7 +72,7 @@ class ChunkGenerator
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public:
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/**
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* Constructor.
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* @param startAddr The starting address of the region.
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* @param _startAddr The starting address of the region.
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* @param totalSize The total size of the region.
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* @param _chunkSize The size/alignment of chunks into which
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* the region should be decomposed.
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@ -104,11 +104,11 @@ class SymbolTable
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/// Find the nearest symbol equal to or less than the supplied
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/// address (e.g., the label for the enclosing function).
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/// @param address The address to look up.
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/// @param symbol Return reference for symbol string.
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/// @param sym_address Return reference for symbol address.
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/// @param next_sym_address Address of following symbol (for
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/// determining valid range of symbol).
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/// @param addr The address to look up.
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/// @param symbol Return reference for symbol string.
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/// @param symaddr Return reference for symbol address.
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/// @param nextaddr Address of following symbol (for
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/// determining valid range of symbol).
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/// @retval True if a symbol was found.
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bool
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findNearestSymbol(Addr addr, std::string &symbol, Addr &symaddr,
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@ -126,7 +126,7 @@ class SymbolTable
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}
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/// Overload for findNearestSymbol() for callers who don't care
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/// about next_sym_address.
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/// about nextaddr.
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bool
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findNearestSymbol(Addr addr, std::string &symbol, Addr &symaddr) const
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{
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@ -259,7 +259,7 @@ class BasicPioDevice : public PioDevice
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{}
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/** return the address ranges that this device responds to.
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* @params range_list range list to populate with ranges
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* @param range_list range list to populate with ranges
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*/
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void addressRanges(AddrRangeList &range_list);
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@ -65,14 +65,14 @@ class IsaFake : public BasicPioDevice
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/**
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* This read always returns -1.
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* @param req The memory request.
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* @param pkt The memory request.
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* @param data Where to put the data.
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*/
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virtual Tick read(Packet *pkt);
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/**
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* All writes are simply ignored.
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* @param req The memory request.
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* @param pkt The memory request.
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* @param data the data to not write.
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*/
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virtual Tick write(Packet *pkt);
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@ -83,7 +83,8 @@ class Tsunami : public Platform
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/**
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* Constructor for the Tsunami Class.
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* @param name name of the object
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* @param intrctrl pointer to the interrupt controller
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* @param s system the object belongs to
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* @param intctrl pointer to the interrupt controller
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*/
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Tsunami(const std::string &name, System *s, IntrControl *intctrl);
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@ -126,12 +126,14 @@ class TsunamiIO : public BasicPioDevice
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/**
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* Serialize this object to the given output stream.
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* @param base The base name of the counter object.
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* @param os The stream to serialize to.
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*/
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void serialize(const std::string &base, std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param base The base name of the counter object.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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@ -221,12 +223,14 @@ class TsunamiIO : public BasicPioDevice
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/**
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* Serialize this object to the given output stream.
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* @param os The stream to serialize to.
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* @param base The base name of the counter object.
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* @param os The stream to serialize to.
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*/
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void serialize(const std::string &base, std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param base The base name of the counter object.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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@ -254,12 +258,14 @@ class TsunamiIO : public BasicPioDevice
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/**
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* Serialize this object to the given output stream.
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* @param base The base name of the counter object.
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* @param os The stream to serialize to.
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*/
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void serialize(const std::string &base, std::ostream &os);
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/**
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* Reconstruct the state of this object from a checkpoint.
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* @param base The base name of the counter object.
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* @param cp The checkpoint use.
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* @param section The section name of this object
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*/
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@ -31,7 +31,8 @@
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*/
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/**
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* @file Definition of a simple bus bridge without buffering.
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* @file
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* Definition of a simple bus bridge without buffering.
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*/
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#include <algorithm>
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@ -30,7 +30,8 @@
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*/
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/**
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* @file Decleration of a simple bus bridge object with no buffering
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* @file
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* Declaration of a simple bus bridge object with no buffering
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*/
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#ifndef __MEM_BRIDGE_HH__
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@ -49,7 +50,7 @@
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class Bridge : public MemObject
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{
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protected:
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/** Decleration of the buses port type, one will be instantiated for each
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/** Declaration of the buses port type, one will be instantiated for each
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of the interfaces connecting to the bus. */
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class BridgePort : public Port
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{
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@ -29,7 +29,8 @@
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*/
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/**
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* @file Definition of a bus object.
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* @file
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* Definition of a bus object.
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*/
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@ -30,7 +30,8 @@
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*/
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/**
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* @file Decleration of a bus object.
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* @file
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* Declaration of a bus object.
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*/
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#ifndef __MEM_BUS_HH__
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@ -97,7 +98,7 @@ class Bus : public MemObject
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void addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id);
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/** Decleration of the buses port type, one will be instantiated for each
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/** Declaration of the buses port type, one will be instantiated for each
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of the interfaces connecting to the bus. */
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class BusPort : public Port
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{
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6
src/mem/cache/base_cache.hh
vendored
6
src/mem/cache/base_cache.hh
vendored
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@ -488,7 +488,7 @@ class BaseCache : public MemObject
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/**
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* Send a response to the slave interface.
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* @param req The request being responded to.
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* @param pkt The request being responded to.
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* @param time The time the response is ready.
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*/
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void respond(Packet *pkt, Tick time)
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@ -501,7 +501,7 @@ class BaseCache : public MemObject
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/**
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* Send a reponse to the slave interface and calculate miss latency.
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* @param req The request to respond to.
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* @param pkt The request to respond to.
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* @param time The time the response is ready.
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*/
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void respondToMiss(Packet *pkt, Tick time)
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@ -517,7 +517,7 @@ class BaseCache : public MemObject
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/**
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* Suppliess the data if cache to cache transfers are enabled.
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* @param req The bus transaction to fulfill.
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* @param pkt The bus transaction to fulfill.
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*/
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void respondToSnoop(Packet *pkt)
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{
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20
src/mem/cache/cache.hh
vendored
20
src/mem/cache/cache.hh
vendored
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@ -159,7 +159,7 @@ class Cache : public BaseCache
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/**
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* Performs the access specified by the request.
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* @param req The request to perform.
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* @param pkt The request to perform.
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* @return The result of the access.
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*/
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bool access(Packet * &pkt);
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@ -172,26 +172,26 @@ class Cache : public BaseCache
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/**
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* Was the request was sent successfully?
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* @param req The request.
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* @param pkt The request.
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* @param success True if the request was sent successfully.
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*/
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virtual void sendResult(Packet * &pkt, bool success);
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/**
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* Handles a response (cache line fill/write ack) from the bus.
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* @param req The request being responded to.
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* @param pkt The request being responded to.
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*/
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void handleResponse(Packet * &pkt);
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/**
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* Start handling a copy transaction.
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* @param req The copy request to perform.
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* @param pkt The copy request to perform.
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*/
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void startCopy(Packet * &pkt);
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/**
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* Handle a delayed copy transaction.
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* @param req The delayed copy request to continue.
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* @param pkt The delayed copy request to continue.
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* @param addr The address being responded to.
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* @param blk The block of the current response.
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* @param mshr The mshr being handled.
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@ -206,7 +206,7 @@ class Cache : public BaseCache
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/**
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* Snoops bus transactions to maintain coherence.
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* @param req The current bus transaction.
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* @param pkt The current bus transaction.
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*/
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void snoop(Packet * &pkt);
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@ -221,9 +221,9 @@ class Cache : public BaseCache
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void invalidateBlk(Addr addr, int asid);
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/**
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* Aquash all requests associated with specified thread.
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* Squash all requests associated with specified thread.
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* intended for use by I-cache.
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* @param req->getThreadNum()ber The thread to squash.
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* @param threadNum The thread to squash.
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*/
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void squash(int threadNum)
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{
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@ -246,7 +246,7 @@ class Cache : public BaseCache
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* time of completion. This function can either update the hierarchy state
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* or just perform the access wherever the data is found depending on the
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* state of the update flag.
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* @param req The memory request to satisfy
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* @param pkt The memory request to satisfy
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* @param update If true, update the hierarchy, otherwise just perform the
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* request.
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* @return The estimated completion time.
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@ -257,7 +257,7 @@ class Cache : public BaseCache
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* Snoop for the provided request in the cache and return the estimated
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* time of completion.
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* @todo Can a snoop probe not change state?
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* @param req The memory request to satisfy
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* @param pkt The memory request to satisfy
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* @param update If true, update the hierarchy, otherwise just perform the
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* request.
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* @return The estimated completion time.
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@ -85,7 +85,7 @@ class CoherenceProtocol : public SimObject
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/**
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* Return the proper state given the current state and the bus response.
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* @param req The bus response.
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* @param pkt The bus response.
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* @param oldState The current block state.
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* @return The new state.
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*/
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@ -95,7 +95,7 @@ class CoherenceProtocol : public SimObject
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/**
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* Handle snooped bus requests.
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* @param cache The cache that snooped the request.
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* @param req The snooped bus request.
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* @param pkt The snooped bus request.
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* @param blk The cache block corresponding to the request, if any.
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* @param mshr The MSHR corresponding to the request, if any.
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* @param new_state The new coherence state of the block.
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4
src/mem/cache/coherence/simple_coherence.hh
vendored
4
src/mem/cache/coherence/simple_coherence.hh
vendored
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@ -96,7 +96,7 @@ class SimpleCoherence
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/**
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* Return the proper state given the current state and the bus response.
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* @param req The bus response.
|
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* @param pkt The bus response.
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||||
* @param current The current block state.
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* @return The new state.
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*/
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@ -107,7 +107,7 @@ class SimpleCoherence
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/**
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* Handle snooped bus requests.
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* @param req The snooped bus request.
|
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* @param pkt The snooped bus request.
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||||
* @param blk The cache block corresponding to the request, if any.
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||||
* @param mshr The MSHR corresponding to the request, if any.
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||||
* @param new_state Return the new state for the block.
|
||||
|
|
4
src/mem/cache/coherence/uni_coherence.hh
vendored
4
src/mem/cache/coherence/uni_coherence.hh
vendored
|
@ -88,7 +88,7 @@ class UniCoherence
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|||
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||||
/**
|
||||
* Just return readable and writeable.
|
||||
* @param req The bus response.
|
||||
* @param pkt The bus response.
|
||||
* @param current The current block state.
|
||||
* @return The new state.
|
||||
*/
|
||||
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@ -116,7 +116,7 @@ class UniCoherence
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|||
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||||
/**
|
||||
* Handle snooped bus requests.
|
||||
* @param req The snooped bus request.
|
||||
* @param pkt The snooped bus request.
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||||
* @param blk The cache block corresponding to the request, if any.
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||||
* @param mshr The MSHR corresponding to the request, if any.
|
||||
* @param new_state The new coherence state of the block.
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||||
|
|
34
src/mem/cache/miss/blocking_buffer.hh
vendored
34
src/mem/cache/miss/blocking_buffer.hh
vendored
|
@ -107,7 +107,7 @@ public:
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|||
/**
|
||||
* Handle a cache miss properly. Requests the bus and marks the cache as
|
||||
* blocked.
|
||||
* @param req The request that missed in the cache.
|
||||
* @param pkt The request that missed in the cache.
|
||||
* @param blk_size The block size of the cache.
|
||||
* @param time The time the miss is detected.
|
||||
*/
|
||||
|
@ -128,43 +128,43 @@ public:
|
|||
}
|
||||
|
||||
/**
|
||||
* Selects a outstanding request to service.
|
||||
* @return The request to service, NULL if none found.
|
||||
* Selects a outstanding pktuest to service.
|
||||
* @return The pktuest to service, NULL if none found.
|
||||
*/
|
||||
Packet * getPacket();
|
||||
|
||||
/**
|
||||
* Set the command to the given bus command.
|
||||
* @param req The request to update.
|
||||
* @param pkt The request to update.
|
||||
* @param cmd The bus command to use.
|
||||
*/
|
||||
void setBusCmd(Packet * &pkt, Packet::Command cmd);
|
||||
|
||||
/**
|
||||
* Restore the original command in case of a bus transmission error.
|
||||
* @param req The request to reset.
|
||||
* @param pkt The request to reset.
|
||||
*/
|
||||
void restoreOrigCmd(Packet * &pkt);
|
||||
|
||||
/**
|
||||
* Marks a request as in service (sent on the bus). This can have side
|
||||
* Marks a pktuest as in service (sent on the bus). This can have side
|
||||
* effect since storage for no response commands is deallocated once they
|
||||
* are successfully sent.
|
||||
* @param req The request that was sent on the bus.
|
||||
* @param pkt The request that was sent on the bus.
|
||||
*/
|
||||
void markInService(Packet * &pkt);
|
||||
|
||||
/**
|
||||
* Frees the resources of the request and unblock the cache.
|
||||
* @param req The request that has been satisfied.
|
||||
* @param time The time when the request is satisfied.
|
||||
* Frees the resources of the pktuest and unblock the cache.
|
||||
* @param pkt The request that has been satisfied.
|
||||
* @param time The time when the pktuest is satisfied.
|
||||
*/
|
||||
void handleResponse(Packet * &pkt, Tick time);
|
||||
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||||
/**
|
||||
* Removes all outstanding requests for a given thread number. If a request
|
||||
* Removes all outstanding pktuests for a given thread number. If a request
|
||||
* has been sent to the bus, this function removes all of its targets.
|
||||
* @param req->getThreadNum()ber The thread number of the requests to squash.
|
||||
* @param threadNum The thread number of the requests to squash.
|
||||
*/
|
||||
void squash(int threadNum);
|
||||
|
||||
|
@ -220,14 +220,14 @@ public:
|
|||
int size, uint8_t *data, bool compressed);
|
||||
|
||||
/**
|
||||
* Perform a writeback request.
|
||||
* @param req The writeback request.
|
||||
* Perform a writeback pktuest.
|
||||
* @param pkt The writeback request.
|
||||
*/
|
||||
void doWriteback(Packet * &pkt);
|
||||
|
||||
/**
|
||||
* Returns true if there are outstanding requests.
|
||||
* @return True if there are outstanding requests.
|
||||
* Returns true if there are outstanding pktuests.
|
||||
* @return True if there are outstanding pktuests.
|
||||
*/
|
||||
bool havePending()
|
||||
{
|
||||
|
@ -237,7 +237,7 @@ public:
|
|||
/**
|
||||
* Add a target to the given MSHR. This assumes it is in the miss queue.
|
||||
* @param mshr The mshr to add a target to.
|
||||
* @param req The target to add.
|
||||
* @param pkt The target to add.
|
||||
*/
|
||||
void addTarget(MSHR *mshr, Packet * &pkt)
|
||||
{
|
||||
|
|
42
src/mem/cache/miss/miss_queue.hh
vendored
42
src/mem/cache/miss/miss_queue.hh
vendored
|
@ -77,7 +77,7 @@ class MissQueue
|
|||
/** The block size of the parent cache. */
|
||||
int blkSize;
|
||||
|
||||
/** Increasing order number assigned to each incoming request. */
|
||||
/** Increasing order number assigned to each incoming pktuest. */
|
||||
uint64_t order;
|
||||
|
||||
bool prefetchMiss;
|
||||
|
@ -164,7 +164,7 @@ class MissQueue
|
|||
|
||||
/**
|
||||
* Allocate a new MSHR to handle the provided miss.
|
||||
* @param req The miss to buffer.
|
||||
* @param pkt The miss to buffer.
|
||||
* @param size The number of bytes to fetch.
|
||||
* @param time The time the miss occurs.
|
||||
* @return A pointer to the new MSHR.
|
||||
|
@ -173,7 +173,7 @@ class MissQueue
|
|||
|
||||
/**
|
||||
* Allocate a new WriteBuffer to handle the provided write.
|
||||
* @param req The write to handle.
|
||||
* @param pkt The write to handle.
|
||||
* @param size The number of bytes to write.
|
||||
* @param time The time the write occurs.
|
||||
* @return A pointer to the new write buffer.
|
||||
|
@ -212,9 +212,9 @@ class MissQueue
|
|||
void setPrefetcher(BasePrefetcher *_prefetcher);
|
||||
|
||||
/**
|
||||
* Handle a cache miss properly. Either allocate an MSHR for the request,
|
||||
* Handle a cache miss properly. Either allocate an MSHR for the pktuest,
|
||||
* or forward it through the write buffer.
|
||||
* @param req The request that missed in the cache.
|
||||
* @param pkt The request that missed in the cache.
|
||||
* @param blk_size The block size of the cache.
|
||||
* @param time The time the miss is detected.
|
||||
*/
|
||||
|
@ -232,43 +232,43 @@ class MissQueue
|
|||
Packet * &target);
|
||||
|
||||
/**
|
||||
* Selects a outstanding request to service.
|
||||
* @return The request to service, NULL if none found.
|
||||
* Selects a outstanding pktuest to service.
|
||||
* @return The pktuest to service, NULL if none found.
|
||||
*/
|
||||
Packet * getPacket();
|
||||
|
||||
/**
|
||||
* Set the command to the given bus command.
|
||||
* @param req The request to update.
|
||||
* @param pkt The request to update.
|
||||
* @param cmd The bus command to use.
|
||||
*/
|
||||
void setBusCmd(Packet * &pkt, Packet::Command cmd);
|
||||
|
||||
/**
|
||||
* Restore the original command in case of a bus transmission error.
|
||||
* @param req The request to reset.
|
||||
* @param pkt The request to reset.
|
||||
*/
|
||||
void restoreOrigCmd(Packet * &pkt);
|
||||
|
||||
/**
|
||||
* Marks a request as in service (sent on the bus). This can have side
|
||||
* Marks a pktuest as in service (sent on the bus). This can have side
|
||||
* effect since storage for no response commands is deallocated once they
|
||||
* are successfully sent.
|
||||
* @param req The request that was sent on the bus.
|
||||
* @param pkt The request that was sent on the bus.
|
||||
*/
|
||||
void markInService(Packet * &pkt);
|
||||
|
||||
/**
|
||||
* Collect statistics and free resources of a satisfied request.
|
||||
* @param req The request that has been satisfied.
|
||||
* @param time The time when the request is satisfied.
|
||||
* Collect statistics and free resources of a satisfied pktuest.
|
||||
* @param pkt The request that has been satisfied.
|
||||
* @param time The time when the pktuest is satisfied.
|
||||
*/
|
||||
void handleResponse(Packet * &pkt, Tick time);
|
||||
|
||||
/**
|
||||
* Removes all outstanding requests for a given thread number. If a request
|
||||
* Removes all outstanding pktuests for a given thread number. If a request
|
||||
* has been sent to the bus, this function removes all of its targets.
|
||||
* @param req->getThreadNum()ber The thread number of the requests to squash.
|
||||
* @param threadNum The thread number of the requests to squash.
|
||||
*/
|
||||
void squash(int threadNum);
|
||||
|
||||
|
@ -313,21 +313,21 @@ class MissQueue
|
|||
int size, uint8_t *data, bool compressed);
|
||||
|
||||
/**
|
||||
* Perform the given writeback request.
|
||||
* @param req The writeback request.
|
||||
* Perform the given writeback pktuest.
|
||||
* @param pkt The writeback request.
|
||||
*/
|
||||
void doWriteback(Packet * &pkt);
|
||||
|
||||
/**
|
||||
* Returns true if there are outstanding requests.
|
||||
* @return True if there are outstanding requests.
|
||||
* Returns true if there are outstanding pktuests.
|
||||
* @return True if there are outstanding pktuests.
|
||||
*/
|
||||
bool havePending();
|
||||
|
||||
/**
|
||||
* Add a target to the given MSHR. This assumes it is in the miss queue.
|
||||
* @param mshr The mshr to add a target to.
|
||||
* @param req The target to add.
|
||||
* @param pkt The target to add.
|
||||
*/
|
||||
void addTarget(MSHR *mshr, Packet * &pkt)
|
||||
{
|
||||
|
|
22
src/mem/cache/miss/mshr.hh
vendored
22
src/mem/cache/miss/mshr.hh
vendored
|
@ -44,7 +44,7 @@ class MSHR;
|
|||
|
||||
/**
|
||||
* Miss Status and handling Register. This class keeps all the information
|
||||
* needed to handle a cache miss including a list of target requests.
|
||||
* needed to handle a cache miss including a list of target pktuests.
|
||||
*/
|
||||
class MSHR {
|
||||
public:
|
||||
|
@ -63,15 +63,15 @@ class MSHR {
|
|||
Addr addr;
|
||||
/** Adress space id of the miss. */
|
||||
short asid;
|
||||
/** True if the request has been sent to the bus. */
|
||||
/** True if the pktuest has been sent to the bus. */
|
||||
bool inService;
|
||||
/** Thread number of the miss. */
|
||||
int threadNum;
|
||||
/** The request that is forwarded to the next level of the hierarchy. */
|
||||
/** The pktuest that is forwarded to the next level of the hierarchy. */
|
||||
Packet * pkt;
|
||||
/** The number of currently allocated targets. */
|
||||
short ntargets;
|
||||
/** The original requesting command. */
|
||||
/** The original pktuesting command. */
|
||||
Packet::Command originalCmd;
|
||||
/** Order number of assigned by the miss queue. */
|
||||
uint64_t order;
|
||||
|
@ -88,24 +88,24 @@ class MSHR {
|
|||
Iterator allocIter;
|
||||
|
||||
private:
|
||||
/** List of all requests that match the address */
|
||||
/** List of all pktuests that match the address */
|
||||
TargetList targets;
|
||||
|
||||
public:
|
||||
/**
|
||||
* Allocate a miss to this MSHR.
|
||||
* @param cmd The requesting command.
|
||||
* @param cmd The pktuesting command.
|
||||
* @param addr The address of the miss.
|
||||
* @param asid The address space id of the miss.
|
||||
* @param size The number of bytes to request.
|
||||
* @param req The original miss.
|
||||
* @param size The number of bytes to pktuest.
|
||||
* @param pkt The original miss.
|
||||
*/
|
||||
void allocate(Packet::Command cmd, Addr addr, int asid, int size,
|
||||
Packet * &pkt);
|
||||
|
||||
/**
|
||||
* Allocate this MSHR as a buffer for the given request.
|
||||
* @param target The memory request to buffer.
|
||||
* Allocate this MSHR as a buffer for the given pktuest.
|
||||
* @param target The memory pktuest to buffer.
|
||||
*/
|
||||
void allocateAsBuffer(Packet * &target);
|
||||
|
||||
|
@ -115,7 +115,7 @@ public:
|
|||
void deallocate();
|
||||
|
||||
/**
|
||||
* Add a request to the list of targets.
|
||||
* Add a pktuest to the list of targets.
|
||||
* @param target The target.
|
||||
*/
|
||||
void allocateTarget(Packet * &target);
|
||||
|
|
34
src/mem/cache/miss/mshr_queue.hh
vendored
34
src/mem/cache/miss/mshr_queue.hh
vendored
|
@ -39,7 +39,7 @@
|
|||
#include "mem/cache/miss/mshr.hh"
|
||||
|
||||
/**
|
||||
* A Class for maintaining a list of pending and allocated memory requests.
|
||||
* A Class for maintaining a list of pending and allocated memory pktuests.
|
||||
*/
|
||||
class MSHRQueue {
|
||||
private:
|
||||
|
@ -55,7 +55,7 @@ class MSHRQueue {
|
|||
// Parameters
|
||||
/**
|
||||
* The total number of MSHRs in this queue. This number is set as the
|
||||
* number of MSHRs requested plus (numReserve - 1). This allows for
|
||||
* number of MSHRs pktuested plus (numReserve - 1). This allows for
|
||||
* the same number of effective MSHRs while still maintaining the reserve.
|
||||
*/
|
||||
const int numMSHRs;
|
||||
|
@ -103,16 +103,16 @@ class MSHRQueue {
|
|||
bool findMatches(Addr addr, int asid, std::vector<MSHR*>& matches) const;
|
||||
|
||||
/**
|
||||
* Find any pending requests that overlap the given request.
|
||||
* @param req The request to find.
|
||||
* Find any pending pktuests that overlap the given request.
|
||||
* @param pkt The request to find.
|
||||
* @return A pointer to the earliest matching MSHR.
|
||||
*/
|
||||
MSHR* findPending(Packet * &pkt) const;
|
||||
|
||||
/**
|
||||
* Allocates a new MSHR for the request and size. This places the request
|
||||
* Allocates a new MSHR for the pktuest and size. This places the request
|
||||
* as the first target in the MSHR.
|
||||
* @param req The request to handle.
|
||||
* @param pkt The request to handle.
|
||||
* @param size The number in bytes to fetch from memory.
|
||||
* @return The a pointer to the MSHR allocated.
|
||||
*
|
||||
|
@ -121,12 +121,12 @@ class MSHRQueue {
|
|||
MSHR* allocate(Packet * &pkt, int size = 0);
|
||||
|
||||
/**
|
||||
* Allocate a read request for the given address, and places the given
|
||||
* Allocate a read pktuest for the given address, and places the given
|
||||
* target on the target list.
|
||||
* @param addr The address to fetch.
|
||||
* @param asid The address space for the fetch.
|
||||
* @param size The number of bytes to request.
|
||||
* @param target The first target for the request.
|
||||
* @param size The number of bytes to pktuest.
|
||||
* @param target The first target for the pktuest.
|
||||
* @return Pointer to the new MSHR.
|
||||
*/
|
||||
MSHR* allocateFetch(Addr addr, int asid, int size, Packet * &target);
|
||||
|
@ -135,7 +135,7 @@ class MSHRQueue {
|
|||
* Allocate a target list for the given address.
|
||||
* @param addr The address to fetch.
|
||||
* @param asid The address space for the fetch.
|
||||
* @param size The number of bytes to request.
|
||||
* @param size The number of bytes to pktuest.
|
||||
* @return Pointer to the new MSHR.
|
||||
*/
|
||||
MSHR* allocateTargetList(Addr addr, int asid, int size);
|
||||
|
@ -151,7 +151,7 @@ class MSHRQueue {
|
|||
* Allocates a target to the given MSHR. Used to keep track of the number
|
||||
* of outstanding targets.
|
||||
* @param mshr The MSHR to allocate the target to.
|
||||
* @param req The target request.
|
||||
* @param pkt The target request.
|
||||
*/
|
||||
void allocateTarget(MSHR* mshr, Packet * &pkt)
|
||||
{
|
||||
|
@ -181,22 +181,22 @@ class MSHRQueue {
|
|||
void markInService(MSHR* mshr);
|
||||
|
||||
/**
|
||||
* Mark an in service mshr as pending, used to resend a request.
|
||||
* Mark an in service mshr as pending, used to resend a pktuest.
|
||||
* @param mshr The MSHR to resend.
|
||||
* @param cmd The command to resend.
|
||||
*/
|
||||
void markPending(MSHR* mshr, Packet::Command cmd);
|
||||
|
||||
/**
|
||||
* Squash outstanding requests with the given thread number. If a request
|
||||
* Squash outstanding pktuests with the given thread number. If a request
|
||||
* is in service, just squashes the targets.
|
||||
* @param req->getThreadNum()ber The thread to squash.
|
||||
* @param threadNum The thread to squash.
|
||||
*/
|
||||
void squash(int threadNum);
|
||||
|
||||
/**
|
||||
* Returns true if the pending list is not empty.
|
||||
* @return True if there are outstanding requests.
|
||||
* @return True if there are outstanding pktuests.
|
||||
*/
|
||||
bool havePending() const
|
||||
{
|
||||
|
@ -213,8 +213,8 @@ class MSHRQueue {
|
|||
}
|
||||
|
||||
/**
|
||||
* Returns the request at the head of the pendingList.
|
||||
* @return The next request to service.
|
||||
* Returns the pktuest at the head of the pendingList.
|
||||
* @return The next pktuest to service.
|
||||
*/
|
||||
Packet * getReq() const
|
||||
{
|
||||
|
|
6
src/mem/cache/tags/fa_lru.hh
vendored
6
src/mem/cache/tags/fa_lru.hh
vendored
|
@ -193,7 +193,7 @@ public:
|
|||
/**
|
||||
* Find the block in the cache and update the replacement data. Returns
|
||||
* the access latency and the in cache flags as a side effect
|
||||
* @param req The req whose block to find
|
||||
* @param pkt The req whose block to find
|
||||
* @param lat The latency of the access.
|
||||
* @param inCache The FALRUBlk::inCache flags.
|
||||
* @return Pointer to the cache block.
|
||||
|
@ -210,7 +210,7 @@ public:
|
|||
|
||||
/**
|
||||
* Find a replacement block for the address provided.
|
||||
* @param req The request to a find a replacement candidate for.
|
||||
* @param pkt The request to a find a replacement candidate for.
|
||||
* @param writebacks List for any writebacks to be performed.
|
||||
* @param compress_blocks List of blocks to compress, for adaptive comp.
|
||||
* @return The block to place the replacement in.
|
||||
|
@ -328,7 +328,7 @@ public:
|
|||
* @param source The block aligned source address.
|
||||
* @param dest The block aligned destination adddress.
|
||||
* @param asid The address space ID.
|
||||
* @param writebacks List for any generated writeback requests.
|
||||
* @param writebacks List for any generated writeback pktuests.
|
||||
*/
|
||||
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks)
|
||||
{
|
||||
|
|
10
src/mem/cache/tags/iic.hh
vendored
10
src/mem/cache/tags/iic.hh
vendored
|
@ -454,7 +454,7 @@ class IIC : public BaseTags
|
|||
/**
|
||||
* Find the block and update the replacement data. This call also returns
|
||||
* the access latency as a side effect.
|
||||
* @param req The req whose block to find
|
||||
* @param pkt The req whose block to find
|
||||
* @param lat The access latency.
|
||||
* @return A pointer to the block found, if any.
|
||||
*/
|
||||
|
@ -470,7 +470,7 @@ class IIC : public BaseTags
|
|||
|
||||
/**
|
||||
* Find a replacement block for the address provided.
|
||||
* @param req The request to a find a replacement candidate for.
|
||||
* @param pkt The request to a find a replacement candidate for.
|
||||
* @param writebacks List for any writebacks to be performed.
|
||||
* @param compress_blocks List of blocks to compress, for adaptive comp.
|
||||
* @return The block to place the replacement in.
|
||||
|
@ -502,14 +502,14 @@ class IIC : public BaseTags
|
|||
* @param source The block-aligned source address.
|
||||
* @param dest The block-aligned destination address.
|
||||
* @param asid The address space DI.
|
||||
* @param writebacks List for any generated writeback requests.
|
||||
* @param writebacks List for any generated writeback pktuests.
|
||||
*/
|
||||
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
|
||||
|
||||
/**
|
||||
* If a block is currently marked copy on write, copy it before writing.
|
||||
* @param req The write request.
|
||||
* @param writebacks List for any generated writeback requests.
|
||||
* @param pkt The write request.
|
||||
* @param writebacks List for any generated writeback pktuests.
|
||||
*/
|
||||
void fixCopy(Packet * &pkt, PacketList &writebacks);
|
||||
|
||||
|
|
6
src/mem/cache/tags/lru.hh
vendored
6
src/mem/cache/tags/lru.hh
vendored
|
@ -170,7 +170,7 @@ public:
|
|||
/**
|
||||
* Finds the given address in the cache and update replacement data.
|
||||
* Returns the access latency as a side effect.
|
||||
* @param req The request whose block to find.
|
||||
* @param pkt The request whose block to find.
|
||||
* @param lat The access latency.
|
||||
* @return Pointer to the cache block if found.
|
||||
*/
|
||||
|
@ -196,7 +196,7 @@ public:
|
|||
|
||||
/**
|
||||
* Find a replacement block for the address provided.
|
||||
* @param req The request to a find a replacement candidate for.
|
||||
* @param pkt The request to a find a replacement candidate for.
|
||||
* @param writebacks List for any writebacks to be performed.
|
||||
* @param compress_blocks List of blocks to compress, for adaptive comp.
|
||||
* @return The block to place the replacement in.
|
||||
|
@ -307,7 +307,7 @@ public:
|
|||
* @param source The block-aligned source address.
|
||||
* @param dest The block-aligned destination address.
|
||||
* @param asid The address space DI.
|
||||
* @param writebacks List for any generated writeback requests.
|
||||
* @param writebacks List for any generated writeback pktuests.
|
||||
*/
|
||||
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
|
||||
|
||||
|
|
14
src/mem/cache/tags/split.hh
vendored
14
src/mem/cache/tags/split.hh
vendored
|
@ -71,13 +71,13 @@ class Split : public BaseTags
|
|||
|
||||
Addr blkMask;
|
||||
|
||||
/** Number of NIC requests that hit in the NIC partition */
|
||||
/** Number of NIC pktuests that hit in the NIC partition */
|
||||
Stats::Scalar<> NR_NP_hits;
|
||||
/** Number of NIC requests that hit in the CPU partition */
|
||||
/** Number of NIC pktuests that hit in the CPU partition */
|
||||
Stats::Scalar<> NR_CP_hits;
|
||||
/** Number of CPU requests that hit in the NIC partition */
|
||||
/** Number of CPU pktuests that hit in the NIC partition */
|
||||
Stats::Scalar<> CR_NP_hits;
|
||||
/** Number of CPU requests that hit in the CPU partition */
|
||||
/** Number of CPU pktuests that hit in the CPU partition */
|
||||
Stats::Scalar<> CR_CP_hits;
|
||||
/** The number of nic replacements (i.e. misses) */
|
||||
Stats::Scalar<> nic_repl;
|
||||
|
@ -203,7 +203,7 @@ class Split : public BaseTags
|
|||
/**
|
||||
* Finds the given address in the cache and update replacement data.
|
||||
* Returns the access latency as a side effect.
|
||||
* @param req The memory request whose block to find
|
||||
* @param pkt The memory request whose block to find
|
||||
* @param lat The access latency.
|
||||
* @return Pointer to the cache block if found.
|
||||
*/
|
||||
|
@ -219,7 +219,7 @@ class Split : public BaseTags
|
|||
|
||||
/**
|
||||
* Find a replacement block for the address provided.
|
||||
* @param req The request to a find a replacement candidate for.
|
||||
* @param pkt The request to a find a replacement candidate for.
|
||||
* @param writebacks List for any writebacks to be performed.
|
||||
* @param compress_blocks List of blocks to compress, for adaptive comp.
|
||||
* @return The block to place the replacement in.
|
||||
|
@ -315,7 +315,7 @@ class Split : public BaseTags
|
|||
* @param source The block-aligned source address.
|
||||
* @param dest The block-aligned destination address.
|
||||
* @param asid The address space DI.
|
||||
* @param writebacks List for any generated writeback requests.
|
||||
* @param writebacks List for any generated writeback pktuests.
|
||||
*/
|
||||
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
|
||||
|
||||
|
|
2
src/mem/cache/tags/split_blk.hh
vendored
2
src/mem/cache/tags/split_blk.hh
vendored
|
@ -47,7 +47,7 @@ class SplitBlk : public CacheBlk {
|
|||
bool isTouched;
|
||||
/** Has this block been used after being brought in? (for LIFO partition) */
|
||||
bool isUsed;
|
||||
/** is this blk a NIC block? (i.e. requested by the NIC) */
|
||||
/** is this blk a NIC block? (i.e. pktuested by the NIC) */
|
||||
bool isNIC;
|
||||
/** timestamp of the arrival of this block into the cache */
|
||||
Tick ts;
|
||||
|
|
6
src/mem/cache/tags/split_lifo.hh
vendored
6
src/mem/cache/tags/split_lifo.hh
vendored
|
@ -203,7 +203,7 @@ public:
|
|||
/**
|
||||
* Finds the given address in the cache and update replacement data.
|
||||
* Returns the access latency as a side effect.
|
||||
* @param req The req whose block to find
|
||||
* @param pkt The req whose block to find
|
||||
* @param lat The access latency.
|
||||
* @return Pointer to the cache block if found.
|
||||
*/
|
||||
|
@ -219,7 +219,7 @@ public:
|
|||
|
||||
/**
|
||||
* Find a replacement block for the address provided.
|
||||
* @param req The request to a find a replacement candidate for.
|
||||
* @param pkt The request to a find a replacement candidate for.
|
||||
* @param writebacks List for any writebacks to be performed.
|
||||
* @param compress_blocks List of blocks to compress, for adaptive comp.
|
||||
* @return The block to place the replacement in.
|
||||
|
@ -330,7 +330,7 @@ public:
|
|||
* @param source The block-aligned source address.
|
||||
* @param dest The block-aligned destination address.
|
||||
* @param asid The address space DI.
|
||||
* @param writebacks List for any generated writeback requests.
|
||||
* @param writebacks List for any generated writeback pktuests.
|
||||
*/
|
||||
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
|
||||
|
||||
|
|
6
src/mem/cache/tags/split_lru.hh
vendored
6
src/mem/cache/tags/split_lru.hh
vendored
|
@ -186,7 +186,7 @@ public:
|
|||
/**
|
||||
* Finds the given address in the cache and update replacement data.
|
||||
* Returns the access latency as a side effect.
|
||||
* @param req The req whose block to find.
|
||||
* @param pkt The req whose block to find.
|
||||
* @param lat The access latency.
|
||||
* @return Pointer to the cache block if found.
|
||||
*/
|
||||
|
@ -202,7 +202,7 @@ public:
|
|||
|
||||
/**
|
||||
* Find a replacement block for the address provided.
|
||||
* @param req The request to a find a replacement candidate for.
|
||||
* @param pkt The request to a find a replacement candidate for.
|
||||
* @param writebacks List for any writebacks to be performed.
|
||||
* @param compress_blocks List of blocks to compress, for adaptive comp.
|
||||
* @return The block to place the replacement in.
|
||||
|
@ -313,7 +313,7 @@ public:
|
|||
* @param source The block-aligned source address.
|
||||
* @param dest The block-aligned destination address.
|
||||
* @param asid The address space DI.
|
||||
* @param writebacks List for any generated writeback requests.
|
||||
* @param writebacks List for any generated writeback pktuests.
|
||||
*/
|
||||
void doCopy(Addr source, Addr dest, int asid, PacketList &writebacks);
|
||||
|
||||
|
|
|
@ -30,7 +30,7 @@
|
|||
|
||||
/**
|
||||
* @file
|
||||
* Base Memory Object decleration.
|
||||
* Base Memory Object declaration.
|
||||
*/
|
||||
|
||||
#ifndef __MEM_MEM_OBJECT_HH__
|
||||
|
|
|
@ -49,7 +49,7 @@
|
|||
class System;
|
||||
|
||||
/**
|
||||
* Page Table Decleration.
|
||||
* Page Table Declaration.
|
||||
*/
|
||||
class PageTable
|
||||
{
|
||||
|
|
|
@ -29,7 +29,8 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @file Port object definitions.
|
||||
* @file
|
||||
* Port object definitions.
|
||||
*/
|
||||
|
||||
#include "base/chunk_generator.hh"
|
||||
|
|
|
@ -30,7 +30,7 @@
|
|||
|
||||
/**
|
||||
* @file
|
||||
* Port Object Decleration. Ports are used to interface memory objects to
|
||||
* Port Object Declaration. Ports are used to interface memory objects to
|
||||
* each other. They will always come in pairs, and we refer to the other
|
||||
* port object as the peer. These are used to make the design more
|
||||
* modular so that a specific interface between every type of objcet doesn't
|
||||
|
|
|
@ -31,7 +31,8 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @file Decleration of a request, the overall memory request consisting of
|
||||
* @file
|
||||
* Declaration of a request, the overall memory request consisting of
|
||||
the parts of the request that are persistent throughout the transaction.
|
||||
*/
|
||||
|
||||
|
|
|
@ -29,7 +29,8 @@
|
|||
*/
|
||||
|
||||
/**
|
||||
* @file Port object definitions.
|
||||
* @file
|
||||
* Port object definitions.
|
||||
*/
|
||||
|
||||
#include "base/chunk_generator.hh"
|
||||
|
|
|
@ -30,7 +30,7 @@
|
|||
|
||||
/**
|
||||
* @file
|
||||
* Virtual Port Object Decleration. These ports incorporate some translation
|
||||
* Virtual Port Object Declaration. These ports incorporate some translation
|
||||
* into their access methods. Thus you can use one to read and write data
|
||||
* to/from virtual addresses.
|
||||
*/
|
||||
|
|
Loading…
Reference in a new issue