includes: sort includes again

This commit is contained in:
Nathan Binkert 2009-05-17 14:34:52 -07:00
parent 709d859530
commit 8d2e51c7f5
99 changed files with 217 additions and 230 deletions

View file

@ -37,8 +37,8 @@ namespace LittleEndianGuest {}
#include "arch/alpha/ipr.hh"
#include "arch/alpha/max_inst_regs.hh"
#include "arch/alpha/types.hh"
#include "config/full_system.hh"
#include "base/types.hh"
#include "config/full_system.hh"
class StaticInstPtr;

View file

@ -33,8 +33,8 @@
#include "arch/alpha/types.hh"
#include "base/misc.hh"
#include "config/full_system.hh"
#include "base/types.hh"
#include "config/full_system.hh"
class ThreadContext;

View file

@ -35,9 +35,9 @@
#include "arch/arm/types.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "config/full_system.hh"
#include "cpu/thread_context.hh"
#include "base/types.hh"
class ThreadContext;

View file

@ -34,8 +34,8 @@
#include "arch/mips/types.hh"
#include "arch/mips/isa_traits.hh"
#include "base/misc.hh"
#include "config/full_system.hh"
#include "base/types.hh"
#include "config/full_system.hh"
class ThreadContext;

View file

@ -36,8 +36,8 @@
#include "arch/mips/types.hh"
#include "arch/mips/mips_core_specific.hh"
#include "config/full_system.hh"
#include "base/types.hh"
#include "config/full_system.hh"
namespace LittleEndianGuest {};

View file

@ -37,11 +37,8 @@
#include "arch/mips/types.hh"
#include "arch/mips/isa_traits.hh"
#include "base/misc.hh"
#include "config/full_system.hh"
//XXX This is needed for size_t. We should use something other than size_t
//#include "kern/linux/linux.hh"
#include "base/types.hh"
#include "config/full_system.hh"
#include "cpu/thread_context.hh"
class ThreadContext;

View file

@ -35,8 +35,8 @@
#include "arch/sparc/types.hh"
#include "arch/sparc/max_inst_regs.hh"
#include "arch/sparc/sparc_traits.hh"
#include "config/full_system.hh"
#include "base/types.hh"
#include "config/full_system.hh"
class StaticInstPtr;

View file

@ -33,8 +33,8 @@
#include "arch/sparc/types.hh"
#include "base/misc.hh"
#include "cpu/thread_context.hh"
#include "base/types.hh"
#include "cpu/thread_context.hh"
class ThreadContext;

View file

@ -32,6 +32,8 @@
#ifndef __ARCH_SPARC_REGFILE_HH__
#define __ARCH_SPARC_REGFILE_HH__
#include <string>
#include "arch/sparc/floatregfile.hh"
#include "arch/sparc/intregfile.hh"
#include "arch/sparc/isa_traits.hh"
@ -39,8 +41,6 @@
#include "arch/sparc/types.hh"
#include "base/types.hh"
#include <string>
class Checkpoint;
namespace SparcISA

View file

@ -58,12 +58,12 @@
#ifndef __ARCH_X86_BIOS_ACPI_HH__
#define __ARCH_X86_BIOS_ACPI_HH__
#include <string>
#include <vector>
#include "base/types.hh"
#include "sim/sim_object.hh"
#include <vector>
#include <string>
class Port;
class X86ACPIRSDPParams;

View file

@ -58,13 +58,13 @@
#ifndef __ARCH_X86_BIOS_E820_HH__
#define __ARCH_X86_BIOS_E820_HH__
#include <vector>
#include "base/types.hh"
#include "params/X86E820Entry.hh"
#include "params/X86E820Table.hh"
#include "base/types.hh"
#include "sim/sim_object.hh"
#include <vector>
class Port;
namespace X86ISA

View file

@ -58,9 +58,9 @@
#include "arch/x86/bios/intelmp.hh"
#include "arch/x86/isa_traits.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "mem/port.hh"
#include "sim/byteswap.hh"
#include "base/types.hh"
// Config entry types
#include "params/X86IntelMPBaseConfigEntry.hh"

View file

@ -87,12 +87,12 @@
#include "arch/x86/bios/smbios.hh"
#include "arch/x86/isa_traits.hh"
#include "base/types.hh"
#include "mem/port.hh"
#include "params/X86SMBiosBiosInformation.hh"
#include "params/X86SMBiosSMBiosStructure.hh"
#include "params/X86SMBiosSMBiosTable.hh"
#include "sim/byteswap.hh"
#include "base/types.hh"
using namespace std;

View file

@ -91,9 +91,9 @@
#include <string>
#include <vector>
#include "base/types.hh"
#include "enums/Characteristic.hh"
#include "enums/ExtCharacteristic.hh"
#include "base/types.hh"
#include "sim/sim_object.hh"
class FunctionalPort;

View file

@ -33,10 +33,10 @@
#include "arch/x86/x86_traits.hh"
#include "base/bitunion.hh"
#include "base/types.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/request.hh"
#include "base/types.hh"
namespace X86ISA
{

View file

@ -88,13 +88,13 @@
#ifndef __ARCH_X86_MISCREGFILE_HH__
#define __ARCH_X86_MISCREGFILE_HH__
#include <string>
#include "arch/x86/faults.hh"
#include "arch/x86/miscregs.hh"
#include "arch/x86/types.hh"
#include "base/types.hh"
#include <string>
class Checkpoint;
namespace X86ISA

View file

@ -61,9 +61,9 @@
#include <iostream>
#include <string>
#include "base/types.hh"
#include "base/bitunion.hh"
#include "base/misc.hh"
#include "base/types.hh"
class Checkpoint;

View file

@ -62,10 +62,10 @@
#include "arch/x86/pagetable.hh"
#include "arch/x86/tlb.hh"
#include "base/types.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "params/X86PagetableWalker.hh"
#include "base/types.hh"
class ThreadContext;

View file

@ -59,8 +59,8 @@
#include "arch/x86/predecoder.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "base/types.hh"
#include "cpu/thread_context.hh"
namespace X86ISA
{

View file

@ -58,6 +58,8 @@
#ifndef __ARCH_X86_REGFILE_HH__
#define __ARCH_X86_REGFILE_HH__
#include <string>
#include "arch/x86/floatregfile.hh"
#include "arch/x86/intregfile.hh"
#include "arch/x86/isa_traits.hh"
@ -65,8 +67,6 @@
#include "arch/x86/types.hh"
#include "base/types.hh"
#include <string>
class Checkpoint;
class EventManager;

View file

@ -61,9 +61,9 @@
#include "arch/x86/types.hh"
#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "config/full_system.hh"
#include "cpu/thread_context.hh"
#include "base/types.hh"
class ThreadContext;

View file

@ -58,7 +58,7 @@
#ifndef __ARCH_X86_X86TRAITS_HH__
#define __ARCH_X86_X86TRAITS_HH__
#include <assert.h>
#include <cassert>
#include "base/types.hh"

View file

@ -31,19 +31,20 @@
#ifndef __BASE__CP_ANNOTATE_HH__
#define __BASE__CP_ANNOTATE_HH__
#include "base/loader/symtab.hh"
#include "config/cp_annotate.hh"
#include "base/types.hh"
#include "sim/serialize.hh"
#include "sim/startup.hh"
#include "sim/system.hh"
#include <string>
#include <list>
#include <vector>
#include <map>
#include "base/hashmap.hh"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "config/cp_annotate.hh"
#include "sim/serialize.hh"
#include "sim/startup.hh"
#include "sim/system.hh"
#if CP_ANNOTATE
#include "params/CPA.hh"
#endif

View file

@ -33,8 +33,8 @@
#include <string>
#include "base/types.hh"
#include "base/crc.hh"
#include "base/types.hh"
#define ETHER_CRC_POLY_LE 0xedb88320
#define ETHER_CRC_POLY_BE 0x04c11db6

View file

@ -32,8 +32,8 @@
#include <string>
#include "base/cprintf.hh"
#include "base/types.hh"
#include "base/inet.hh"
#include "base/types.hh"
using namespace std;
namespace Net {

View file

@ -38,8 +38,8 @@
#include <vector>
#include "base/range.hh"
#include "dev/etherpkt.hh"
#include "base/types.hh"
#include "dev/etherpkt.hh"
#include "dnet/os.h"
#include "dnet/eth.h"

View file

@ -28,10 +28,10 @@
* Authors: Nathan Binkert
*/
#ifndef __INTMATH_HH__
#define __INTMATH_HH__
#ifndef __BASE_INTMATH_HH__
#define __BASE_INTMATH_HH__
#include <assert.h>
#include <cassert>
#include "base/types.hh"
@ -229,4 +229,4 @@ hex2Int(char c)
return 0;
}
#endif // __INTMATH_HH__
#endif // __BASE_INTMATH_HH__

View file

@ -38,8 +38,8 @@
#include "base/misc.hh"
#include "base/output.hh"
#include "base/trace.hh"
#include "base/varargs.hh"
#include "base/types.hh"
#include "base/varargs.hh"
#include "sim/core.hh"
using namespace std;

View file

@ -38,10 +38,10 @@
#include <signal.h>
#include <unistd.h>
#include "sim/async.hh"
#include "base/types.hh"
#include "base/misc.hh"
#include "base/pollevent.hh"
#include "base/types.hh"
#include "sim/async.hh"
#include "sim/core.hh"
#include "sim/serialize.hh"

View file

@ -32,8 +32,9 @@
#ifndef __RES_LIST_HH__
#define __RES_LIST_HH__
#include <cassert>
#include "base/cprintf.hh"
#include <assert.h>
#define DEBUG_REMOVE 0

View file

@ -63,10 +63,10 @@
#include "base/cprintf.hh"
#include "base/intmath.hh"
#include "base/refcnt.hh"
#include "base/str.hh"
#include "base/stats/info.hh"
#include "base/stats/types.hh"
#include "base/stats/visit.hh"
#include "base/str.hh"
#include "base/types.hh"
class Callback;

View file

@ -42,8 +42,8 @@
#include "base/stats/mysql_run.hh"
#include "base/stats/types.hh"
#include "base/str.hh"
#include "base/userinfo.hh"
#include "base/types.hh"
#include "base/userinfo.hh"
using namespace std;

View file

@ -32,8 +32,8 @@
#include "base/statistics.hh"
#include "base/stats/output.hh"
#include "sim/eventq.hh"
#include "base/types.hh"
#include "sim/eventq.hh"
using namespace std;

View file

@ -29,14 +29,14 @@
* Nathan Binkert
*/
#ifndef __EXETRACE_HH__
#define __EXETRACE_HH__
#ifndef __CPU_EXETRACE_HH__
#define __CPU_EXETRACE_HH__
#include "base/trace.hh"
#include "cpu/static_inst.hh"
#include "base/types.hh"
#include "sim/insttracer.hh"
#include "cpu/static_inst.hh"
#include "params/ExeTracer.hh"
#include "sim/insttracer.hh"
class ThreadContext;
@ -88,4 +88,4 @@ class ExeTracer : public InstTracer
/* namespace Trace */ }
#endif // __EXETRACE_HH__
#endif // __CPU_EXETRACE_HH__

View file

@ -36,10 +36,10 @@
#include "arch/faults.hh"
#include "arch/isa_traits.hh"
#include "base/types.hh"
#include "cpu/inorder/inorder_dyn_inst.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inst_seq.hh"
#include "base/types.hh"
/** Struct that defines the information passed from in between stages */
/** This information mainly goes forward through the pipeline. */

View file

@ -29,19 +29,18 @@
* Authors: Korey Sewell
*/
#ifndef __INORDERTRACE_HH__
#define __INORDERTRACE_HH__
#ifndef __CPU_INORDER_INORDER_TRACE_HH__
#define __CPU_INORDER_INORDER_TRACE_HH__
#include "base/trace.hh"
#include "cpu/static_inst.hh"
#include "base/types.hh"
#include "sim/insttracer.hh"
#include "params/InOrderTrace.hh"
#include "cpu/exetrace.hh"
#include "cpu/static_inst.hh"
#include "params/InOrderTrace.hh"
#include "sim/insttracer.hh"
class ThreadContext;
namespace Trace {
class InOrderTraceRecord : public ExeTracerRecord
@ -95,4 +94,4 @@ class InOrderTrace : public InstTracer
/* namespace Trace */ }
#endif // __EXETRACE_HH__
#endif // __CPU_INORDER_INORDER_TRACE_HH__

View file

@ -29,18 +29,17 @@
* Nathan Binkert
*/
#ifndef __INTELTRACE_HH__
#define __INTELTRACE_HH__
#ifndef __CPU_INTELTRACE_HH__
#define __CPU_INTELTRACE_HH__
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "params/IntelTrace.hh"
#include "base/types.hh"
#include "sim/insttracer.hh"
class ThreadContext;
namespace Trace {
class IntelTraceRecord : public InstRecord
@ -85,4 +84,4 @@ class IntelTrace : public InstTracer
/* namespace Trace */ }
#endif // __EXETRACE_HH__
#endif // __CPU_INTELTRACE_HH__

View file

@ -29,13 +29,13 @@
* Nathan Binkert
*/
#ifndef __LEGIONTRACE_HH__
#define __LEGIONTRACE_HH__
#ifndef __CPU_LEGIONTRACE_HH__
#define __CPU_LEGIONTRACE_HH__
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "params/LegionTrace.hh"
#include "base/types.hh"
#include "sim/insttracer.hh"
class ThreadContext;
@ -78,4 +78,4 @@ class LegionTrace : public InstTracer
/* namespace Trace */ }
#endif // __LEGIONTRACE_HH__
#endif // __CPU_LEGIONTRACE_HH__

View file

@ -29,19 +29,18 @@
* Nathan Binkert
*/
#ifndef __NATIVETRACE_HH__
#define __NATIVETRACE_HH__
#ifndef __CPU_NATIVETRACE_HH__
#define __CPU_NATIVETRACE_HH__
#include "base/trace.hh"
#include "cpu/static_inst.hh"
#include "base/types.hh"
#include "sim/insttracer.hh"
#include "arch/x86/intregs.hh"
#include "arch/x86/floatregs.hh"
#include "arch/x86/intregs.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "sim/insttracer.hh"
class ThreadContext;
namespace Trace {
class NativeTrace;
@ -213,4 +212,4 @@ class NativeTrace : public InstTracer
/* namespace Trace */ }
#endif // __EXETRACE_HH__
#endif // __CPU_NATIVETRACE_HH__

View file

@ -31,11 +31,11 @@
#ifndef __CPU_O3_2BIT_LOCAL_PRED_HH__
#define __CPU_O3_2BIT_LOCAL_PRED_HH__
#include "cpu/o3/sat_counter.hh"
#include "base/types.hh"
#include <vector>
#include "base/types.hh"
#include "cpu/o3/sat_counter.hh"
/**
* Implements a local predictor that uses the PC to index into a table of
* counters. Note that any time a pointer to the bp_history is given, it

View file

@ -31,18 +31,16 @@
#ifndef __CPU_O3_BPRED_UNIT_HH__
#define __CPU_O3_BPRED_UNIT_HH__
#include "base/statistics.hh"
#include "cpu/inst_seq.hh"
#include <list>
#include "base/statistics.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/2bit_local_pred.hh"
#include "cpu/o3/btb.hh"
#include "cpu/o3/ras.hh"
#include "cpu/o3/tournament_pred.hh"
#include "base/types.hh"
#include <list>
class DerivO3CPUParams;
/**

View file

@ -33,9 +33,9 @@
#include <vector>
#include "sim/faults.hh"
#include "cpu/inst_seq.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
#include "sim/faults.hh"
// Typedef for physical register index type. Although the Impl would be the
// most likely location for this, there are a few classes that need this

View file

@ -32,17 +32,17 @@
#include <algorithm>
#include <cstring>
#include "config/use_checker.hh"
#include "arch/isa_traits.hh"
#include "arch/utility.hh"
#include "base/types.hh"
#include "config/use_checker.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/exetrace.hh"
#include "cpu/o3/fetch.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "params/DerivO3CPU.hh"
#include "sim/byteswap.hh"
#include "base/types.hh"
#include "sim/core.hh"
#if FULL_SYSTEM
@ -51,8 +51,6 @@
#include "sim/system.hh"
#endif // FULL_SYSTEM
#include "params/DerivO3CPU.hh"
template<class Impl>
void
DefaultFetch<Impl>::IcachePort::setPeer(Port *port)

View file

@ -38,11 +38,11 @@
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/dep_graph.hh"
#include "cpu/op_class.hh"
#include "sim/eventq.hh"
#include "base/types.hh"
class DerivO3CPUParams;
class FUPool;

View file

@ -31,9 +31,10 @@
#ifndef __CPU_O3_RAS_HH__
#define __CPU_O3_RAS_HH__
#include "base/types.hh"
#include <vector>
#include "base/types.hh"
/** Return address stack class, implements a simple RAS. */
class ReturnAddrStack
{

View file

@ -36,8 +36,8 @@
#include <utility>
#include <vector>
#include "cpu/inst_seq.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
struct ltseqnum {
bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const

View file

@ -31,10 +31,11 @@
#ifndef __CPU_O3_TOURNAMENT_PRED_HH__
#define __CPU_O3_TOURNAMENT_PRED_HH__
#include "cpu/o3/sat_counter.hh"
#include "base/types.hh"
#include <vector>
#include "base/types.hh"
#include "cpu/o3/sat_counter.hh"
/**
* Implements a tournament branch predictor, hopefully identical to the one
* used in the 21264. It has a local predictor, which uses a local history

View file

@ -35,8 +35,8 @@
#include <list>
#include <utility>
#include "cpu/inst_seq.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
/**
* Simple class to hold onto a list of pairs, each pair having a memory

View file

@ -38,8 +38,8 @@
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "cpu/inst_seq.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
class FUPool;
class MemInterface;

View file

@ -31,8 +31,8 @@
#ifndef __CPU_OZONE_NULL_PREDICTOR_HH__
#define __CPU_OZONE_NULL_PREDICTOR_HH__
#include "cpu/inst_seq.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh"
template <class Impl>
class NullPredictor

View file

@ -28,10 +28,10 @@
* Authors: Steve Reinhardt
*/
#include "arch/utility.hh"
#include "arch/faults.hh"
#include "base/cprintf.hh"
#include "arch/utility.hh"
#include "base/cp_annotate.hh"
#include "base/cprintf.hh"
#include "base/inifile.hh"
#include "base/loader/symtab.hh"
#include "base/misc.hh"
@ -39,6 +39,7 @@
#include "base/range.hh"
#include "base/stats/events.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "cpu/profile.hh"
@ -49,9 +50,9 @@
#include "cpu/thread_context.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "params/BaseSimpleCPU.hh"
#include "sim/byteswap.hh"
#include "sim/debug.hh"
#include "base/types.hh"
#include "sim/sim_events.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
@ -67,8 +68,6 @@
#include "mem/mem_object.hh"
#endif // FULL_SYSTEM
#include "params/BaseSimpleCPU.hh"
using namespace std;
using namespace TheISA;

View file

@ -35,13 +35,13 @@
#include "arch/isa_traits.hh"
#include "arch/regfile.hh"
#include "arch/tlb.hh"
#include "base/types.hh"
#include "config/full_system.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/eventq.hh"
#include "base/types.hh"
#include "sim/serialize.hh"
class BaseCPU;

View file

@ -36,14 +36,14 @@
#include "arch/isa_traits.hh"
#include "arch/utility.hh"
#include "sim/faults.hh"
#include "base/bitfield.hh"
#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/refcnt.hh"
#include "base/types.hh"
#include "cpu/op_class.hh"
#include "sim/faults.hh"
#include "base/types.hh"
#include "sim/faults.hh"
// forward declarations
struct AlphaSimpleImpl;

View file

@ -33,12 +33,12 @@
#include "arch/regfile.hh"
#include "arch/types.hh"
#include "base/types.hh"
#include "config/full_system.hh"
#include "mem/request.hh"
#include "sim/faults.hh"
#include "base/types.hh"
#include "sim/serialize.hh"
#include "sim/byteswap.hh"
#include "sim/faults.hh"
#include "sim/serialize.hh"
// @todo: Figure out a more architecture independent way to obtain the ITB and
// DTB pointers.

View file

@ -36,10 +36,10 @@
#define __DEV_ALPHA_BACKDOOR_HH__
#include "base/range.hh"
#include "base/types.hh"
#include "dev/alpha/access.h"
#include "dev/io_device.hh"
#include "params/AlphaBackdoor.hh"
#include "base/types.hh"
#include "sim/sim_object.hh"
class BaseCPU;

View file

@ -35,14 +35,14 @@
#ifndef __DEV_ETHERLINK_HH__
#define __DEV_ETHERLINK_HH__
#include "dev/etherobject.hh"
#include "base/types.hh"
#include "dev/etherint.hh"
#include "dev/etherobject.hh"
#include "dev/etherpkt.hh"
#include "params/EtherLink.hh"
#include "sim/eventq.hh"
#include "base/types.hh"
#include "sim/sim_object.hh"
#include "params/EtherLink.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
class EtherDump;
class Checkpoint;

View file

@ -36,9 +36,9 @@
#ifndef __ETHERPKT_HH__
#define __ETHERPKT_HH__
#include <cassert>
#include <iosfwd>
#include <memory>
#include <assert.h>
#include "base/refcnt.hh"
#include "base/types.hh"

View file

@ -37,8 +37,8 @@
#include <iostream>
#include "base/bitunion.hh"
#include "sim/eventq.hh"
#include "base/types.hh"
#include "sim/eventq.hh"
#include "sim/serialize.hh"
/** Programmable Interval Timer (Intel 8254) */

View file

@ -36,10 +36,10 @@
#define __DEV_MIPS_BACKDOOR_HH__
#include "base/range.hh"
#include "dev/mips/access.h"
#include "dev/io_device.hh"
#include "params/MipsBackdoor.hh"
#include "base/types.hh"
#include "dev/io_device.hh"
#include "dev/mips/access.h"
#include "params/MipsBackdoor.hh"
#include "sim/sim_object.hh"
class BaseCPU;

View file

@ -38,6 +38,7 @@
#include "base/debug.hh"
#include "base/inet.hh"
#include "base/types.hh"
#include "cpu/thread_context.hh"
#include "dev/etherlink.hh"
#include "dev/ns_gige.hh"
@ -45,7 +46,6 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/NSGigE.hh"
#include "base/types.hh"
#include "sim/system.hh"
const char *NsRxStateStrings[] =

View file

@ -35,14 +35,14 @@
#include "arch/vtophys.hh"
#include "base/debug.hh"
#include "base/inet.hh"
#include "cpu/thread_context.hh"
#include "base/types.hh"
#include "cpu/intr_control.hh"
#include "cpu/thread_context.hh"
#include "dev/etherlink.hh"
#include "dev/sinic.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/eventq.hh"
#include "base/types.hh"
#include "sim/stats.hh"
using namespace std;

View file

@ -31,7 +31,7 @@
#ifndef __DEV_X86_INTDEV_HH__
#define __DEV_X86_INTDEV_HH__
#include <assert.h>
#include <cassert>
#include <string>
#include "arch/x86/x86_traits.hh"

View file

@ -28,7 +28,7 @@
* Authors: Gabe Black
*/
#include <assert.h>
#include <cassert>
#include "dev/x86/pc.hh"
#include "dev/x86/south_bridge.hh"

View file

@ -31,16 +31,16 @@
#include <sys/types.h>
#include <algorithm>
#include "base/cprintf.hh"
#include "base/trace.hh"
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"
#include "kern/tru64/mbuf.hh"
#include "base/types.hh"
#include "sim/system.hh"
#include "sim/arguments.hh"
#include "arch/isa_traits.hh"
#include "arch/vtophys.hh"
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/thread_context.hh"
#include "kern/tru64/mbuf.hh"
#include "sim/arguments.hh"
#include "sim/system.hh"
using namespace TheISA;

View file

@ -31,8 +31,8 @@
#ifndef __MBUF_HH__
#define __MBUF_HH__
#include "base/types.hh"
#include "arch/isa_traits.hh"
#include "base/types.hh"
namespace tru64 {

View file

@ -41,16 +41,16 @@
#include <set>
#include <list>
#include "base/range.hh"
#include "base/hashmap.hh"
#include "base/range.hh"
#include "base/range_map.hh"
#include "base/types.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
#include "mem/request.hh"
#include "sim/eventq.hh"
#include "params/Bus.hh"
#include "sim/eventq.hh"
class Bus : public MemObject
{

View file

@ -37,18 +37,15 @@
* Cache definitions.
*/
#include "base/types.hh"
#include "base/fast_alloc.hh"
#include "base/misc.hh"
#include "base/range.hh"
#include "mem/cache/cache.hh"
#include "base/types.hh"
#include "mem/cache/blk.hh"
#include "mem/cache/cache.hh"
#include "mem/cache/mshr.hh"
#include "mem/cache/prefetch/base.hh"
#include "sim/sim_exit.hh" // for SimExitEvent
#include "sim/sim_exit.hh"
template<class TagStore>
Cache<TagStore>::Cache(const Params *p, TagStore *tags, BasePrefetcher *pf)

10
src/mem/cache/mshr.cc vendored
View file

@ -34,16 +34,16 @@
* Miss Status and Handling Register (MSHR) definitions.
*/
#include <assert.h>
#include <algorithm>
#include <cassert>
#include <string>
#include <vector>
#include <algorithm>
#include "mem/cache/mshr.hh"
#include "sim/core.hh" // for curTick
#include "base/types.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "mem/cache/cache.hh"
#include "mem/cache/mshr.hh"
#include "sim/core.hh"
using namespace std;

View file

@ -33,13 +33,12 @@
* Definitions a fully associative LRU tagstore.
*/
#include <cassert>
#include <sstream>
#include <assert.h>
#include "mem/cache/tags/fa_lru.hh"
#include "base/intmath.hh"
#include "base/misc.hh"
#include "mem/cache/tags/fa_lru.hh"
using namespace std;

View file

@ -33,15 +33,15 @@
* Declaration of a fully associative LRU tag store.
*/
#ifndef __FA_LRU_HH__
#define __FA_LRU_HH__
#ifndef __MEM_CACHE_TAGS_FA_LRU_HH__
#define __MEM_CACHE_TAGS_FA_LRU_HH__
#include <list>
#include "mem/cache/blk.hh"
#include "mem/packet.hh"
#include "base/hashmap.hh"
#include "mem/cache/blk.hh"
#include "mem/cache/tags/base.hh"
#include "mem/packet.hh"
/**
* A fully associative cache block.
@ -281,4 +281,4 @@ public:
}
};
#endif
#endif // __MEM_CACHE_TAGS_FA_LRU_HH__

View file

@ -37,10 +37,10 @@
#include <string>
#include "base/misc.hh"
#include "base/types.hh"
#include "mem/cache/tags/iic.hh"
#include "mem/cache/tags/iic_repl/gen.hh"
#include "params/GenRepl.hh"
#include "base/types.hh"
using namespace std;

View file

@ -41,11 +41,10 @@
#include <string>
#include <list>
#include "cpu/smt.hh"
#include "base/types.hh"
#include "cpu/smt.hh"
#include "sim/sim_object.hh"
class IIC;
/**

View file

@ -33,16 +33,16 @@
* Declaration of a LRU tag store.
*/
#ifndef __LRU_HH__
#define __LRU_HH__
#ifndef __MEM_CACHE_TAGS_LRU_HH__
#define __MEM_CACHE_TAGS_LRU_HH__
#include <cassert>
#include <cstring>
#include <list>
#include "mem/cache/blk.hh" // base class
#include "mem/packet.hh" // for inlined functions
#include <assert.h>
#include "mem/cache/blk.hh"
#include "mem/cache/tags/base.hh"
#include "mem/packet.hh"
class BaseCache;
@ -261,4 +261,4 @@ public:
virtual void cleanupRefs();
};
#endif
#endif // __MEM_CACHE_TAGS_LRU_HH__

View file

@ -30,7 +30,8 @@
* $Id$
*/
#include "assert.h"
#include <cassert>
#include "mem/gems_common/util.hh"
// Split a string into a head and tail strings on the specified

View file

@ -48,11 +48,10 @@
#include "base/flags.hh"
#include "base/misc.hh"
#include "base/printable.hh"
#include "mem/request.hh"
#include "base/types.hh"
#include "mem/request.hh"
#include "sim/core.hh"
struct Packet;
typedef Packet *PacketPtr;
typedef uint8_t* PacketDataPtr;

View file

@ -33,17 +33,17 @@
* Declaration of a non-full system Page Table.
*/
#ifndef __PAGE_TABLE__
#define __PAGE_TABLE__
#ifndef __MEM_PAGE_TABLE_HH__
#define __MEM_PAGE_TABLE_HH__
#include <string>
#include "sim/faults.hh"
#include "arch/isa_traits.hh"
#include "arch/tlb.hh"
#include "base/hashmap.hh"
#include "mem/request.hh"
#include "base/types.hh"
#include "mem/request.hh"
#include "sim/faults.hh"
#include "sim/serialize.hh"
class Process;
@ -133,4 +133,4 @@ class PageTable
void unserialize(Checkpoint *cp, const std::string &section);
};
#endif
#endif // __MEM_PAGE_TABLE_HH__

View file

@ -42,11 +42,11 @@
#include "arch/isa_traits.hh"
#include "base/misc.hh"
#include "base/random.hh"
#include "base/types.hh"
#include "config/full_system.hh"
#include "mem/packet_access.hh"
#include "mem/physical.hh"
#include "sim/eventq.hh"
#include "base/types.hh"
using namespace std;
using namespace TheISA;

View file

@ -31,13 +31,14 @@
* $Id$
*/
#ifndef DEBUG_H
#define DEBUG_H
#ifndef __MEM_RUBY_DEBUG_HH__
#define __MEM_RUBY_DEBUG_HH__
#include <unistd.h>
#include <iostream>
#include "config/ruby_debug.hh"
#include "mem/ruby/common/Global.hh"
extern std::ostream * debug_cout_ptr;
@ -302,5 +303,5 @@ const bool ASSERT_FLAG = true;
}\
}
#endif //DEBUG_H
#endif // __MEM_RUBY_DEBUG_HH__

View file

@ -32,8 +32,8 @@
*
* */
#ifndef GLOBAL_H
#define GLOBAL_H
#ifndef __MEM_RUBY_GLOBAL_HH__
#define __MEM_RUBY_GLOBAL_HH__
#ifdef SINGLE_LEVEL_CACHE
const bool TWO_LEVEL_CACHE = false;
@ -105,5 +105,5 @@ extern inline int max_tokens()
}
#endif //GLOBAL_H
#endif // __MEM_RUBY_GLOBAL_HH__

View file

@ -67,8 +67,8 @@
* SOFTWARE.
*------------------------------------------------------------*/
#include <math.h>
#include <assert.h>
#include <cassert>
#include <cmath>
#include "mem/ruby/network/orion/parm_technology.hh"
#include "mem/ruby/network/orion/SIM_port.hh"

View file

@ -26,11 +26,12 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdio.h>
#include <cassert>
#include <cmath>
#include <cstdio>
#include "mem/ruby/network/orion/parm_technology.hh"
#include "mem/ruby/network/orion/power_utils.hh"
#include <assert.h>
#include <math.h>
/* ----------- from SIM_power_util.c ------------ */

View file

@ -28,24 +28,20 @@
* Authors: Daniel Sanchez
*/
#include "arch/isa_traits.hh"
#include "mem/rubymem.hh"
#include "sim/eventq.hh"
#include "base/types.hh"
#include "base/output.hh"
// Ruby includes
#include "mem/ruby/system/System.hh"
#include "mem/ruby/system/Sequencer.hh"
#include "mem/ruby/init.hh"
#include "mem/ruby/common/Debug.hh"
#include "sim/sim_exit.hh"
#include <iostream>
#include <fstream>
#include "arch/isa_traits.hh"
#include "base/output.hh"
#include "base/types.hh"
#include "mem/ruby/common/Debug.hh"
#include "mem/ruby/init.hh"
#include "mem/ruby/system/Sequencer.hh"
#include "mem/ruby/system/System.hh"
#include "mem/rubymem.hh"
#include "sim/eventq.hh"
#include "sim/sim_exit.hh"
using namespace std;
using namespace TheISA;

View file

@ -30,9 +30,7 @@
#ifndef SLICC_GLOBAL_H
#define SLICC_GLOBAL_H
#include <assert.h> /* slicc needs to include this in order to use classes in
* ../common directory.
*/
#include <cassert>
#include "mem/gems_common/std-includes.hh"
#include "mem/gems_common/Map.hh"

View file

@ -36,8 +36,8 @@
#include "base/misc.hh"
#include "base/socket.hh"
#include "sim/core.hh"
#include "base/types.hh"
#include "sim/core.hh"
#include "sim/startup.hh"
extern const char *compileDate;

View file

@ -31,8 +31,8 @@
%module event
%{
#include "python/swig/pyevent.hh"
#include "base/types.hh"
#include "python/swig/pyevent.hh"
#include "sim/eventq.hh"
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
@ -75,9 +75,10 @@
%include "stdint.i"
%include "std_string.i"
%include "base/types.hh"
%include "sim/eventq.hh"
%include "python/swig/pyevent.hh"
%include "sim/eventq.hh"
struct CountedDrainEvent : public Event
{

View file

@ -30,8 +30,8 @@
#include <Python.h>
#include "cpu/base.hh"
#include "base/types.hh"
#include "cpu/base.hh"
#include "sim/serialize.hh"
#include "sim/sim_object.hh"
#include "sim/system.hh"

View file

@ -37,6 +37,7 @@
// import these files for SWIG to wrap
%include "stdint.i"
%include "std_string.i"
%include "base/types.hh"
class BaseCPU;

View file

@ -31,12 +31,12 @@
#ifndef __SIM_ARGUMENTS_HH__
#define __SIM_ARGUMENTS_HH__
#include <assert.h>
#include <cassert>
#include "arch/vtophys.hh"
#include "base/refcnt.hh"
#include "mem/vport.hh"
#include "base/types.hh"
#include "mem/vport.hh"
class ThreadContext;

View file

@ -47,8 +47,8 @@
#include "base/flags.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "sim/serialize.hh"
#include "base/types.hh"
#include "sim/serialize.hh"
class EventQueue; // forward declaration

View file

@ -39,9 +39,9 @@
#include "base/cprintf.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "sim/async.hh"
#include "sim/core.hh"
#include "base/types.hh"
#include "sim/init.hh"
using namespace std;

View file

@ -34,9 +34,9 @@
#include "base/bigint.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/inst_seq.hh" // for InstSeqNum
#include "cpu/static_inst.hh"
#include "base/types.hh"
#include "sim/sim_object.hh"
class ThreadContext;

View file

@ -29,14 +29,14 @@
* Nathan Binkert
*/
#include <assert.h>
#include <cassert>
#include "base/callback.hh"
#include "base/inifile.hh"
#include "base/match.hh"
#include "base/misc.hh"
#include "base/trace.hh"
#include "base/stats/events.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"

View file

@ -31,13 +31,13 @@
#include "base/misc.hh"
#include "base/pollevent.hh"
#include "sim/stat_control.hh"
#include "base/types.hh"
#include "sim/async.hh"
#include "sim/eventq.hh"
#include "base/types.hh"
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
#include "sim/simulate.hh"
#include "sim/stat_control.hh"
/** Simulate for num_cycles additional cycles. If num_cycles is -1
* (the default), do not limit simulation; some other event must

View file

@ -50,11 +50,11 @@
#include <fcntl.h>
#include <sys/uio.h>
#include "base/types.hh"
#include "base/chunk_generator.hh"
#include "base/intmath.hh" // for RoundUp
#include "base/misc.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/translating_port.hh"

View file

@ -30,8 +30,9 @@
#include <iostream>
#include <cassert>
#include "base/types.hh"
#include "base/range_map.hh"
#include "base/types.hh"
using namespace std;

View file

@ -31,8 +31,8 @@
#include <cassert>
#include <iostream>
#include "base/types.hh"
#include "base/range_map.hh"
#include "base/types.hh"
using namespace std;

View file

@ -34,7 +34,7 @@
#include <sys/user.h>
#include <sys/types.h>
#include <sys/ptrace.h>
#include <assert.h>
#include <cassert>
#include <string>
#include "tracechild.hh"

View file

@ -34,7 +34,7 @@
#include <linux/user.h>
#include <sys/types.h>
#include <sys/ptrace.h>
#include <assert.h>
#include <cassert>
#include <string>
#include "tracechild.hh"

View file

@ -32,7 +32,7 @@
#define TRACECHILD_SPARC_HH
#include <asm-sparc64/reg.h>
#include <assert.h>
#include <cassert>
#include <ostream>
#include <stdint.h>
#include <string>