Automated merge with ssh://m5sim.org//repo/m5

src/arch/arm/ArmTLB.py

@@ -32,23 +32,6 @@ from m5.SimObject import SimObject
 from m5.params import *
 
 class ArmTLB(SimObject):
-    abstract = True
     type = 'ArmTLB'
     cxx_class = 'ArmISA::TLB'
-    size = Param.Int("TLB size")
-
-class ArmDTB(ArmTLB):
-    type = 'ArmDTB'
-    cxx_class = 'ArmISA::DTB'
-    size = 64
-
-class ArmITB(ArmTLB):
-    type = 'ArmITB'
-    cxx_class = 'ArmISA::ITB'
-    size = 64
-
-class ArmUTB(ArmTLB):
-    type = 'ArmUTB'
-    cxx_class = 'ArmISA::UTB'
-    size = 64
-
+    size = Param.Int(64, "TLB size")

src/arch/arm/microcode_rom.hh

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2008 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_ARM_MICROCODE_ROM_HH__
+#define __ARCH_ARM_MICROCODE_ROM_HH__
+
+#include "sim/microcode_rom.hh"
+
+namespace ArmISA
+{
+    using ::MicrocodeRom;
+}
+
+#endif // __ARCH_ARM_MICROCODE_ROM_HH__

src/arch/arm/tlb.cc

@@ -36,20 +36,17 @@
 #include <string>
 #include <vector>
 
+#include "arch/arm/faults.hh"
 #include "arch/arm/pagetable.hh"
 #include "arch/arm/tlb.hh"
-#include "arch/arm/faults.hh"
 #include "arch/arm/utility.hh"
 #include "base/inifile.hh"
 #include "base/str.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
-#include "sim/process.hh"
 #include "mem/page_table.hh"
-#include "params/ArmDTB.hh"
-#include "params/ArmITB.hh"
 #include "params/ArmTLB.hh"
-#include "params/ArmUTB.hh"
+#include "sim/process.hh"
 
 
 using namespace std;
@@ -279,7 +276,7 @@ TLB::regStats()
 }
 
 Fault
-ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
+TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 {
 #if !FULL_SYSTEM
     Process * p = tc->getProcessPtr();
@@ -290,68 +287,18 @@ ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
 
     return NoFault;
 #else
-  fatal("ITB translate not yet implemented\n");
+  fatal("translate atomic not yet implemented\n");
 #endif
 }
 
 void
-ITB::translateTiming(RequestPtr req, ThreadContext *tc,
-        Translation *translation)
+TLB::translateTiming(RequestPtr req, ThreadContext *tc,
+        Translation *translation, Mode mode)
 {
     assert(translation);
-    translation->finish(translateAtomic(req, tc), req, tc, false);
+    translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 }
 
-
-Fault
-DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
-{
-#if !FULL_SYSTEM
-    Process * p = tc->getProcessPtr();
-
-    Fault fault = p->pTable->translate(req);
-    if(fault != NoFault)
-        return fault;
-
-    return NoFault;
-#else
-  fatal("DTB translate not yet implemented\n");
-#endif
-}
-
-void
-DTB::translateTiming(RequestPtr req, ThreadContext *tc,
-        Translation *translation, bool write)
-{
-    assert(translation);
-    translation->finish(translateAtomic(req, tc, write), req, tc, write);
-}
-
-///////////////////////////////////////////////////////////////////////
-//
-//  Arm ITB
-//
-ITB::ITB(const Params *p)
-    : TLB(p)
-{}
-
-
-///////////////////////////////////////////////////////////////////////
-//
-//  Arm DTB
-//
-DTB::DTB(const Params *p)
-    : TLB(p)
-{}
-
-///////////////////////////////////////////////////////////////////////
-//
-//  Arm UTB
-//
-UTB::UTB(const Params *p)
-    : ITB(p), DTB(p)
-{}
-
 ArmISA::PTE &
 TLB::index(bool advance)
 {
@@ -363,20 +310,8 @@ TLB::index(bool advance)
     return *pte;
 }
 
-ArmISA::ITB *
-ArmITBParams::create()
+ArmISA::TLB *
+ArmTLBParams::create()
 {
-    return new ArmISA::ITB(this);
-}
-
-ArmISA::DTB *
-ArmDTBParams::create()
-{
-    return new ArmISA::DTB(this);
-}
-
-ArmISA::UTB *
-ArmUTBParams::create()
-{
-    return new ArmISA::UTB(this);
+    return new ArmISA::TLB(this);
 }

src/arch/arm/tlb.hh

@@ -43,8 +43,7 @@
 #include "arch/arm/pagetable.hh"
 #include "base/statistics.hh"
 #include "mem/request.hh"
-#include "params/ArmDTB.hh"
-#include "params/ArmITB.hh"
+#include "params/ArmTLB.hh"
 #include "sim/faults.hh"
 #include "sim/tlb.hh"
 
@@ -135,6 +134,10 @@ class TLB : public BaseTLB
 
     static Fault checkCacheability(RequestPtr &req);
 
+    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
+    void translateTiming(RequestPtr req, ThreadContext *tc,
+            Translation *translation, Mode mode);
+
     // Checkpointing
     void serialize(std::ostream &os);
     void unserialize(Checkpoint *cp, const std::string &section);
@@ -142,36 +145,6 @@ class TLB : public BaseTLB
     void regStats();
 };
 
-class ITB : public TLB
-{
-  public:
-    typedef ArmTLBParams Params;
-    ITB(const Params *p);
-
-    Fault translateAtomic(RequestPtr req, ThreadContext *tc);
-    void translateTiming(RequestPtr req, ThreadContext *tc,
-            Translation *translation);
-};
-
-class DTB : public TLB
-{
-  public:
-    typedef ArmTLBParams Params;
-    DTB(const Params *p);
-
-    Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write);
-    void translateTiming(RequestPtr req, ThreadContext *tc,
-            Translation *translation, bool write);
-};
-
-class UTB : public ITB, public DTB
-{
-  public:
-    typedef ArmTLBParams Params;
-    UTB(const Params *p);
-
-};
-
-}
+/* namespace ArmISA */ }
 
 #endif // __ARCH_ARM_TLB_HH__

src/cpu/BaseCPU.py

@@ -54,7 +54,7 @@ elif build_env['TARGET_ISA'] == 'mips':
     if build_env['FULL_SYSTEM']:
         from MipsInterrupts import MipsInterrupts
 elif build_env['TARGET_ISA'] == 'arm':
-    from ArmTLB import ArmDTB
+    from ArmTLB import ArmTLB
     if build_env['FULL_SYSTEM']:
         from ArmInterrupts import ArmInterrupts
 
@@ -109,8 +109,8 @@ class BaseCPU(MemObject):
                     MipsInterrupts(), "Interrupt Controller")
     elif build_env['TARGET_ISA'] == 'arm':
         UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
-        dtb = Param.ArmTLB(ArmDTB(), "Data TLB")
-        itb = Param.ArmTLB(ArmITB(), "Instruction TLB")
+        dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
+        itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
         if build_env['FULL_SYSTEM']:
             interrupts = Param.ArmInterrupts(
                     ArmInterrupts(), "Interrupt Controller")

src/sim/pseudo_inst.cc

@@ -35,7 +35,8 @@
 #include <fstream>
 #include <string>
 
-#include "arch/kernel_stats.hh"
+#include "config/full_system.hh"
+
 #include "arch/vtophys.hh"
 #include "base/debug.hh"
 #include "cpu/base.hh"
@@ -49,7 +50,9 @@
 #include "sim/stat_control.hh"
 #include "sim/stats.hh"
 #include "sim/system.hh"
+
 #if FULL_SYSTEM
+#include "arch/kernel_stats.hh"
 #include "sim/vptr.hh"
 #endif