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X86: Fix a bug in the iret microcode.

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Gabe Black 2009-01-25 20:31:17 -08:00
parent 389fbfdab1
commit 0449fb2b7a
1 changed files with 2 additions and 1 deletions
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3
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
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@ -75,6 +75,8 @@ def macroop IRET_PROT {
ld t2, ss, [1, t0, rsp], "1 * env.stackSize", dataSize=ssz
ld t3, ss, [1, t0, rsp], "2 * env.stackSize", dataSize=ssz
# Read the handy m5 register for use later
rdm5reg t4
###
@ -89,7 +91,6 @@ def macroop IRET_PROT {
br label("protToVirtFallThrough"), flags=(nCECF,)
#CPL=0
rdm5reg t4
andi t0, t4, 0x30, flags=(EZF,)
br label("protToVirtFallThrough"), flags=(nCEZF,)