X86: Tame the wilds of def operands.
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Gabe Black
parent
df378285f8
commit
7b6587fc9c
1 changed files with 76 additions and 57 deletions
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@ -94,75 +94,94 @@ def operand_types {{
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'df' : ('float', 64),
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}};
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let {{
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def foldInt(idx, foldBit, id):
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return ('IntReg', 'uqw', 'INTREG_FOLDED(%s, %s)' % (idx, foldBit),
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'IsInteger', id)
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def intReg(idx, id):
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return ('IntReg', 'uqw', idx, 'IsInteger', id)
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def impIntReg(idx, id):
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return ('IntReg', 'uqw', 'INTREG_IMPLICIT(%s)' % idx, 'IsInteger', id)
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def floatReg(idx, id):
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return ('FloatReg', 'df', idx, 'IsFloating', id)
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def controlReg(idx, id, ctype = 'uqw'):
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return ('ControlReg', ctype, idx,
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(None, None, ['IsSerializeAfter',
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'IsSerializing',
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'IsNonSpeculative']),
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id)
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}};
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def operands {{
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'SrcReg1': ('IntReg', 'uqw', 'INTREG_FOLDED(src1, foldOBit)', 'IsInteger', 1),
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'SSrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 1),
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'SrcReg2': ('IntReg', 'uqw', 'INTREG_FOLDED(src2, foldOBit)', 'IsInteger', 2),
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'SSrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 1),
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'Index': ('IntReg', 'uqw', 'INTREG_FOLDED(index, foldABit)', 'IsInteger', 3),
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'Base': ('IntReg', 'uqw', 'INTREG_FOLDED(base, foldABit)', 'IsInteger', 4),
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'DestReg': ('IntReg', 'uqw', 'INTREG_FOLDED(dest, foldOBit)', 'IsInteger', 5),
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'SDestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 5),
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'Data': ('IntReg', 'uqw', 'INTREG_FOLDED(data, foldOBit)', 'IsInteger', 6),
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'ProdLow': ('IntReg', 'uqw', 'INTREG_IMPLICIT(0)', 'IsInteger', 7),
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'ProdHi': ('IntReg', 'uqw', 'INTREG_IMPLICIT(1)', 'IsInteger', 8),
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'Quotient': ('IntReg', 'uqw', 'INTREG_IMPLICIT(2)', 'IsInteger', 9),
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'Remainder': ('IntReg', 'uqw', 'INTREG_IMPLICIT(3)', 'IsInteger', 10),
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'Divisor': ('IntReg', 'uqw', 'INTREG_IMPLICIT(4)', 'IsInteger', 11),
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'Rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 12),
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'Rbx': ('IntReg', 'uqw', '(INTREG_RBX)', 'IsInteger', 13),
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'Rcx': ('IntReg', 'uqw', '(INTREG_RCX)', 'IsInteger', 14),
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'Rdx': ('IntReg', 'uqw', '(INTREG_RDX)', 'IsInteger', 15),
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'Rsp': ('IntReg', 'uqw', '(INTREG_RSP)', 'IsInteger', 16),
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'Rbp': ('IntReg', 'uqw', '(INTREG_RBP)', 'IsInteger', 17),
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'Rsi': ('IntReg', 'uqw', '(INTREG_RSI)', 'IsInteger', 18),
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'Rdi': ('IntReg', 'uqw', '(INTREG_RDI)', 'IsInteger', 19),
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'FpSrcReg1': ('FloatReg', 'df', 'src1', 'IsFloating', 20),
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'FpSrcReg2': ('FloatReg', 'df', 'src2', 'IsFloating', 21),
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'FpDestReg': ('FloatReg', 'df', 'dest', 'IsFloating', 22),
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'FpData': ('FloatReg', 'df', 'data', 'IsFloating', 23),
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'SrcReg1': foldInt('src1', 'foldOBit', 1),
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'SSrcReg1': intReg('src1', 1),
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'SrcReg2': foldInt('src2', 'foldOBit', 2),
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'SSrcReg2': intReg('src2', 1),
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'Index': foldInt('index', 'foldABit', 3),
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'Base': foldInt('base', 'foldABit', 4),
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'DestReg': foldInt('dest', 'foldOBit', 5),
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'SDestReg': intReg('dest', 5),
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'Data': foldInt('data', 'foldOBit', 6),
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'ProdLow': impIntReg(0, 7),
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'ProdHi': impIntReg(1, 8),
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'Quotient': impIntReg(2, 9),
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'Remainder': impIntReg(3, 10),
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'Divisor': impIntReg(4, 11),
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'Rax': intReg('(INTREG_RAX)', 12),
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'Rbx': intReg('(INTREG_RBX)', 13),
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'Rcx': intReg('(INTREG_RCX)', 14),
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'Rdx': intReg('(INTREG_RDX)', 15),
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'Rsp': intReg('(INTREG_RSP)', 16),
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'Rbp': intReg('(INTREG_RBP)', 17),
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'Rsi': intReg('(INTREG_RSI)', 18),
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'Rdi': intReg('(INTREG_RDI)', 19),
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'FpSrcReg1': floatReg('src1', 20),
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'FpSrcReg2': floatReg('src2', 21),
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'FpDestReg': floatReg('dest', 22),
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'FpData': floatReg('data', 23),
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'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 50),
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'uIP': ('UPC', 'uqw', None, (None, None, 'IsControl'), 51),
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'nuIP': ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52),
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# This holds the condition code portion of the flag register. The
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# nccFlagBits version holds the rest.
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'ccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', None, 60),
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'ccFlagBits': intReg('INTREG_PSEUDO(0)', 60),
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# These register should needs to be more protected so that later
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# instructions don't map their indexes with an old value.
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'nccFlagBits': ('ControlReg', 'uqw', 'MISCREG_RFLAGS', None, 61),
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'TOP': ('ControlReg', 'ub', 'MISCREG_X87_TOP', None, 62),
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'nccFlagBits': controlReg('MISCREG_RFLAGS', 61),
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'TOP': controlReg('MISCREG_X87_TOP', 62, ctype='ub'),
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# The segment base as used by memory instructions.
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'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_EFF_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70),
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'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70),
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# Operands to get and set registers indexed by the operands of the
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# original instruction.
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'ControlDest': ('ControlReg', 'uqw', 'MISCREG_CR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 100),
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'ControlSrc1': ('ControlReg', 'uqw', 'MISCREG_CR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 101),
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'DebugDest': ('ControlReg', 'uqw', 'MISCREG_DR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 102),
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'DebugSrc1': ('ControlReg', 'uqw', 'MISCREG_DR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 103),
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'SegBaseDest': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 104),
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'SegBaseSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 105),
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'SegLimitDest': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 106),
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'SegLimitSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 107),
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'SegSelDest': ('ControlReg', 'uqw', 'MISCREG_SEG_SEL(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 108),
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'SegSelSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_SEL(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 109),
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'SegAttrDest': ('ControlReg', 'uqw', 'MISCREG_SEG_ATTR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 110),
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'SegAttrSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_ATTR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 111),
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'ControlDest': controlReg('MISCREG_CR(dest)', 100),
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'ControlSrc1': controlReg('MISCREG_CR(src1)', 101),
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'DebugDest': controlReg('MISCREG_DR(dest)', 102),
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'DebugSrc1': controlReg('MISCREG_DR(src1)', 103),
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'SegBaseDest': controlReg('MISCREG_SEG_BASE(dest)', 104),
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'SegBaseSrc1': controlReg('MISCREG_SEG_BASE(src1)', 105),
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'SegLimitDest': controlReg('MISCREG_SEG_LIMIT(dest)', 106),
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'SegLimitSrc1': controlReg('MISCREG_SEG_LIMIT(src1)', 107),
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'SegSelDest': controlReg('MISCREG_SEG_SEL(dest)', 108),
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'SegSelSrc1': controlReg('MISCREG_SEG_SEL(src1)', 109),
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'SegAttrDest': controlReg('MISCREG_SEG_ATTR(dest)', 110),
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'SegAttrSrc1': controlReg('MISCREG_SEG_ATTR(src1)', 111),
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# Operands to access specific control registers directly.
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'EferOp': ('ControlReg', 'uqw', 'MISCREG_EFER', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 200),
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'CR4Op': ('ControlReg', 'uqw', 'MISCREG_CR4', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 201),
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'DR7Op': ('ControlReg', 'uqw', 'MISCREG_DR7', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 202),
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'LDTRBase': ('ControlReg', 'uqw', 'MISCREG_TSL_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 203),
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'LDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSL_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 204),
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'LDTRSel': ('ControlReg', 'uqw', 'MISCREG_TSL', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 205),
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'GDTRBase': ('ControlReg', 'uqw', 'MISCREG_TSG_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 206),
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'GDTRLimit': ('ControlReg', 'uqw', 'MISCREG_TSG_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 207),
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'CSBase': ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 208),
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'CSAttr': ('ControlReg', 'udw', 'MISCREG_CS_ATTR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 209),
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'MiscRegDest': ('ControlReg', 'uqw', 'dest', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 210),
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'MiscRegSrc1': ('ControlReg', 'uqw', 'src1', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 211),
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'TscOp': ('ControlReg', 'uqw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 212),
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'M5Reg': ('ControlReg', 'uqw', 'MISCREG_M5_REG', (None, None, None), 213),
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'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 300)
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'EferOp': controlReg('MISCREG_EFER', 200),
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'CR4Op': controlReg('MISCREG_CR4', 201),
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'DR7Op': controlReg('MISCREG_DR7', 202),
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'LDTRBase': controlReg('MISCREG_TSL_BASE', 203),
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'LDTRLimit': controlReg('MISCREG_TSL_LIMIT', 204),
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'LDTRSel': controlReg('MISCREG_TSL', 205),
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'GDTRBase': controlReg('MISCREG_TSG_BASE', 206),
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'GDTRLimit': controlReg('MISCREG_TSG_LIMIT', 207),
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'CSBase': controlReg('MISCREG_CS_EFF_BASE', 208),
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'CSAttr': controlReg('MISCREG_CS_ATTR', 209),
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'MiscRegDest': controlReg('dest', 210),
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'MiscRegSrc1': controlReg('src1', 211),
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'TscOp': controlReg('MISCREG_TSC', 212),
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'M5Reg': controlReg('MISCREG_M5_REG', 213),
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'Mem': ('Mem', 'uqw', None, \
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('IsMemRef', 'IsLoad', 'IsStore'), 300)
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}};
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