ARM: Make 32 bit thumb use the new, external load instructions.
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Gabe Black
parent
3b93015304
commit
fde3c8f41d
4 changed files with 69 additions and 52 deletions
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@ -78,6 +78,7 @@ def bitfield COND_CODE condCode;
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def bitfield S_FIELD sField;
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def bitfield RN rn;
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def bitfield RD rd;
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def bitfield RT rt;
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def bitfield SHIFT_SIZE shiftSize;
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def bitfield SHIFT shift;
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def bitfield RM rm;
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@ -96,6 +97,7 @@ def bitfield PUBWL pubwl;
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def bitfield IMM imm;
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def bitfield IMMED_11_0 immed11_0;
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def bitfield IMMED_7_0 immed7_0;
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def bitfield IMMED_HI_11_8 immedHi11_8;
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def bitfield IMMED_LO_3_0 immedLo3_0;
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@ -419,58 +419,7 @@
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0x1: decode HTOPCODE_6_5 {
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0x0: WarnUnimpl::Load_byte_memory_hints();
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0x1: WarnUnimpl::Load_halfword_memory_hints();
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0x2: decode HTOPCODE_8 {
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0x0: decode HTRN {
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0xf: ArmLoadMemory::ldr1(
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{{ Rd.uw = Mem.uw }},
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{{ EA = roundUp(PC, 4) +
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(UP ? IMMED_11_0 : -IMMED_11_0); }});
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default: decode HTOPCODE_7 {
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0x0: decode LTOPCODE_11_8 {
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0x0: decode LTOPCODE_7_6 {
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0x0: ArmLoadMemory::ldr2(
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{{ Rd = Mem; }},
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{{ EA = Rn +
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(Rm <<
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bits(machInst, 5, 4)); }}
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);
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}
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0x9: ArmLoadMemory::ldr3(
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{{ Rd = Mem;
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Rn = Rn - IMMED_11_0; }},
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{{ EA = Rn; }}
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);
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0xb: ArmLoadMemory::ldr4(
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{{ Rd = Mem;
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Rn = Rn + IMMED_11_0; }},
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{{ EA = Rn; }}
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);
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0xc: ArmLoadMemory::ldr5(
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{{ Rd = Mem; }},
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{{ EA = Rn - IMMED_11_0; }}
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);
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0xd: ArmLoadMemory::ldr6(
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{{ Rd = Mem;
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Rn = Rn - IMMED_11_0; }},
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{{ EA = Rn - IMMED_11_0; }}
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);
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0xf: ArmLoadMemory::ldr7(
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{{ Rd = Mem;
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Rn = Rn + IMMED_11_0; }},
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{{ EA = Rn + IMMED_11_0; }}
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);
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0xe: ArmLoadMemory::ldrt(
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{{ Rd = Mem; }},
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{{ EA = Rn + IMMED_11_0; }}
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); // This should force user level access
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}
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0x1: ArmLoadMemory::ldr8(
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{{ Rd = Mem; }},
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{{ EA = Rn + IMMED_11_0; }}
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);
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}
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}
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}
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0x2: Thumb32LoadWord::thumb32LoadWord();
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0x3: WarnUnimpl::undefined();
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}
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}
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@ -203,6 +203,71 @@ def format AddrMode3(l0Type, l0Code, l1Type, l1Code) {{
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}'''
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}};
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def format Thumb32LoadWord() {{
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decode = '''
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{
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uint32_t op1 = bits(machInst, 24, 23);
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if (bits(op1, 1) == 0) {
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uint32_t op2 = bits(machInst, 11, 6);
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if (HTRN == 0xF) {
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if (UP) {
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return new %(literal_u)s(machInst, RT, INTREG_PC,
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true, IMMED_11_0);
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} else {
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return new %(literal)s(machInst, RT, INTREG_PC,
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false, IMMED_11_0);
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}
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} else if (op1 == 0x1) {
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return new %(imm_pu)s(machInst, RT, RN, true, IMMED_11_0);
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} else if (op2 == 0) {
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return new %(register)s(machInst, RT, RN, UP,
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bits(machInst, 5, 4), LSL, RM);
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} else if ((op2 & 0x3c) == 0x38) {
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return new %(ldrt)s(machInst, RT, RN, true, IMMED_7_0);
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} else if ((op2 & 0x3c) == 0x30 || //P
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(op2 & 0x24) == 0x24) { //W
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uint32_t puw = bits(machInst, 10, 8);
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uint32_t imm = IMMED_7_0;
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switch (puw) {
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case 0:
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case 2:
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// If we're here, either P or W must have been set.
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panic("Neither P or W set, but that "
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"shouldn't be possible.\\n");
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case 1:
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return new %(imm_w)s(machInst, RT, RN, false, imm);
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case 3:
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return new %(imm_uw)s(machInst, RT, RN, true, imm);
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case 4:
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return new %(imm_p)s(machInst, RT, RN, false, imm);
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case 5:
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return new %(imm_pw)s(machInst, RT, RN, false, imm);
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case 6:
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return new %(imm_pu)s(machInst, RT, RN, true, imm);
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case 7:
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return new %(imm_puw)s(machInst, RT, RN, true, imm);
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}
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}
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} else {
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return new Unknown(machInst);
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}
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}
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'''
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classNames = {
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"literal_u" : loadImmClassName(False, True, False),
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"literal" : loadImmClassName(False, False, False),
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"register" : loadRegClassName(False, True, False),
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"ldrt" : loadImmClassName(False, True, False, user=True),
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"imm_w" : loadImmClassName(True, False, True),
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"imm_uw" : loadImmClassName(True, True, True),
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"imm_p" : loadImmClassName(False, False, False),
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"imm_pw" : loadImmClassName(False, False, True),
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"imm_pu" : loadImmClassName(False, True, False),
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"imm_puw" : loadImmClassName(False, True, True)
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}
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decode_block = decode % classNames
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}};
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def format ArmLoadMemory(memacc_code, ea_code = {{ EA = Rn + disp; }},
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mem_flags = [], inst_flags = []) {{
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ea_code = ArmGenericCodeSubs(ea_code)
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@ -86,6 +86,7 @@ namespace ArmISA
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Bitfield<20> sField;
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Bitfield<19, 16> rn;
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Bitfield<15, 12> rd;
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Bitfield<15, 12> rt;
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Bitfield<11, 7> shiftSize;
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Bitfield<6, 5> shift;
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Bitfield<3, 0> rm;
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