ARM: Define the store instructions from outside the decoder.
--HG-- rename : src/arch/arm/isa/insts/ldr.isa => src/arch/arm/isa/insts/str.isa
This commit is contained in:
Gabe Black
parent
81fdced83f
commit
3b93015304
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@ -255,9 +255,9 @@ format DataOp {
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}});
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}
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}
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0x2: AddrMode2::addrMode2(True, Disp, disp);
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0x2: AddrMode2::addrMode2(True);
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0x3: decode OPCODE_4 {
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0: AddrMode2::addrMode2(False, Shift, Rm_Imm);
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0: AddrMode2::addrMode2(False);
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1: decode MEDIA_OPCODE {
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0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions();
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0x8: decode MISC_OPCODE {
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@ -83,137 +83,10 @@ def template LoadStoreConstructor {{
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}
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}};
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def template StoreExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (%(predicate_test)s)
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{
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
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memAccessFlags, NULL);
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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def template StoreInitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (%(predicate_test)s)
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{
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
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memAccessFlags, NULL);
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}
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// Need to write back any potential address register update
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if (fault == NoFault) {
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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def template StoreCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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if (%(predicate_test)s)
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{
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if (fault == NoFault) {
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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def template StoreCondCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(op_dest_decl)s;
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if (%(predicate_test)s)
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{
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if (fault == NoFault) {
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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let {{
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def buildPUBWLCase(p, u, b, w, l):
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return (p << 4) + (u << 3) + (b << 2) + (w << 1) + (l << 0)
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def buildMode2Inst(p, u, b, w, l, suffix, offset):
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mnem = ("str", "ldr")[l]
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op = ("-", "+")[u]
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offset = op + ArmGenericCodeSubs(offset);
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mem = ("Mem", "Mem.ub")[b]
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code = ("%s = Rd;", "Rd = %s;")[l] % mem
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ea_code = "EA = Rn %s;" % ("", offset)[p]
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if p == 0 or w == 1:
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code += "Rn = Rn %s;" % offset
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if p == 0 and w == 0:
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# Here's where we'll tack on a flag to make this a usermode access.
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mnem += "t"
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type = ("Store", "Load")[l]
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newSuffix = "_%s_P%dU%dB%dW%d" % (suffix, p, u, b, w)
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if b == 1:
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mnem += "b"
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return LoadStoreBase(mnem, mnem.capitalize() + newSuffix,
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ea_code, code, mem_flags = [], inst_flags = [],
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base_class = 'Memory' + suffix,
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exec_template_base = type.capitalize())
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def buildMode3Inst(p, u, i, w, type, code, mnem):
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op = ("-", "+")[u]
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offset = ("%s Rm", "%s hilo")[i] % op
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@ -228,7 +101,7 @@ let {{
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exec_template_base = type.capitalize())
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}};
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def format AddrMode2(imm, suffix, offset) {{
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def format AddrMode2(imm) {{
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if eval(imm):
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imm = True
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else:
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@ -243,20 +116,6 @@ def format AddrMode2(imm, suffix, offset) {{
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for u in (0, 1):
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for b in (0, 1):
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for w in (0, 1):
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(new_header_output,
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new_decoder_output,
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new_decode_block,
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new_exec_output) = buildMode2Inst(p, u, b, w, 0,
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suffix, offset)
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header_output += new_header_output
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decoder_output += new_decoder_output
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exec_output += new_exec_output
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decode_block += '''
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case %#x:
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{%s}
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break;
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''' % (buildPUBWLCase(p,u,b,w,0), new_decode_block)
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post = (p == 0)
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user = (p == 0 and w == 0)
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writeback = (p == 0 or w == 1)
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@ -272,21 +131,31 @@ def format AddrMode2(imm, suffix, offset) {{
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if imm:
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newDecode = "return new %s(machInst, RD, RN," + \
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"%s, machInst.immed11_0);"
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className = loadImmClassName(post, add, writeback,
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loadClass = loadImmClassName(post, add, writeback,
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size, False, user)
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newDecode = newDecode % (className, addStr)
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storeClass = storeImmClassName(post, add, writeback,
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size, False, user)
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loadDecode = newDecode % (loadClass, addStr)
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storeDecode = newDecode % (storeClass, addStr)
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else:
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newDecode = "return new %s(machInst, RD, RN, %s," + \
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"machInst.shiftSize," + \
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"machInst.shift, RM);"
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className = loadRegClassName(post, add, writeback,
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loadClass = loadRegClassName(post, add, writeback,
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size, False, user)
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newDecode = newDecode % (className, addStr)
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decode_block += '''
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storeClass = storeRegClassName(post, add, writeback,
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size, False, user)
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loadDecode = newDecode % (loadClass, addStr)
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storeDecode = newDecode % (storeClass, addStr)
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decode = '''
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case %#x:
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{%s}
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break;
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''' % (buildPUBWLCase(p,u,b,w,1), newDecode)
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'''
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decode_block += decode % \
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(buildPUBWLCase(p,u,b,w,1), loadDecode)
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decode_block += decode % \
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(buildPUBWLCase(p,u,b,w,0), storeDecode)
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decode_block += '''
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default:
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return new Unknown(machInst);
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@ -45,3 +45,6 @@
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//Loads of a single item
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##include "ldr.isa"
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//Stores of a single item
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##include "str.isa"
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139
src/arch/arm/isa/insts/str.isa
Normal file
139
src/arch/arm/isa/insts/str.isa
Normal file
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@ -0,0 +1,139 @@
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// -*- mode:c++ -*-
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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let {{
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header_output = ""
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decoder_output = ""
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exec_output = ""
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def storeImmClassName(post, add, writeback, \
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size=4, sign=False, user=False):
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return memClassName("STORE_IMM", post, add, writeback,
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size, sign, user)
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def storeRegClassName(post, add, writeback, \
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size=4, sign=False, user=False):
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return memClassName("STORE_REG", post, add, writeback,
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size, sign, user)
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def emitStore(name, Name, imm, eaCode, accCode, memFlags, instFlags, base):
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global header_output, decoder_output, exec_output
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(newHeader,
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newDecoder,
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newExec) = newLoadStoreBase(name, Name, imm,
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eaCode, accCode,
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memFlags, instFlags,
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base, execTemplateBase = 'Store')
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header_output += newHeader
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decoder_output += newDecoder
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exec_output += newExec
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def buildImmStore(mnem, post, add, writeback, \
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size=4, sign=False, user=False):
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name = mnem
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Name = storeImmClassName(post, add, writeback, \
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size, sign, user)
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if add:
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op = " +"
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else:
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op = " -"
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offset = op + " imm"
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eaCode = "EA = Base"
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if not post:
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eaCode += offset
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eaCode += ";"
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accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
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if writeback:
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accCode += "Base = Base %s;\n" % offset
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base = buildMemBase("MemoryNewImm", post, writeback)
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emitStore(name, Name, True, eaCode, accCode, [], [], base)
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def buildRegStore(mnem, post, add, writeback, \
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size=4, sign=False, user=False):
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name = mnem
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Name = storeRegClassName(post, add, writeback,
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size, sign, user)
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if add:
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op = " +"
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else:
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op = " -"
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offset = op + " shift_rm_imm(Index, shiftAmt," + \
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" shiftType, CondCodes<29:>)"
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eaCode = "EA = Base"
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if not post:
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eaCode += offset
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eaCode += ";"
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accCode = "Mem%s = Dest;\n" % buildMemSuffix(sign, size)
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if writeback:
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accCode += "Base = Base %s;\n" % offset
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base = buildMemBase("MemoryNewReg", post, writeback)
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emitStore(name, Name, False, eaCode, accCode, [], [], base)
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def buildStores(mnem, size=4, sign=False, user=False):
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buildImmStore(mnem, True, True, True, size, sign, user)
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buildRegStore(mnem, True, True, True, size, sign, user)
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buildImmStore(mnem, True, False, True, size, sign, user)
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buildRegStore(mnem, True, False, True, size, sign, user)
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buildImmStore(mnem, False, True, True, size, sign, user)
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buildRegStore(mnem, False, True, True, size, sign, user)
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buildImmStore(mnem, False, False, True, size, sign, user)
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buildRegStore(mnem, False, False, True, size, sign, user)
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buildImmStore(mnem, False, True, False, size, sign, user)
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buildRegStore(mnem, False, True, False, size, sign, user)
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buildImmStore(mnem, False, False, False, size, sign, user)
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buildRegStore(mnem, False, False, False, size, sign, user)
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buildStores("str")
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buildStores("strt", user=True)
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buildStores("strb", size=1)
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buildStores("strbt", size=1, user=True)
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buildStores("strh", size=2)
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buildStores("strht", size=2, user=True)
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}};
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@ -1,5 +1,17 @@
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// -*- mode:c++ -*-
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
|
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
|
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Copyright (c) 2007-2008 The Florida State University
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// All rights reserved.
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//
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@ -56,6 +68,71 @@ def template LoadExecute {{
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}
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}};
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def template StoreExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (%(predicate_test)s)
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{
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
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memAccessFlags, NULL);
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if (traceData) { traceData->setData(Mem); }
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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def template StoreInitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (%(predicate_test)s)
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{
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
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memAccessFlags, NULL);
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if (traceData) { traceData->setData(Mem); }
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}
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// Need to write back any potential address register update
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if (fault == NoFault) {
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%(op_wb)s;
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}
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}
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return fault;
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}
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}};
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def template LoadInitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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@ -106,6 +183,27 @@ def template LoadCompleteAcc {{
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}
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}};
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def template StoreCompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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if (%(predicate_test)s)
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{
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if (fault == NoFault) {
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%(op_wb)s;
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}
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}
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return fault;
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}
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||||
}};
|
||||
|
||||
def template LoadStoreImmDeclare {{
|
||||
/**
|
||||
* Static instruction class for "%(mnemonic)s".
|
||||
|
|
|
|||
Loading…
Reference in a new issue