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ARM: Define the load instructions from outside the decoder.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:01 -05:00
parent 321d3a6e8c
commit 81fdced83f
10 changed files with 665 additions and 97 deletions
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4
src/arch/arm/isa/decoder/arm.isa
View file

@ -255,9 +255,9 @@ format DataOp {
}});
}
}
0x2: AddrMode2::addrMode2(Disp, disp);
0x2: AddrMode2::addrMode2(True, Disp, disp);
0x3: decode OPCODE_4 {
0: AddrMode2::addrMode2(Shift, Rm_Imm);
0: AddrMode2::addrMode2(False, Shift, Rm_Imm);
1: decode MEDIA_OPCODE {
0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions();
0x8: decode MISC_OPCODE {

157
src/arch/arm/isa/formats/mem.isa
View file

@ -1,5 +1,17 @@
// -*- mode:c++ -*-
// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
@ -72,86 +84,6 @@ def template LoadStoreConstructor {{
}};
def template LoadExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
if (%(predicate_test)s)
{
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
%(memacc_code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
}
return fault;
}
}};
def template LoadInitiateAcc {{
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
%(op_src_decl)s;
%(op_rd)s;
%(ea_code)s;
if (%(predicate_test)s)
{
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
}
}
return fault;
}
}};
def template LoadCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
if (%(predicate_test)s)
{
// ARM instructions will not have a pkt if the predicate is false
Mem = pkt->get<typeof(Mem)>();
if (fault == NoFault) {
%(memacc_code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
}
return fault;
}
}};
def template StoreExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
@ -296,7 +228,12 @@ let {{
exec_template_base = type.capitalize())
}};
def format AddrMode2(suffix, offset) {{
def format AddrMode2(imm, suffix, offset) {{
if eval(imm):
imm = True
else:
imm = False
header_output = decoder_output = exec_output = ""
decode_block = "switch(PUBWL) {\n"
@ -306,20 +243,50 @@ def format AddrMode2(suffix, offset) {{
for u in (0, 1):
for b in (0, 1):
for w in (0, 1):
for l in (0, 1):
(new_header_output,
new_decoder_output,
new_decode_block,
new_exec_output) = buildMode2Inst(p, u, b, w, l,
suffix, offset)
header_output += new_header_output
decoder_output += new_decoder_output
exec_output += new_exec_output
decode_block += '''
case %#x:
{%s}
break;
''' % (buildPUBWLCase(p,u,b,w,l), new_decode_block)
(new_header_output,
new_decoder_output,
new_decode_block,
new_exec_output) = buildMode2Inst(p, u, b, w, 0,
suffix, offset)
header_output += new_header_output
decoder_output += new_decoder_output
exec_output += new_exec_output
decode_block += '''
case %#x:
{%s}
break;
''' % (buildPUBWLCase(p,u,b,w,0), new_decode_block)
post = (p == 0)
user = (p == 0 and w == 0)
writeback = (p == 0 or w == 1)
add = (u == 1)
if b == 0:
size = 4
else:
size = 1
if add:
addStr = "true"
else:
addStr = "false"
if imm:
newDecode = "return new %s(machInst, RD, RN," + \
"%s, machInst.immed11_0);"
className = loadImmClassName(post, add, writeback,
size, False, user)
newDecode = newDecode % (className, addStr)
else:
newDecode = "return new %s(machInst, RD, RN, %s," + \
"machInst.shiftSize," + \
"machInst.shift, RM);"
className = loadRegClassName(post, add, writeback,
size, False, user)
newDecode = newDecode % (className, addStr)
decode_block += '''
case %#x:
{%s}
break;
''' % (buildPUBWLCase(p,u,b,w,1), newDecode)
decode_block += '''
default:
return new Unknown(machInst);

34
src/arch/arm/isa/insts/basic.isa Normal file
View file

@ -0,0 +1,34 @@
// -*- mode:c++ -*-
// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Stephen Hines
// Declarations for execute() methods.
def template BasicExecDeclare {{
Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};

47
src/arch/arm/isa/insts/insts.isa Normal file
View file

@ -0,0 +1,47 @@
// -*- mode:c++ -*-
// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
//Basic forms of various templates
##include "basic.isa"
//Useful bits shared by memory instructions
##include "mem.isa"
//Loads of a single item
##include "ldr.isa"

143
src/arch/arm/isa/insts/ldr.isa Normal file
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@ -0,0 +1,143 @@
// -*- mode:c++ -*-
// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
let {{
header_output = ""
decoder_output = ""
exec_output = ""
def loadImmClassName(post, add, writeback, \
size=4, sign=False, user=False):
return memClassName("LOAD_IMM", post, add, writeback,
size, sign, user)
def loadRegClassName(post, add, writeback, \
size=4, sign=False, user=False):
return memClassName("LOAD_REG", post, add, writeback,
size, sign, user)
def emitLoad(name, Name, imm, eaCode, accCode, memFlags, instFlags, base):
global header_output, decoder_output, exec_output
(newHeader,
newDecoder,
newExec) = newLoadStoreBase(name, Name, imm,
eaCode, accCode,
memFlags, instFlags,
base, execTemplateBase = 'Load')
header_output += newHeader
decoder_output += newDecoder
exec_output += newExec
def buildImmLoad(mnem, post, add, writeback, \
size=4, sign=False, user=False):
name = mnem
Name = loadImmClassName(post, add, writeback, \
size, sign, user)
if add:
op = " +"
else:
op = " -"
offset = op + " imm"
eaCode = "EA = Base"
if not post:
eaCode += offset
eaCode += ";"
accCode = "Dest = Mem%s;\n" % buildMemSuffix(sign, size)
if writeback:
accCode += "Base = Base %s;\n" % offset
base = buildMemBase("MemoryNewImm", post, writeback)
emitLoad(name, Name, True, eaCode, accCode, [], [], base)
def buildRegLoad(mnem, post, add, writeback, \
size=4, sign=False, user=False):
name = mnem
Name = loadRegClassName(post, add, writeback,
size, sign, user)
if add:
op = " +"
else:
op = " -"
offset = op + " shift_rm_imm(Index, shiftAmt," + \
" shiftType, CondCodes<29:>)"
eaCode = "EA = Base"
if not post:
eaCode += offset
eaCode += ";"
accCode = "Dest = Mem%s;\n" % buildMemSuffix(sign, size)
if writeback:
accCode += "Base = Base %s;\n" % offset
base = buildMemBase("MemoryNewReg", post, writeback)
emitLoad(name, Name, False, eaCode, accCode, [], [], base)
def buildLoads(mnem, size=4, sign=False, user=False):
buildImmLoad(mnem, True, True, True, size, sign, user)
buildRegLoad(mnem, True, True, True, size, sign, user)
buildImmLoad(mnem, True, False, True, size, sign, user)
buildRegLoad(mnem, True, False, True, size, sign, user)
buildImmLoad(mnem, False, True, True, size, sign, user)
buildRegLoad(mnem, False, True, True, size, sign, user)
buildImmLoad(mnem, False, False, True, size, sign, user)
buildRegLoad(mnem, False, False, True, size, sign, user)
buildImmLoad(mnem, False, True, False, size, sign, user)
buildRegLoad(mnem, False, True, False, size, sign, user)
buildImmLoad(mnem, False, False, False, size, sign, user)
buildRegLoad(mnem, False, False, False, size, sign, user)
buildLoads("ldr")
buildLoads("ldrt", user=True)
buildLoads("ldrb", size=1)
buildLoads("ldrbt", size=1, user=True)
buildLoads("ldrsb", size=1, sign=True)
buildLoads("ldrsbt", size=1, sign=True, user=True)
buildLoads("ldrh", size=2)
buildLoads("ldrht", size=2, user=True)
buildLoads("hdrsh", size=2, sign=True)
buildLoads("ldrsht", size=2, sign=True, user=True)
}};

143
src/arch/arm/isa/insts/mem.isa Normal file
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@ -0,0 +1,143 @@
// -*- mode:c++ -*-
// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
let {{
def newLoadStoreBase(name, Name, imm, eaCode, accCode, memFlags,
instFlags, base = 'MemoryNew', execTemplateBase = ''):
# Make sure flags are in lists (convert to lists if not).
memFlags = makeList(memFlags)
instFlags = makeList(instFlags)
# This shouldn't be part of the eaCode, but until the exec templates
# are converted over it's the easiest place to put it.
eaCode += '\n unsigned memAccessFlags = '
if memFlags:
eaCode += (string.join(memFlags, '|') + ';')
else:
eaCode += '0;'
predicateTest = 'testPredicate(CondCodes, condCode)'
iop = InstObjParams(name, Name, base,
{'ea_code': eaCode,
'memacc_code': accCode,
'predicate_test': predicateTest},
instFlags)
fullExecTemplate = eval(execTemplateBase + 'Execute')
initiateAccTemplate = eval(execTemplateBase + 'InitiateAcc')
completeAccTemplate = eval(execTemplateBase + 'CompleteAcc')
if imm:
declareTemplate = LoadStoreImmDeclare
constructTemplate = LoadStoreImmConstructor
else:
declareTemplate = LoadStoreRegDeclare
constructTemplate = LoadStoreRegConstructor
# (header_output, decoder_output, decode_block, exec_output)
return (declareTemplate.subst(iop),
constructTemplate.subst(iop),
fullExecTemplate.subst(iop)
+ initiateAccTemplate.subst(iop)
+ completeAccTemplate.subst(iop))
def memClassName(base, post, add, writeback, \
size=4, sign=False, user=False):
Name = base
if post:
Name += '_PY'
else:
Name += '_PN'
if add:
Name += '_AY'
else:
Name += '_AN'
if writeback:
Name += '_WY'
else:
Name += '_WN'
Name += ('_SZ%d' % size)
if sign:
Name += '_SY'
else:
Name += '_SN'
if user:
Name += '_UY'
else:
Name += '_UN'
return Name
def buildMemSuffix(sign, size):
if size == 4:
memSuffix = ''
elif size == 2:
if sign:
memSuffix = '.sh'
else:
memSuffix = '.uh'
elif size == 1:
if sign:
memSuffix = '.sb'
else:
memSuffix = '.ub'
else:
raise Exception, "Unrecognized size for load %d" % size
return memSuffix
def buildMemBase(base, post, writeback):
if post and writeback:
base = "MemoryNewPostIndex<%s>" % base
elif not post and writeback:
base = "MemoryNewPreIndex<%s>" % base
elif not post and not writeback:
base = "MemoryNewOffset<%s>" % base
else:
raise Exception, "Illegal combination of post and writeback"
return base
}};

6
src/arch/arm/isa/main.isa
View file

@ -62,6 +62,12 @@ namespace ArmISA;
//Include the operand_types and operand definitions
##include "operands.isa"
//Templates for the C++ versions of the instructions
##include "templates/templates.isa"
//Include manually defined instructions
##include "insts/insts.isa"
//Include the definitions for the instruction formats
##include "formats/formats.isa"

7
src/arch/arm/isa/operands.isa
View file

@ -69,6 +69,13 @@ let {{
}};
def operands {{
#Abstracted integer reg operands
'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
maybePCRead, maybePCWrite),
'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
maybePCRead, maybePCWrite),
'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
maybePCRead, maybePCWrite),
#General Purpose Integer Reg Operands
'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),

180
src/arch/arm/isa/templates/mem.isa Normal file
View file

@ -0,0 +1,180 @@
// -*- mode:c++ -*-
// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Stephen Hines
def template LoadExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
%(ea_code)s;
if (%(predicate_test)s)
{
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
%(memacc_code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
}
return fault;
}
}};
def template LoadInitiateAcc {{
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
%(op_src_decl)s;
%(op_rd)s;
%(ea_code)s;
if (%(predicate_test)s)
{
if (fault == NoFault) {
fault = xc->read(EA, (uint%(mem_acc_size)d_t &)Mem, memAccessFlags);
}
}
return fault;
}
}};
def template LoadCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
%(op_rd)s;
if (%(predicate_test)s)
{
// ARM instructions will not have a pkt if the predicate is false
Mem = pkt->get<typeof(Mem)>();
if (fault == NoFault) {
%(memacc_code)s;
}
if (fault == NoFault) {
%(op_wb)s;
}
}
return fault;
}
}};
def template LoadStoreImmDeclare {{
/**
* Static instruction class for "%(mnemonic)s".
*/
class %(class_name)s : public %(base_class)s
{
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
%(BasicExecDeclare)s
%(InitiateAccDeclare)s
%(CompleteAccDeclare)s
};
}};
def template LoadStoreRegDeclare {{
/**
* Static instruction class for "%(mnemonic)s".
*/
class %(class_name)s : public %(base_class)s
{
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add,
int32_t _shiftAmt, uint32_t _shiftType,
uint32_t _index);
%(BasicExecDeclare)s
%(InitiateAccDeclare)s
%(CompleteAccDeclare)s
};
}};
def template InitiateAccDeclare {{
Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
def template CompleteAccDeclare {{
Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
def template LoadStoreImmConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
(IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
{
%(constructor)s;
}
}};
def template LoadStoreRegConstructor {{
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add,
int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
(IntRegIndex)_dest, (IntRegIndex)_base, _add,
_shiftAmt, (ArmShiftType)_shiftType,
(IntRegIndex)_index)
{
%(constructor)s;
}
}};

41
src/arch/arm/isa/templates/templates.isa Normal file
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@ -0,0 +1,41 @@
// -*- mode:c++ -*-
// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black
//Templates for memory instructions
##include "mem.isa"