ARM: Implement a new set of base classes for non macro memory instructions.
This commit is contained in:
Gabe Black
parent
8933857af7
commit
321d3a6e8c
2 changed files with 235 additions and 2 deletions
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@ -1,4 +1,17 @@
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/* Copyright (c) 2007-2008 The Florida State University
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -32,6 +45,28 @@
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namespace ArmISA
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{
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void
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MemoryNew::printInst(std::ostream &os, AddrMode addrMode) const
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{
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printMnemonic(os);
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printReg(os, dest);
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os << ", [";
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printReg(os, base);
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if (addrMode != AddrMd_PostIndex) {
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os << ", ";
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printOffset(os);
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os << "]";
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if (addrMode == AddrMd_PreIndex) {
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os << "!";
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}
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} else {
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os << "] ";
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printOffset(os);
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}
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}
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std::string
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Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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@ -50,4 +85,5 @@ Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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ss << "!";
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return ss.str();
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}
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}
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@ -1,4 +1,17 @@
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/* Copyright (c) 2007-2008 The Florida State University
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/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -33,6 +46,190 @@
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namespace ArmISA
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{
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class MemoryNew : public PredOp
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{
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public:
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enum AddrMode {
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AddrMd_Offset,
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AddrMd_PreIndex,
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AddrMd_PostIndex
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};
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protected:
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IntRegIndex dest;
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IntRegIndex base;
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bool add;
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MemoryNew(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _base, bool _add)
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: PredOp(mnem, _machInst, __opClass),
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dest(_dest), base(_base), add(_add)
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{}
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virtual void
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printOffset(std::ostream &os) const
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{}
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void printInst(std::ostream &os, AddrMode addrMode) const;
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};
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// The address is a base register plus an immediate.
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class MemoryNewImm : public MemoryNew
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{
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protected:
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int32_t imm;
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MemoryNewImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm)
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: MemoryNew(mnem, _machInst, __opClass, _dest, _base, _add), imm(_imm)
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{}
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void
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printOffset(std::ostream &os) const
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{
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int32_t pImm = imm;
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if (!add)
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pImm = -pImm;
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ccprintf(os, "#%d", pImm);
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}
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};
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// The address is a shifted register plus an immediate
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class MemoryNewReg : public MemoryNew
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{
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protected:
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int32_t shiftAmt;
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ArmShiftType shiftType;
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IntRegIndex index;
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MemoryNewReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _base, bool _add,
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int32_t _shiftAmt, ArmShiftType _shiftType,
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IntRegIndex _index)
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: MemoryNew(mnem, _machInst, __opClass, _dest, _base, _add),
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shiftAmt(_shiftAmt), shiftType(_shiftType), index(_index)
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{}
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void
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printOffset(std::ostream &os) const
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{
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if (!add)
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os << "-";
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printReg(os, index);
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if (shiftType != LSL || shiftAmt != 0) {
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switch (shiftType) {
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case LSL:
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ccprintf(os, " LSL #%d", shiftAmt);
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break;
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case LSR:
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if (shiftAmt == 0) {
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ccprintf(os, " LSR #%d", 32);
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} else {
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ccprintf(os, " LSR #%d", shiftAmt);
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}
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break;
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case ASR:
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if (shiftAmt == 0) {
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ccprintf(os, " ASR #%d", 32);
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} else {
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ccprintf(os, " ASR #%d", shiftAmt);
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}
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break;
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case ROR:
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if (shiftAmt == 0) {
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ccprintf(os, " RRX");
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} else {
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ccprintf(os, " ROR #%d", shiftAmt);
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}
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break;
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}
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}
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}
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};
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template<class Base>
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class MemoryNewOffset : public Base
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{
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protected:
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MemoryNewOffset(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
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bool _add, int32_t _imm)
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: Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
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{}
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MemoryNewOffset(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
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bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
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IntRegIndex _index)
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: Base(mnem, _machInst, __opClass, _dest, _base, _add,
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_shiftAmt, _shiftType, _index)
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{}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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this->printInst(ss, MemoryNew::AddrMd_Offset);
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return ss.str();
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}
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};
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template<class Base>
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class MemoryNewPreIndex : public Base
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{
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protected:
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MemoryNewPreIndex(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
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bool _add, int32_t _imm)
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: Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
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{}
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MemoryNewPreIndex(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
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bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
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IntRegIndex _index)
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: Base(mnem, _machInst, __opClass, _dest, _base, _add,
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_shiftAmt, _shiftType, _index)
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{}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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this->printInst(ss, MemoryNew::AddrMd_PreIndex);
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return ss.str();
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}
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};
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template<class Base>
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class MemoryNewPostIndex : public Base
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{
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protected:
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MemoryNewPostIndex(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
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bool _add, int32_t _imm)
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: Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
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{}
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MemoryNewPostIndex(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
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bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
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IntRegIndex _index)
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: Base(mnem, _machInst, __opClass, _dest, _base, _add,
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_shiftAmt, _shiftType, _index)
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{}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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this->printInst(ss, MemoryNew::AddrMd_PostIndex);
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return ss.str();
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}
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};
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/**
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* Base class for general Arm memory-format instructions.
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*/
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