Make default PhysicalMemory latency slightly more realistic.
Also update stats to reflect change.
This commit is contained in:
Steve Reinhardt
parent
b179c3f4cd
commit
62c08a75ad
131 changed files with 5698 additions and 5670 deletions
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@ -35,7 +35,7 @@ class PhysicalMemory(MemObject):
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port = VectorPort("the access port")
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range = Param.AddrRange(AddrRange('128MB'), "Device Address")
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file = Param.String('', "memory mapped file")
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latency = Param.Latency('1t', "latency of an access")
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latency = Param.Latency('30ns', "latency of an access")
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latency_var = Param.Latency('0ns', "access variablity")
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zero = Param.Bool(False, "zero initialize memory")
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null = Param.Bool(False, "do not store data, always return zero")
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@ -368,6 +368,7 @@ cmd=gzip input.log 1
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cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
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egid=100
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env=
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errout=cerr
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euid=100
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executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
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gid=100
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@ -393,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
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[system.physmem]
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type=PhysicalMemory
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file=
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latency=1
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latency=30000
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latency_var=0
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null=false
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range=0:134217727
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@ -1,40 +1,40 @@
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---------- Begin Simulation Statistics ----------
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global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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global.BPredUnit.BTBHits 65739146 # Number of BTB hits
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global.BPredUnit.BTBLookups 73253175 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 177 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 4205990 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 70175548 # Number of conditional branches predicted
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global.BPredUnit.lookups 76112488 # Number of BP lookups
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global.BPredUnit.usedRAS 1692573 # Number of times the RAS was used to get a target.
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host_inst_rate 131337 # Simulator instruction rate (inst/s)
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host_mem_usage 179084 # Number of bytes of host memory used
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host_seconds 4306.11 # Real time elapsed on the host
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host_tick_rate 38417331 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 21896719 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 16284345 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 127086189 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 43192001 # Number of stores inserted to the mem dependence unit.
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global.BPredUnit.BTBHits 65718863 # Number of BTB hits
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global.BPredUnit.BTBLookups 73181378 # Number of BTB lookups
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global.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions.
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global.BPredUnit.condIncorrect 4206850 # Number of conditional branches incorrect
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global.BPredUnit.condPredicted 70112297 # Number of conditional branches predicted
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global.BPredUnit.lookups 76039028 # Number of BP lookups
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global.BPredUnit.usedRAS 1692219 # Number of times the RAS was used to get a target.
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host_inst_rate 225803 # Simulator instruction rate (inst/s)
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host_mem_usage 201396 # Number of bytes of host memory used
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host_seconds 2504.62 # Real time elapsed on the host
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host_tick_rate 66707870 # Simulator tick rate (ticks/s)
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memdepunit.memDep.conflictingLoads 19292303 # Number of conflicting loads.
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memdepunit.memDep.conflictingStores 14732751 # Number of conflicting stores.
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memdepunit.memDep.insertedLoads 126977207 # Number of loads inserted to the mem dependence unit.
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memdepunit.memDep.insertedStores 43223597 # Number of stores inserted to the mem dependence unit.
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 565552443 # Number of instructions simulated
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sim_seconds 0.165429 # Number of seconds simulated
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sim_ticks 165429421500 # Number of ticks simulated
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sim_seconds 0.167078 # Number of seconds simulated
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sim_ticks 167078186500 # Number of ticks simulated
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system.cpu.commit.COM:branches 62547159 # Number of branches committed
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system.cpu.commit.COM:bw_lim_events 20148945 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_lim_events 17700250 # number cycles where commit BW limit reached
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system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
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system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle.samples 320950455
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system.cpu.commit.COM:committed_per_cycle.samples 322711309
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system.cpu.commit.COM:committed_per_cycle.min_value 0
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0 102049912 3179.62%
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1 106118520 3306.38%
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2 36548740 1138.77%
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3 11550344 359.88%
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4 9951958 310.08%
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5 22152324 690.21%
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6 10779065 335.85%
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7 1650647 51.43%
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8 20148945 627.79%
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0 108088817 3349.40%
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1 100475751 3113.49%
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2 37367184 1157.91%
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3 9733028 301.60%
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4 10676883 330.85%
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5 22147835 686.30%
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6 13251874 410.64%
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7 3269687 101.32%
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8 17700250 548.49%
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system.cpu.commit.COM:committed_per_cycle.max_value 8
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system.cpu.commit.COM:committed_per_cycle.end_dist
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@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 115049510 # Nu
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system.cpu.commit.COM:membars 0 # Number of memory barriers committed
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system.cpu.commit.COM:refs 154862033 # Number of memory references committed
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system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
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system.cpu.commit.branchMispredicts 4205367 # The number of times a branch was mispredicted
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system.cpu.commit.branchMispredicts 4206223 # The number of times a branch was mispredicted
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system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
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system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
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system.cpu.commit.commitSquashedInsts 61707712 # The number of squashed insts skipped by commit
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system.cpu.commit.commitSquashedInsts 61418223 # The number of squashed insts skipped by commit
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system.cpu.committedInsts 565552443 # Number of Instructions Simulated
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system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
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system.cpu.cpi 0.585019 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.585019 # CPI: Total CPI of All Threads
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system.cpu.cpi 0.590849 # CPI: Cycles Per Instruction
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system.cpu.cpi_total 0.590849 # CPI: Total CPI of All Threads
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system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
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system.cpu.dcache.ReadReq_accesses 115038352 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 6257.587595 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3367.177206 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 114105250 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 5838967500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.008111 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 933102 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 716795 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 728344000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.001880 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 216307 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_accesses 113146791 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 19647.218520 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7806.236909 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 112293702 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 16760826000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.007540 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 853089 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_hits 636812 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_miss_latency 1688309500 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.001911 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 216277 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 7448.640662 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7159.473367 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 37241994 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 16456482928 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.056001 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 2209327 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1872039 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 2414804453 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_avg_miss_latency 32801.298408 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35637.649046 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 37121636 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 76416692881 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.059052 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 2329685 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_hits 1992407 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_miss_latency 12019794995 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.008549 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 337288 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs 1999.750000 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets 2750 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 321.245700 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 4 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 4 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 7999 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 11000 # number of cycles access was blocked
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system.cpu.dcache.WriteReq_mshr_misses 337278 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs 6922.723577 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets 21318.181818 # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 317.179200 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 123 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 11 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 851495 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_targets 234500 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 154489673 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 7094.973483 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 5677.703832 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 151347244 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 22295450428 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.020341 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 3142429 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2588834 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 3143148453 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.003583 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 553595 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_accesses 152598112 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 29275.568696 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 24763.762399 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 149415338 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 93177518881 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.020857 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 3182774 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 2629219 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 13708104495 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.003628 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 553555 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 154489673 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 7094.973483 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 5677.703832 # average overall mshr miss latency
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system.cpu.dcache.overall_accesses 152598112 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 29275.568696 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 24763.762399 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 151347244 # number of overall hits
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system.cpu.dcache.overall_miss_latency 22295450428 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.020341 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 3142429 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2588834 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 3143148453 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.003583 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 553595 # number of overall MSHR misses
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system.cpu.dcache.overall_hits 149415338 # number of overall hits
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system.cpu.dcache.overall_miss_latency 93177518881 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.020857 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 3182774 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 2629219 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 13708104495 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.003628 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 553555 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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@ -120,102 +120,102 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
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system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 468826 # number of replacements
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system.cpu.dcache.sampled_refs 472922 # Sample count of references to valid blocks.
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system.cpu.dcache.replacements 468828 # number of replacements
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system.cpu.dcache.sampled_refs 472924 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4095.170465 # Cycle average of tags in use
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system.cpu.dcache.total_refs 151924159 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 50285000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 334126 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 46422286 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 645 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 4161088 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 690019158 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 145191324 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 123829448 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 9907520 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 1984 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 5507398 # Number of cycles decode is unblocking
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system.cpu.dtb.accesses 163087430 # DTB accesses
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system.cpu.dcache.tagsinuse 4094.202443 # Cycle average of tags in use
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system.cpu.dcache.total_refs 150001656 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 126621000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 334123 # number of writebacks
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system.cpu.decode.DECODE:BlockedCycles 49202535 # Number of cycles decode is blocked
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system.cpu.decode.DECODE:BranchMispred 654 # Number of times decode detected a branch misprediction
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system.cpu.decode.DECODE:BranchResolved 4158991 # Number of times decode resolved a branch
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system.cpu.decode.DECODE:DecodedInsts 689696251 # Number of instructions handled by decode
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system.cpu.decode.DECODE:IdleCycles 144199512 # Number of cycles decode is idle
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system.cpu.decode.DECODE:RunCycles 123896072 # Number of cycles decode is running
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system.cpu.decode.DECODE:SquashCycles 9869869 # Number of cycles decode is squashing
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system.cpu.decode.DECODE:SquashedInsts 2004 # Number of squashed instructions handled by decode
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system.cpu.decode.DECODE:UnblockCycles 5413191 # Number of cycles decode is unblocking
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system.cpu.dtb.accesses 163077395 # DTB accesses
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system.cpu.dtb.acv 0 # DTB access violations
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system.cpu.dtb.hits 163038163 # DTB hits
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system.cpu.dtb.misses 49267 # DTB misses
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system.cpu.dtb.read_accesses 122338189 # DTB read accesses
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system.cpu.dtb.hits 163013885 # DTB hits
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system.cpu.dtb.misses 63510 # DTB misses
|
||||
system.cpu.dtb.read_accesses 122284114 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 122317544 # DTB read hits
|
||||
system.cpu.dtb.read_misses 20645 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 40749241 # DTB write accesses
|
||||
system.cpu.dtb.read_hits 122260501 # DTB read hits
|
||||
system.cpu.dtb.read_misses 23613 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 40793281 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 40720619 # DTB write hits
|
||||
system.cpu.dtb.write_misses 28622 # DTB write misses
|
||||
system.cpu.fetch.Branches 76112488 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 66025670 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 197184214 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1351502 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 699221634 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 4235220 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.230045 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 66025670 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 67431719 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.113353 # Number of inst fetches per cycle
|
||||
system.cpu.dtb.write_hits 40753384 # DTB write hits
|
||||
system.cpu.dtb.write_misses 39897 # DTB write misses
|
||||
system.cpu.fetch.Branches 76039028 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 66014416 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 197129359 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1352914 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 698864070 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 4233116 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.227555 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 66014416 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 67411082 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.091428 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 330857976
|
||||
system.cpu.fetch.rateDist.samples 332581179
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 199699470 6035.81%
|
||||
1 10371896 313.48%
|
||||
2 15863038 479.45%
|
||||
3 14602598 441.36%
|
||||
4 12358229 373.52%
|
||||
5 14818818 447.89%
|
||||
6 6010699 181.67%
|
||||
7 3341156 100.98%
|
||||
8 53792072 1625.84%
|
||||
0 201466276 6057.66%
|
||||
1 10360751 311.53%
|
||||
2 15882086 477.54%
|
||||
3 14599006 438.96%
|
||||
4 12362950 371.73%
|
||||
5 14822133 445.67%
|
||||
6 6008311 180.66%
|
||||
7 3307530 99.45%
|
||||
8 53772136 1616.81%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 66025670 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 9355.263158 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6819.290466 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 66024644 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 9598500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 1026 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 124 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 6151000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 66014416 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 36203.165098 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35497.228381 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 66013247 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 42321500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 1169 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 267 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 32018500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 73198.053215 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 73185.417960 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 66025670 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 9355.263158 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6819.290466 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 66024644 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 9598500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000016 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 1026 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 124 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 6151000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_accesses 66014416 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 36203.165098 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35497.228381 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 66013247 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 42321500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 1169 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 267 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 32018500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 66025670 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 9355.263158 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6819.290466 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 66014416 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 36203.165098 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35497.228381 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 66024644 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 9598500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 1026 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 124 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 6151000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_hits 66013247 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 42321500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 1169 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 267 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 32018500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -229,63 +229,63 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 32 # number of replacements
|
||||
system.cpu.icache.replacements 34 # number of replacements
|
||||
system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 769.239178 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 66024644 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 769.803769 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 66013247 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 868 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 67336673 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 43018581 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.810881 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 164027135 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 41145337 # Number of stores executed
|
||||
system.cpu.idleCycles 1575195 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 67316863 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 42997381 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.793347 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 164017998 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 41189464 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 491694974 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 595952322 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.808476 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 487237026 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 596051181 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.811465 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 397523802 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.801228 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 597113280 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 4671395 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 85472 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 127086189 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 3259094 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 43192001 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 663707703 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 122881798 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 6536173 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 599145915 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 1317 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 395375822 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.783749 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 597227214 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 4671564 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 2251991 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 126977207 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 3270425 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 43223597 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 663380014 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 122828534 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 6459967 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 599258177 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 2444 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 9907520 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 4668 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 34441 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 9869869 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 84553 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 4162 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 7269203 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 14266 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 207 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 9107751 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 14447 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 32461 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 5902 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 12036679 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 3379478 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 32461 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 540781 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 4130614 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.709347 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.709347 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 605682088 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 29567 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 5881 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 11927697 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 3411074 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 29567 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 540318 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 4131246 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.692478 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.692478 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 605718144 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
No_OpClass 0 0.00% # Type of FU issued
|
||||
IntAlu 438760030 72.44% # Type of FU issued
|
||||
IntMult 6517 0.00% # Type of FU issued
|
||||
IntAlu 438834867 72.45% # Type of FU issued
|
||||
IntMult 6546 0.00% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 29 0.00% # Type of FU issued
|
||||
FloatCmp 5 0.00% # Type of FU issued
|
||||
|
|
@ -293,17 +293,17 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|||
FloatMult 4 0.00% # Type of FU issued
|
||||
FloatDiv 0 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 124950238 20.63% # Type of FU issued
|
||||
MemWrite 41965260 6.93% # Type of FU issued
|
||||
MemRead 124855458 20.61% # Type of FU issued
|
||||
MemWrite 42021230 6.94% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 6912738 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.011413 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 7232327 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.011940 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
No_OpClass 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 5342591 77.29% # attempts to use FU when none available
|
||||
IntMult 72 0.00% # attempts to use FU when none available
|
||||
IntAlu 5390835 74.54% # attempts to use FU when none available
|
||||
IntMult 67 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 0 0.00% # attempts to use FU when none available
|
||||
FloatCmp 0 0.00% # attempts to use FU when none available
|
||||
|
|
@ -311,102 +311,102 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 924602 13.38% # attempts to use FU when none available
|
||||
MemWrite 645473 9.34% # attempts to use FU when none available
|
||||
MemRead 1490139 20.60% # attempts to use FU when none available
|
||||
MemWrite 351286 4.86% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 330857976
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 332581179
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 90630363 2739.25%
|
||||
1 66723730 2016.69%
|
||||
2 79382589 2399.30%
|
||||
3 36274593 1096.38%
|
||||
4 32477730 981.62%
|
||||
5 12845074 388.24%
|
||||
6 10946309 330.85%
|
||||
7 1065447 32.20%
|
||||
8 512141 15.48%
|
||||
0 92203834 2772.37%
|
||||
1 67051351 2016.09%
|
||||
2 80133785 2409.45%
|
||||
3 36043476 1083.75%
|
||||
4 30084945 904.59%
|
||||
5 14579095 438.36%
|
||||
6 10850498 326.25%
|
||||
7 1143008 34.37%
|
||||
8 491187 14.77%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 1.830636 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 620689100 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 605682088 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 53858401 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 17774 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 29864580 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 66025708 # ITB accesses
|
||||
system.cpu.iq.ISSUE:rate 1.812679 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 620382610 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 605718144 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 53519343 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 12833 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 29313590 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 66014456 # ITB accesses
|
||||
system.cpu.itb.acv 0 # ITB acv
|
||||
system.cpu.itb.hits 66025670 # ITB hits
|
||||
system.cpu.itb.misses 38 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 256615 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 5221.239990 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2221.239990 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1339848500 # number of ReadExReq miss cycles
|
||||
system.cpu.itb.hits 66014416 # ITB hits
|
||||
system.cpu.itb.misses 40 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 256647 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34260.342026 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31141.538767 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 8792814000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 256615 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 570003500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_misses 256647 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7992382500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 256615 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 217209 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 5324.201615 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2324.201615 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 181418 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 190558500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.164777 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 35791 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 83185500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164777 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 35791 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 80676 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5165.743220 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2166.071694 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 416751500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 256647 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 217179 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34303.958543 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31015.588334 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 181383 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1227944500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.164823 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 35796 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1110234000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.164823 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 35796 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 80643 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34136.391255 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31030.684622 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 2752861000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 80676 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 174750000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 80643 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2502407500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 80676 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 334126 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 334126 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 80643 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 334123 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 334123 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs 5083.333333 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 3.724082 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_refs 3.723010 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 78 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 396500 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 473824 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 5233.842671 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2233.842671 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 181418 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1530407000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.617119 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 292406 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 473826 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34265.680834 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31126.122014 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 181383 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 10020758500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.617195 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 292443 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 653189000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.617119 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 292406 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 9102616500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.617195 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 292443 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 473824 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 5233.842671 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2233.842671 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 473826 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34265.680834 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31126.122014 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 181418 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1530407000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.617119 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 292406 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 181383 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 10020758500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.617195 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 292443 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 653189000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.617119 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 292406 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 9102616500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.617195 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 292443 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -418,31 +418,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 85250 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 100885 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 85262 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 100888 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 16355.319881 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 375704 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 16333.158558 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 375607 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 63237 # number of writebacks
|
||||
system.cpu.numCycles 330858844 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 11109833 # Number of cycles rename is blocking
|
||||
system.cpu.l2cache.writebacks 63236 # number of writebacks
|
||||
system.cpu.numCycles 334156374 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 15214869 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 34908767 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 152607206 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 316634 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 896955924 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 680550426 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 519573186 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 116670528 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 9907520 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 40562533 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 55718297 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 356 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 79715664 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 25 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 189 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 31587364 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 151899466 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 2286618 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 131 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 896816435 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 680424801 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 519473844 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 116401000 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 9869869 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 39195269 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 55618955 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 706 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 77660301 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 26 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 36535 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7004
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 21 2008 20:12:56
|
||||
M5 started Mon Jul 21 20:22:47 2008
|
||||
M5 compiled Aug 2 2008 17:07:15
|
||||
M5 started Sat Aug 2 17:11:39 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
|
||||
M5 commit date Tue Jul 15 14:38:51 2008 -0400
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing tests/run.py long/00.gzip/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -166,6 +166,7 @@ cmd=gzip input.log 1
|
|||
cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
|
||||
gid=100
|
||||
|
|
@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1122189 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 222560 # Number of bytes of host memory used
|
||||
host_seconds 536.32 # Real time elapsed on the host
|
||||
host_tick_rate 1430957420 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1676744 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 200380 # Number of bytes of host memory used
|
||||
host_seconds 358.94 # Real time elapsed on the host
|
||||
host_tick_rate 2167478980 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 601856964 # Number of instructions simulated
|
||||
sim_seconds 0.767457 # Number of seconds simulated
|
||||
sim_ticks 767457055000 # Number of ticks simulated
|
||||
sim_seconds 0.778004 # Number of seconds simulated
|
||||
sim_ticks 778003833000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 16196.211338 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13196.211338 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 21095.452016 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18095.452016 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 3259196000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 4245080000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2655500000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3641384000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 26999.984797 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.984797 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.984797 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.984797 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 39122430 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 8880052000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 18417891000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.008337 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 328891 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 7893379000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 17431218000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.008337 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 328891 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 22898.927230 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 19898.927230 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 42750.401322 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 153435240 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 12139248000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 22662971000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.003443 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 530123 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 10548879000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 21072602000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.003443 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 530123 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 22898.927230 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 19898.927230 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 42750.401322 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 153435240 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 12139248000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 22662971000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 530123 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 10548879000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 21072602000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.003443 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 451299 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4094.918042 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4094.195523 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 357644000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 579204000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 325723 # number of writebacks
|
||||
system.cpu.dtb.accesses 153970296 # DTB accesses
|
||||
system.cpu.dtb.acv 0 # DTB access violations
|
||||
|
|
@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
|
|||
system.cpu.dtb.write_hits 39451321 # DTB write hits
|
||||
system.cpu.dtb.write_misses 2302 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 601861898 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 601861103 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 21465000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 44520000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 795 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 19080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 42135000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 795 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 601861898 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 601861103 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 21465000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 44520000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 795 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 19080000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 42135000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 795 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 601861103 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 21465000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 44520000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 795 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 19080000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 42135000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 795 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 24 # number of replacements
|
||||
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 673.689179 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 673.225224 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -160,31 +160,31 @@ system.cpu.itb.acv 0 # IT
|
|||
system.cpu.itb.hits 601861898 # ITB hits
|
||||
system.cpu.itb.misses 20 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 5845749000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 13216476000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 254163 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2795793000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 10166520000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 254163 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 167236 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 800193000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1809132000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.172210 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 34791 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 382701000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1391640000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.172210 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 34791 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 74728 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22998.461086 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 1718629000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51996.520715 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 3885596000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 74728 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 822008000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2989120000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 74728 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -198,29 +198,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 167236 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 6645942000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 15025608000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.633407 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 288954 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 3178494000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 11558160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.633407 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 288954 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 167236 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 6645942000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 15025608000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.633407 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 288954 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 3178494000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 11558160000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.633407 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 288954 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 84513 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 100134 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 16357.683393 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 16343.542372 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 352458 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 63194 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1534914110 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1556007666 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 601856964 # Number of instructions executed
|
||||
system.cpu.num_refs 154866966 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7006
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7003
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 21 2008 20:12:56
|
||||
M5 started Mon Jul 21 20:13:00 2008
|
||||
M5 compiled Aug 2 2008 17:07:15
|
||||
M5 started Sat Aug 2 17:07:24 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
|
||||
M5 commit date Tue Jul 15 14:38:51 2008 -0400
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing tests/run.py long/00.gzip/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -394,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,122 +1,122 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 181900655 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 205112403 # Number of BTB lookups
|
||||
global.BPredUnit.BTBHits 182414509 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 203429504 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 84376140 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 253553370 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 253553370 # Number of BP lookups
|
||||
global.BPredUnit.condIncorrect 83681535 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 254458067 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 254458067 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 148554 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214964 # Number of bytes of host memory used
|
||||
host_seconds 9461.99 # Real time elapsed on the host
|
||||
host_tick_rate 116526717 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 445262703 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 137431528 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 741823023 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 303434035 # Number of stores inserted to the mem dependence unit.
|
||||
host_inst_rate 99984 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 203500 # Number of bytes of host memory used
|
||||
host_seconds 14058.38 # Real time elapsed on the host
|
||||
host_tick_rate 78434309 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 460341314 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 141106006 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 743909112 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 301399355 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1405618364 # Number of instructions simulated
|
||||
sim_seconds 1.102575 # Number of seconds simulated
|
||||
sim_ticks 1102574586000 # Number of ticks simulated
|
||||
sim_insts 1405618365 # Number of instructions simulated
|
||||
sim_seconds 1.102659 # Number of seconds simulated
|
||||
sim_ticks 1102659164000 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 86248929 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 8144949 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 8096119 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 1965667914
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 1964055138
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 1089833449 5544.34%
|
||||
1 574599936 2923.18%
|
||||
2 120982749 615.48%
|
||||
3 121997991 620.64%
|
||||
4 27903349 141.95%
|
||||
5 7399398 37.64%
|
||||
6 10434529 53.08%
|
||||
7 4371564 22.24%
|
||||
8 8144949 41.44%
|
||||
0 1088074348 5539.94%
|
||||
1 575643775 2930.89%
|
||||
2 120435536 613.20%
|
||||
3 120975808 615.95%
|
||||
4 27955061 142.33%
|
||||
5 8084154 41.16%
|
||||
6 10447088 53.19%
|
||||
7 4343249 22.11%
|
||||
8 8096119 41.22%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
system.cpu.commit.COM:count 1489537507 # Number of instructions committed
|
||||
system.cpu.commit.COM:loads 402517242 # Number of loads committed
|
||||
system.cpu.commit.COM:count 1489537508 # Number of instructions committed
|
||||
system.cpu.commit.COM:loads 402517243 # Number of loads committed
|
||||
system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 569375198 # Number of memory references committed
|
||||
system.cpu.commit.COM:refs 569375199 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 84376140 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 1489537507 # The number of committed instructions
|
||||
system.cpu.commit.branchMispredicts 83681535 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 1489537508 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 1379626157 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 1405618364 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1405618364 # Number of Instructions Simulated
|
||||
system.cpu.cpi 1.568811 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.568811 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 431515523 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 5833.098785 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2978.922588 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 430678453 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4882712000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.001940 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 837070 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 610026 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 676346500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000526 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 227044 # number of ReadReq MSHR misses
|
||||
system.cpu.commit.commitSquashedInsts 1390237691 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 1405618365 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1405618365 # Number of Instructions Simulated
|
||||
system.cpu.cpi 1.568931 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.568931 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 426261934 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14297.934404 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6789.549883 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 425346266 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 13092161000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002148 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 915668 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 667355 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1685933500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000583 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 248313 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 9037.500000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 6037.500000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 38037.500000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35037.500000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_miss_latency 361500 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency 1521500 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 241500 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 1401500 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 10313.448208 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7754.282564 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 164722472 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 22010528000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.012790 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 2134158 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1792190 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2651716500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002049 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 341968 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 37763.233543 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36078.301493 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 164634096 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 83930070500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.013320 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 2222534 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1870625 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 12696279000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.002109 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 351909 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 1192.957701 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 1119.158506 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 598372153 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 9051.220573 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 5848.845016 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 595400925 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 26893240000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.004966 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2971228 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 2402216 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3328063000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000951 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 569012 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 593118564 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 30916.502985 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23961.488416 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 589980362 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 97022231500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.005291 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 3138202 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 2537980 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 14382212500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.001012 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 600222 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 598372153 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 9051.220573 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 5848.845016 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 593118564 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 30916.502985 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23961.488416 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 595400925 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 26893240000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.004966 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2971228 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 2402216 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3328063000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000951 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 569012 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 589980362 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 97022231500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.005291 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 3138202 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 2537980 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 14382212500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.001012 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 600222 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -128,89 +128,89 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 495162 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 499258 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 523278 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 527374 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4095.748023 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 595593676 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 87021000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 338803 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 411671419 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 3446173364 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 768410177 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 782727450 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 239480011 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 2858868 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 253553370 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 356679957 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 1203446624 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 10248361 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 3739591650 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 90314479 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.114982 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 356679957 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 181900655 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.695845 # Number of inst fetches per cycle
|
||||
system.cpu.dcache.tagsinuse 4095.579742 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 590215098 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 166150000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 348745 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 416443424 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 3435538867 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 762668523 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 782001807 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 239759981 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 2941384 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 254458067 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 354588627 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 1199300776 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 10659934 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 3732201090 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 88873600 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.115384 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 354588627 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 182414509 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.692364 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 2205147925
|
||||
system.cpu.fetch.rateDist.samples 2203815119
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 1358381303 6160.05%
|
||||
1 256975915 1165.35%
|
||||
2 81117048 367.85%
|
||||
3 38328968 173.82%
|
||||
4 87811486 398.21%
|
||||
5 41185341 186.77%
|
||||
6 30948688 140.35%
|
||||
7 20663450 93.71%
|
||||
8 289735726 1313.91%
|
||||
0 1359103013 6167.05%
|
||||
1 256500552 1163.89%
|
||||
2 81150170 368.23%
|
||||
3 38425919 174.36%
|
||||
4 85384466 387.44%
|
||||
5 41200028 186.95%
|
||||
6 32567288 147.78%
|
||||
7 20688755 93.88%
|
||||
8 288794928 1310.43%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 356679957 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 8956.578947 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6409.949165 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 356678437 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 13614000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 1520 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 143 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 8826500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 354588627 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 33291.255289 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34798.042059 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 354586500 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 70810500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 2127 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 748 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 47986500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 1377 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses 1379 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 259025.734931 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 257319.666183 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 356679957 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 8956.578947 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6409.949165 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 356678437 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 13614000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 1520 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 143 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 8826500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_accesses 354588627 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 33291.255289 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 354586500 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 70810500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 2127 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 748 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 47986500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 1377 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 1379 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 356679957 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 8956.578947 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6409.949165 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 354588627 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 33291.255289 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 34798.042059 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 356678437 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 13614000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 1520 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 143 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 8826500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_hits 354586500 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 70810500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 2127 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 748 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 47986500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 1377 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 1379 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -222,180 +222,180 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 225 # number of replacements
|
||||
system.cpu.icache.sampled_refs 1377 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 222 # number of replacements
|
||||
system.cpu.icache.sampled_refs 1378 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1055.483361 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 356678437 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1057.993155 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 354586500 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 1248 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 127608554 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 350339648 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.854427 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 751913263 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 205327824 # Number of stores executed
|
||||
system.cpu.idleCycles 1503210 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 128154505 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 351416641 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.859194 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 749485536 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 207432555 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 1480064020 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1846024853 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.961974 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 1490113295 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 1862924805 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.963395 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1423783452 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.837143 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1859136578 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 92169933 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 589367 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 741823023 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 21373777 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 17132653 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 303434035 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2869227464 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 546585439 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 102564755 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1884138731 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 34478 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 1435567316 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.844742 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 1872447494 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 91815045 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 3100813 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 743909112 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 21390970 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 17059388 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 301399355 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2879831212 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 542052981 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 94512452 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 1894795224 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 42359 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 6242 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 239480011 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 64953 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 9887 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 239759981 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 75706 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 115050896 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 46197 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 115767211 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 47414 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 6187252 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 5 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 339305781 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 136576079 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 6187252 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 1512583 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 90657350 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.637426 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.637426 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 1986703486 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 5474059 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 341391869 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 134541399 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 5474059 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 1481544 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 90333501 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.637377 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.637377 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 1989307676 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
No_OpClass 0 0.00% # Type of FU issued
|
||||
IntAlu 1179878973 59.39% # Type of FU issued
|
||||
IntAlu 1186637130 59.65% # Type of FU issued
|
||||
IntMult 0 0.00% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 3034527 0.15% # Type of FU issued
|
||||
FloatAdd 2990817 0.15% # Type of FU issued
|
||||
FloatCmp 0 0.00% # Type of FU issued
|
||||
FloatCvt 0 0.00% # Type of FU issued
|
||||
FloatMult 0 0.00% # Type of FU issued
|
||||
FloatDiv 0 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 573304663 28.86% # Type of FU issued
|
||||
MemWrite 230485323 11.60% # Type of FU issued
|
||||
MemRead 571681967 28.74% # Type of FU issued
|
||||
MemWrite 227997762 11.46% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 3941252 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.001984 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 4014629 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.002018 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
No_OpClass 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 143239 3.63% # attempts to use FU when none available
|
||||
IntAlu 142220 3.54% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 224135 5.69% # attempts to use FU when none available
|
||||
FloatAdd 232758 5.80% # attempts to use FU when none available
|
||||
FloatCmp 0 0.00% # attempts to use FU when none available
|
||||
FloatCvt 0 0.00% # attempts to use FU when none available
|
||||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 3231256 81.99% # attempts to use FU when none available
|
||||
MemWrite 342622 8.69% # attempts to use FU when none available
|
||||
MemRead 3328923 82.92% # attempts to use FU when none available
|
||||
MemWrite 310728 7.74% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 2205147925
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 2203815119
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 1087983599 4933.83%
|
||||
1 585856114 2656.77%
|
||||
2 293424201 1330.63%
|
||||
3 167599230 760.04%
|
||||
4 47518525 215.49%
|
||||
5 16542278 75.02%
|
||||
6 5287445 23.98%
|
||||
7 801144 3.63%
|
||||
8 135389 0.61%
|
||||
0 1083882017 4918.21%
|
||||
1 586425796 2660.96%
|
||||
2 298714416 1355.44%
|
||||
3 164995052 748.68%
|
||||
4 47215795 214.25%
|
||||
5 14943133 67.81%
|
||||
6 6716024 30.47%
|
||||
7 790185 3.59%
|
||||
8 132701 0.60%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 0.900938 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 2497217188 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 1986703486 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 21670628 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 1069660701 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 613054 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 19426957 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1294993120 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 272214 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 5811.034701 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2811.034701 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1581845000 # number of ReadExReq miss cycles
|
||||
system.cpu.iq.ISSUE:rate 0.902050 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 2506731523 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 1989307676 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 21683048 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 1079315476 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 646020 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 19439377 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 1293054260 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 279061 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34294.559254 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31161.513074 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 9570274000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 272214 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 765203000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_misses 279061 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 8695963000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 272214 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 228421 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 5108.517819 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2108.517819 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 193459 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 178604000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.153059 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 34962 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 73718000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.153059 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 34962 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 69801 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5210.620192 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2210.777783 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 363706500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 279061 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 249692 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34106.905217 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.384556 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 214675 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1194321500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.140241 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 35017 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1085610500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.140241 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 35017 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 72896 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34203.262182 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31019.788466 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 2493281000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 69801 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154314500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 72896 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2261218500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 69801 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 338803 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 338803 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 72896 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 348745 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 348745 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 3.926755 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 4.234582 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 500635 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 5731.075996 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2731.075996 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 193459 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1760449000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.613573 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 307176 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 528753 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34273.637440 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31143.771611 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 214675 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 10764595500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.593998 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 314078 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 838921000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.613573 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 307176 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 9781573500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.593998 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 314078 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 500635 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 5731.075996 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2731.075996 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 528753 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34273.637440 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31143.771611 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 193459 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1760449000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.613573 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 307176 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 214675 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 10764595500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.593998 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 314078 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 838921000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.613573 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 307176 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 9781573500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.593998 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 314078 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -407,32 +407,33 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 84458 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 99911 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 84497 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 99948 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 16412.598383 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 392326 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 16402.911294 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 423238 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 61939 # number of writebacks
|
||||
system.cpu.numCycles 2205149173 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 14473235 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1244779248 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:FullRegisterEvents 14 # Number of times there has been no free registers
|
||||
system.cpu.rename.RENAME:IQFullEvents 33041 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 831090066 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 23088137 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 4934375551 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 3102245036 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 2427299354 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 719533567 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 239480011 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 32278503 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 1182520106 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 368292543 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 22008551 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 170259176 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 21764852 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 5225 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.l2cache.writebacks 61945 # number of writebacks
|
||||
system.cpu.numCycles 2205318329 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 17694794 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1244779250 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:FullRegisterEvents 863 # Number of times there has been no free registers
|
||||
system.cpu.rename.RENAME:IQFullEvents 27112 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 826425908 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 23298987 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 4917191839 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 3093611624 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 2420068293 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 717791899 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 239759981 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 32521117 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 1175289043 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 369621420 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 21984764 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 170791733 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 21775085 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 43186 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7005
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 23 2008 16:00:51
|
||||
M5 started Wed Jul 23 16:00:54 2008
|
||||
M5 executing on blue
|
||||
M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf
|
||||
M5 commit date Wed Jul 23 15:35:08 2008 -0700
|
||||
M5 compiled Aug 2 2008 17:21:13
|
||||
M5 started Sat Aug 2 17:21:17 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing tests/run.py long/00.gzip/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
spec_init
|
||||
|
|
@ -43,4 +43,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 1102574586000 because target called exit()
|
||||
Exiting @ tick 1102659164000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -192,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 2417575 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 214112 # Number of bytes of host memory used
|
||||
host_seconds 616.12 # Real time elapsed on the host
|
||||
host_tick_rate 3359990664 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1927863 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 202560 # Number of bytes of host memory used
|
||||
host_seconds 772.63 # Real time elapsed on the host
|
||||
host_tick_rate 2692643700 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1489523295 # Number of instructions simulated
|
||||
sim_seconds 2.070168 # Number of seconds simulated
|
||||
sim_ticks 2070168106000 # Number of ticks simulated
|
||||
sim_seconds 2.080416 # Number of seconds simulated
|
||||
sim_ticks 2080416155000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 16193.228451 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13193.228451 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 21085.814994 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.814994 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 3133163000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 4079810000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2552705000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3499352000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_miss_latency 1080000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 960000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 26999.993742 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.993742 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.993742 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.993742 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 166527221 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 8629063000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 17897318000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.001915 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 319595 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 7670278000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 16938533000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001915 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 319595 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 22924.696101 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 19924.696101 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 42833.642251 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 39833.642251 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 568846579 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 11762226000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 21977128000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 513081 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 10222983000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 20437885000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 513081 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 22924.696101 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 19924.696101 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 42833.642251 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 39833.642251 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 568846579 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 11762226000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 21977128000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 513081 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 10222983000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 20437885000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 513081 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 449125 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4095.496088 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4095.205833 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 375475000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 596368000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 316420 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 1489528206 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 26953.026197 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23953.026197 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1489527099 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 29837000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 61824000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 1107 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 26516000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 58503000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 1107 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 1489528206 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 26953.026197 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 23953.026197 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1489527099 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 29837000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 61824000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 1107 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 26516000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 58503000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 1107 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 1489528206 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 26953.026197 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 23953.026197 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 1489527099 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 29837000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 1107 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 26516000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 58503000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 1107 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -148,37 +148,37 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 118 # number of replacements
|
||||
system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 906.562887 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 906.330613 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1489527099 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 5973905000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 13506220000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 259735 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2857085000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 10389400000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 259735 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 160847 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 776158000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1754792000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.173418 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 33746 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 371206000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1349840000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173418 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 33746 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 59900 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22999.232053 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 1377654000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.263773 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 3114696000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 59900 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 658900000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2396000000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 59900 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 316420 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -192,29 +192,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 160847 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 6750063000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 15261012000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.645967 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 293481 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 3228291000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 11739240000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.645967 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 293481 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 160847 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 6750063000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 15261012000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.645967 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 293481 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 3228291000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 11739240000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.645967 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 293481 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -231,12 +231,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 82905 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 98339 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 16362.166769 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 16356.207611 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 337181 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 61861 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 4140336212 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 4160832310 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 1489523295 # Number of instructions executed
|
||||
system.cpu.num_refs 569365767 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7002
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7006
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 23 2008 16:00:51
|
||||
M5 started Wed Jul 23 16:02:08 2008
|
||||
M5 executing on blue
|
||||
M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf
|
||||
M5 commit date Wed Jul 23 15:35:08 2008 -0700
|
||||
M5 compiled Aug 2 2008 17:21:13
|
||||
M5 started Sat Aug 2 17:23:47 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing tests/run.py long/00.gzip/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
spec_init
|
||||
|
|
@ -43,4 +43,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 2070168106000 because target called exit()
|
||||
Exiting @ tick 2080416155000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -192,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:268435455
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 2198270 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 346304 # Number of bytes of host memory used
|
||||
host_seconds 110.92 # Real time elapsed on the host
|
||||
host_tick_rate 3278529226 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1384402 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 334744 # Number of bytes of host memory used
|
||||
host_seconds 176.13 # Real time elapsed on the host
|
||||
host_tick_rate 2080531769 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 243835278 # Number of instructions simulated
|
||||
sim_seconds 0.363660 # Number of seconds simulated
|
||||
sim_ticks 363659868000 # Number of ticks simulated
|
||||
sim_seconds 0.366446 # Number of seconds simulated
|
||||
sim_ticks 366445521000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14002.999360 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11002.999360 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 14009.690242 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.690242 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 81327577 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 12502676000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 12508650000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 892857 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 9824105000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 9830079000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.010859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 892857 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_hits 3878 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_miss_latency 216000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency 448000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.002059 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_misses 8 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 192000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 424000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.002059 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 8 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 22806988 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 2564001000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 5317928000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.004147 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 94963 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2279112000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5033039000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.004147 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 94963 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 15252.451864 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 12252.451864 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 18046.382944 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 104134565 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 15066677000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 17826578000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.009397 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 987820 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 12103217000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 14863118000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.009397 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 987820 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 15252.451864 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 12252.451864 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 18046.382944 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 15046.382944 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 104134565 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 15066677000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 17826578000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.009397 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 987820 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 12103217000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 14863118000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.009397 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 987820 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 935475 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 3566.422282 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 3569.547350 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 134205827000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 134389803000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 94875 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 244431627 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 26970.521542 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23970.521542 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 55904.761905 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52904.761905 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 244430745 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 23788000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 49308000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 21142000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 46662000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 244431627 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 26970.521542 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 23970.521542 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 55904.761905 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 244430745 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 23788000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 49308000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 882 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 21142000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 46662000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 882 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 244431627 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 26970.521542 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 23970.521542 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 55904.761905 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 244430745 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 23788000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 49308000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 882 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 21142000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 46662000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 882 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -148,37 +148,37 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 25 # number of replacements
|
||||
system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 725.877742 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 726.233997 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 244430745 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 46714 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1074422000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2429128000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 46714 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 513854000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1868560000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 46714 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 893739 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 892653 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 24978000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 56472000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.001215 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1086 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 11946000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 43440000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001215 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1086 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 48257 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 1109911000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 2509364000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 48257 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530827000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1930280000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 48257 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 94875 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -192,29 +192,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 892653 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1099400000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 2485600000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.050827 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 47800 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 525800000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1912000000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.050827 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 47800 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 892653 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1099400000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 2485600000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.050827 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 47800 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 525800000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1912000000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.050827 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 47800 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -231,12 +231,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 891 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 15559 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 8943.216339 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 8958.603097 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 802210 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 41 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 727319736 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 732891042 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 243835278 # Number of instructions executed
|
||||
system.cpu.num_refs 105711442 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 443 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7004
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 23 2008 16:00:51
|
||||
M5 started Wed Jul 23 16:00:53 2008
|
||||
M5 executing on blue
|
||||
M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf
|
||||
M5 commit date Wed Jul 23 15:35:08 2008 -0700
|
||||
M5 compiled Aug 2 2008 17:21:13
|
||||
M5 started Sat Aug 2 17:25:03 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing tests/run.py long/10.mcf/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
||||
|
|
@ -28,4 +28,4 @@ simplex iterations : 2663
|
|||
flow value : 3080014995
|
||||
checksum : 68389
|
||||
optimal
|
||||
Exiting @ tick 363659868000 because target called exit()
|
||||
Exiting @ tick 366445521000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -368,6 +368,7 @@ cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels
|
|||
cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
gid=100
|
||||
|
|
@ -393,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 37055347 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 45947414 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 1096 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 5691744 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 35558640 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 62480259 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 12398507 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 99164 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 157680 # Number of bytes of host memory used
|
||||
host_seconds 3787.43 # Real time elapsed on the host
|
||||
host_tick_rate 35615266 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 72769124 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 54049353 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 125306666 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 92782205 # Number of stores inserted to the mem dependence unit.
|
||||
global.BPredUnit.BTBHits 38296034 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 45834466 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 1077 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 5781170 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 35418150 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 62209737 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 12344504 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 169173 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 208828 # Number of bytes of host memory used
|
||||
host_seconds 2220.07 # Real time elapsed on the host
|
||||
host_tick_rate 60807494 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 73961217 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 54131405 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 124841223 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 92324076 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 375574819 # Number of instructions simulated
|
||||
sim_seconds 0.134890 # Number of seconds simulated
|
||||
sim_ticks 134890208500 # Number of ticks simulated
|
||||
sim_seconds 0.134997 # Number of seconds simulated
|
||||
sim_ticks 134996684500 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 44587532 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 13065530 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 13163574 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 254286247
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 254545672
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 123470433 4855.57%
|
||||
1 49744073 1956.22%
|
||||
2 18820215 740.12%
|
||||
3 19293865 758.75%
|
||||
4 12510791 492.00%
|
||||
5 8575068 337.22%
|
||||
6 5688152 223.69%
|
||||
7 3118120 122.62%
|
||||
8 13065530 513.81%
|
||||
0 123085209 4835.49%
|
||||
1 50466868 1982.63%
|
||||
2 18758377 736.94%
|
||||
3 19955031 783.95%
|
||||
4 11844121 465.30%
|
||||
5 8478667 333.09%
|
||||
6 5819307 228.62%
|
||||
7 2974518 116.86%
|
||||
8 13163574 517.14%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
|
|
@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 100651995 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 174183397 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 5687554 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 5776994 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 96777858 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 94782663 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 375574819 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.718313 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.718313 # CPI: Total CPI of All Threads
|
||||
system.cpu.cpi 0.718880 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.718880 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 95885716 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 9843.626807 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7312.880325 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 95884194 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 14982000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1522 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 536 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 7210500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 95501309 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 33012.273524 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31966.971545 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 95499598 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 56484000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1711 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 727 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 31455500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 986 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 984 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 9673.649142 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7598.791541 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 73509773 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 105984500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000149 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 10956 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 7646 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 25152000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 30310.747349 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36196.886371 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 73502716 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 545987492 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000245 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 18013 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 14704 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 119775497 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 3310 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.WriteReq_mshr_misses 3309 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs 3249.700000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 40554.032799 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_refs 40460.273163 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 32497 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 169406445 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 9694.382113 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 7533.170391 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 169393967 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 120966500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000074 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 12478 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 8182 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 32362500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_accesses 169022038 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 30545.096938 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 169002314 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 602471492 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000117 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 19724 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 15431 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 151230997 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 4296 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 4293 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 169406445 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 9694.382113 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 7533.170391 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 169022038 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 30545.096938 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 35227.346145 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 169393967 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 120966500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000074 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 12478 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 8182 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 32362500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_hits 169002314 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 602471492 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000117 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 19724 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 15431 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 151230997 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 4296 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 4293 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -120,104 +120,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 781 # number of replacements
|
||||
system.cpu.dcache.replacements 782 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 4177 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 3296.858616 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 169394195 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 3293.970402 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 169002561 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 636 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 18955564 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 4312 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 11369096 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 533723337 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 133094788 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 100949486 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 15490881 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 12729 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 1286410 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 186077432 # DTB accesses
|
||||
system.cpu.dtb.acv 11216 # DTB access violations
|
||||
system.cpu.dtb.hits 186006805 # DTB hits
|
||||
system.cpu.dtb.misses 70627 # DTB misses
|
||||
system.cpu.dtb.read_accesses 104841123 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 11216 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 104772046 # DTB read hits
|
||||
system.cpu.dtb.read_misses 69077 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 81236309 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 81234759 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1550 # DTB write misses
|
||||
system.cpu.fetch.Branches 62480259 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 64020665 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 168778939 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1468351 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 547045642 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 6042059 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.231597 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 64020665 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 49453854 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.027744 # Number of inst fetches per cycle
|
||||
system.cpu.dcache.writebacks 635 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 18875032 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 4277 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 11323346 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 531939828 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 132443197 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 101952317 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 15306974 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 12561 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 1275127 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 185115437 # DTB accesses
|
||||
system.cpu.dtb.acv 1 # DTB access violations
|
||||
system.cpu.dtb.hits 185076670 # DTB hits
|
||||
system.cpu.dtb.misses 38767 # DTB misses
|
||||
system.cpu.dtb.read_accesses 104449499 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 104412186 # DTB read hits
|
||||
system.cpu.dtb.read_misses 37313 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 80665938 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 1 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 80664484 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1454 # DTB write misses
|
||||
system.cpu.fetch.Branches 62209737 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 63866189 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 169616790 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 1519057 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 544903543 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 6123543 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.230412 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 63866189 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 50640538 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.018211 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 269777129
|
||||
system.cpu.fetch.rateDist.samples 269852647
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 165019149 6116.87%
|
||||
1 11208105 415.46%
|
||||
2 10970042 406.63%
|
||||
3 7809028 289.46%
|
||||
4 16007682 593.37%
|
||||
5 8770390 325.10%
|
||||
6 6686429 247.85%
|
||||
7 3981315 147.58%
|
||||
8 39324989 1457.68%
|
||||
0 164102333 6081.18%
|
||||
1 12367121 458.29%
|
||||
2 12410556 459.90%
|
||||
3 6615129 245.14%
|
||||
4 15923029 590.06%
|
||||
5 8709903 322.77%
|
||||
6 6580254 243.85%
|
||||
7 4007808 148.52%
|
||||
8 39136514 1450.29%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 64020665 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 8765.688380 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6021.951220 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 64016474 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 36737000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000065 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 4191 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 296 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 23455500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 63866189 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 32249.018798 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 30883.598563 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 63861348 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 156117500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 4841 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 945 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 120322500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 3895 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 16435.551733 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 16391.516427 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 64020665 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 8765.688380 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6021.951220 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 64016474 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 36737000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000065 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 4191 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 296 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 23455500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_accesses 63866189 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 32249.018798 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 63861348 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 156117500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 4841 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 945 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 120322500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 3895 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 64020665 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 8765.688380 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6021.951220 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 63866189 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 32249.018798 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 30883.598563 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 64016474 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 36737000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000065 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 4191 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 296 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 23455500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_hits 63861348 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 156117500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 4841 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 945 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 120322500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 3895 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -229,184 +229,184 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 1973 # number of replacements
|
||||
system.cpu.icache.sampled_refs 3895 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 1975 # number of replacements
|
||||
system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1826.958701 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 64016474 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1823.540410 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 63861348 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 3290 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 51062363 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 27214999 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.560789 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 192842691 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 81246989 # Number of stores executed
|
||||
system.cpu.idleCycles 140725 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 50976852 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 27164335 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.553144 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 191842297 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 80676625 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 287107823 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 417299912 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.702706 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 285463488 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 415481244 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.703314 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 201752289 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.546813 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 418066212 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 6311133 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 2198946 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 125306666 # Number of dispatched load instructions
|
||||
system.cpu.iew.WB:producers 200770523 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.538857 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 416287471 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 6390314 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 2178518 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 124841223 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 239 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 6339692 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 92782205 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 495443138 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 111595702 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 10411801 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 421070304 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 127438 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewDispSquashedInsts 6302760 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 92324076 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 493447669 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 111165672 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 10261542 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 419338657 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 25079 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 23538 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 15490881 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 491568 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 23746 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 15306974 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 341836 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 8710387 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 3327 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 8734674 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 2193 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 505299 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 175942 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 24654671 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 19250803 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 505299 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 821714 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 5489419 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.392150 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.392150 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 431482105 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 436213 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 176181 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 24189228 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 18792674 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 436213 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 847804 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 5542510 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.391052 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.391052 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 429600199 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
No_OpClass 33581 0.01% # Type of FU issued
|
||||
IntAlu 167002612 38.70% # Type of FU issued
|
||||
IntMult 2153139 0.50% # Type of FU issued
|
||||
IntAlu 166319017 38.71% # Type of FU issued
|
||||
IntMult 2152935 0.50% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 34874757 8.08% # Type of FU issued
|
||||
FloatCmp 7889981 1.83% # Type of FU issued
|
||||
FloatCvt 2903377 0.67% # Type of FU issued
|
||||
FloatMult 16803027 3.89% # Type of FU issued
|
||||
FloatDiv 1591666 0.37% # Type of FU issued
|
||||
FloatAdd 35077566 8.17% # Type of FU issued
|
||||
FloatCmp 7830879 1.82% # Type of FU issued
|
||||
FloatCvt 2898460 0.67% # Type of FU issued
|
||||
FloatMult 16788316 3.91% # Type of FU issued
|
||||
FloatDiv 1569716 0.37% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 114230521 26.47% # Type of FU issued
|
||||
MemWrite 83999444 19.47% # Type of FU issued
|
||||
MemRead 113503270 26.42% # Type of FU issued
|
||||
MemWrite 83426459 19.42% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 10446664 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.024211 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 10457046 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.024341 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
No_OpClass 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 32363 0.31% # attempts to use FU when none available
|
||||
IntAlu 40640 0.39% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 95689 0.92% # attempts to use FU when none available
|
||||
FloatCmp 7492 0.07% # attempts to use FU when none available
|
||||
FloatCvt 12721 0.12% # attempts to use FU when none available
|
||||
FloatMult 1683122 16.11% # attempts to use FU when none available
|
||||
FloatDiv 1408746 13.49% # attempts to use FU when none available
|
||||
FloatAdd 76056 0.73% # attempts to use FU when none available
|
||||
FloatCmp 13381 0.13% # attempts to use FU when none available
|
||||
FloatCvt 12891 0.12% # attempts to use FU when none available
|
||||
FloatMult 1723474 16.48% # attempts to use FU when none available
|
||||
FloatDiv 1473560 14.09% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 5941492 56.87% # attempts to use FU when none available
|
||||
MemWrite 1265039 12.11% # attempts to use FU when none available
|
||||
MemRead 5907144 56.49% # attempts to use FU when none available
|
||||
MemWrite 1209900 11.57% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 269777129
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 269852647
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 99508340 3688.54%
|
||||
1 57898126 2146.15%
|
||||
2 39403533 1460.60%
|
||||
3 28850583 1069.42%
|
||||
4 24598298 911.80%
|
||||
5 10625217 393.85%
|
||||
6 6146486 227.84%
|
||||
7 2145397 79.52%
|
||||
8 601149 22.28%
|
||||
0 99465935 3685.94%
|
||||
1 57766030 2140.65%
|
||||
2 39984555 1481.72%
|
||||
3 29664957 1099.30%
|
||||
4 23966119 888.12%
|
||||
5 10452564 387.34%
|
||||
6 5712017 211.67%
|
||||
7 2252970 83.49%
|
||||
8 587500 21.77%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 1.599383 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 468227900 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 431482105 # Number of instructions issued
|
||||
system.cpu.iq.ISSUE:rate 1.591151 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 466283095 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 429600199 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 239 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 91553989 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 1306748 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 89615992 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 918381 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 68680838 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 64020959 # ITB accesses
|
||||
system.cpu.iq.iqSquashedOperandsExamined 68228106 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 63866476 # ITB accesses
|
||||
system.cpu.itb.acv 0 # ITB acv
|
||||
system.cpu.itb.hits 64020665 # ITB hits
|
||||
system.cpu.itb.misses 294 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 3195 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 6098.591549 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 3098.591549 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 19485000 # number of ReadExReq miss cycles
|
||||
system.cpu.itb.hits 63866189 # ITB hits
|
||||
system.cpu.itb.misses 287 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 3197 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34596.340006 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31467.625899 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 110604499 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 3195 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 9900000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_misses 3197 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 100602000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 3195 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 4877 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 5592.080378 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2592.080378 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 647 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 23654500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.867336 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 4230 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 10964500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.867336 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 4230 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 121 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5698.347107 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2698.347107 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 689500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 3197 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 4876 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34359.867330 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31168.325041 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 655 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 145033000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.865669 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 4221 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 131561500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.865669 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 4221 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 119 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34441.176471 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31285.714286 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 4098500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 121 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 326500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 119 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3723000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 121 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 636 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 636 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 119 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 635 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 635 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs 3000 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.128309 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.130240 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 2 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 6000 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 8072 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 5810.033670 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2810.033670 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 647 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 43139500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.919846 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7425 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 8073 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34461.782017 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 655 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 255637499 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.918865 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7418 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 20864500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.919846 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7425 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 232163500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.918865 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7418 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 8072 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 5810.033670 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2810.033670 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 8073 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34461.782017 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31297.317336 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 647 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 43139500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.919846 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7425 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 655 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 255637499 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.918865 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7418 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 20864500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.919846 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7425 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 232163500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.918865 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7418 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -418,31 +418,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 15 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 4684 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 14 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 4676 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 3884.477480 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 601 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 3875.343408 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 609 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 269780419 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 8898218 # Number of cycles rename is blocking
|
||||
system.cpu.numCycles 269993372 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 8452992 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 1493929 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 138057394 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 7378387 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 685335905 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 519882318 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 336260549 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 96875532 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 15490881 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 10098203 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 76728208 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 356901 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 37939 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 22218757 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:IQFullEvents 1780176 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 137359458 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 7392558 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 684397837 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 518816398 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 335732022 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 97960614 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 15306974 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 10399659 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 76199681 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 372950 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 37950 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 22290547 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 251 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 727 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.timesIdled 3086 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
getting pixel output filename pixels_out.cook
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 21 2008 20:12:56
|
||||
M5 started Mon Jul 21 20:12:58 2008
|
||||
M5 compiled Aug 2 2008 17:07:15
|
||||
M5 started Sat Aug 2 17:07:19 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
|
||||
M5 commit date Tue Jul 15 14:38:51 2008 -0400
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing tests/run.py long/30.eon/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Eon, Version 1.1
|
||||
|
|
|
|||
|
|
@ -166,6 +166,7 @@ cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels
|
|||
cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
|
||||
gid=100
|
||||
|
|
@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 948947 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 204452 # Number of bytes of host memory used
|
||||
host_seconds 420.11 # Real time elapsed on the host
|
||||
host_tick_rate 1349967290 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1657758 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 207956 # Number of bytes of host memory used
|
||||
host_seconds 240.48 # Real time elapsed on the host
|
||||
host_tick_rate 2359203743 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 398664609 # Number of instructions simulated
|
||||
sim_seconds 0.567139 # Number of seconds simulated
|
||||
sim_ticks 567138642000 # Number of ticks simulated
|
||||
sim_seconds 0.567352 # Number of seconds simulated
|
||||
sim_ticks 567351850000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 25398.947368 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22398.947368 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 94753540 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 24129000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 48286000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000010 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 950 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 21279000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 45436000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 73517416 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 89478000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 185584000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 3314 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 79536000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 175642000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 3314 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 26643.292683 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23643.292683 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 54847.560976 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 168270956 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 113607000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 233870000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 4264 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 100815000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 221078000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 4264 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 26643.292683 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23643.292683 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 54847.560976 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 168270956 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 113607000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 233870000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 4264 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 100815000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 221078000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 4264 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 764 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 3289.418113 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 3288.899192 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 625 # number of writebacks
|
||||
|
|
@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
|
|||
system.cpu.dtb.write_hits 73520730 # DTB write hits
|
||||
system.cpu.dtb.write_misses 35 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 398664666 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 25343.588347 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 22343.588347 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 50648.516199 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 47648.516199 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 398660993 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 93087000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 186032000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 82068000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 175013000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 3673 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 398664666 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 25343.588347 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 22343.588347 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 50648.516199 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 398660993 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 93087000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 186032000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 82068000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 175013000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 3673 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 25343.588347 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 22343.588347 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 398660993 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 93087000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 186032000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 3673 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 82068000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 175013000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 3673 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 1769 # number of replacements
|
||||
system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1795.354000 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1795.124700 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -160,31 +160,31 @@ system.cpu.itb.acv 0 # IT
|
|||
system.cpu.itb.hits 398664666 # ITB hits
|
||||
system.cpu.itb.misses 173 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 73646000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 166504000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 3202 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 35222000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 128080000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 3202 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 585 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 92874000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 209976000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.873459 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 4038 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 44418000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 112 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 2576000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 5824000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 112 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1232000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4480000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -198,29 +198,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 585 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 166520000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 376480000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.925240 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7240 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 79640000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 289600000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.925240 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7240 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 585 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 166520000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 376480000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.925240 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7240 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 79640000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 289600000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.925240 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7240 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 15 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 4491 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 3714.818787 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 3714.176115 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 540 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1134277284 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1134703700 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 398664609 # Number of instructions executed
|
||||
system.cpu.num_refs 174183455 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7002
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7005
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
getting pixel output filename pixels_out.cook
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 21 2008 20:12:56
|
||||
M5 started Mon Jul 21 20:13:28 2008
|
||||
M5 compiled Aug 2 2008 17:07:15
|
||||
M5 started Sat Aug 2 17:16:23 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
|
||||
M5 commit date Tue Jul 15 14:38:51 2008 -0400
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing tests/run.py long/30.eon/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Eon, Version 1.1
|
||||
|
|
|
|||
|
|
@ -166,6 +166,7 @@ cmd=perlbmk -I. -I lib lgred.makerand.pl
|
|||
cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
gid=100
|
||||
|
|
@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1017888 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 209744 # Number of bytes of host memory used
|
||||
host_seconds 1973.68 # Real time elapsed on the host
|
||||
host_tick_rate 1403993769 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1695111 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 207112 # Number of bytes of host memory used
|
||||
host_seconds 1185.17 # Real time elapsed on the host
|
||||
host_tick_rate 2375153470 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2008987605 # Number of instructions simulated
|
||||
sim_seconds 2.771038 # Number of seconds simulated
|
||||
sim_ticks 2771037759000 # Number of ticks simulated
|
||||
sim_seconds 2.814951 # Number of seconds simulated
|
||||
sim_ticks 2814951154000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 26811.881426 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23811.881426 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 55392.232299 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52392.232299 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 39096871000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 80772510000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 34722295000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 76397934000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 26999.692460 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.692460 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.692460 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.692460 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 210720109 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 2019226000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 4188049000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000355 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 74787 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1794865000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3963688000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 74787 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 26821.043863 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23821.043863 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 55421.867488 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 720331943 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 41116097000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 84960559000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002124 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1532979 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 36517160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 80361622000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002124 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1532979 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 26821.043863 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23821.043863 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 55421.867488 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 720331943 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 41116097000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 84960559000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002124 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1532979 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 36517160000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 80361622000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002124 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1532979 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 1526048 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4095.350762 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4095.198740 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 812770000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 1054514000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 74589 # number of writebacks
|
||||
system.cpu.dtb.accesses 722298387 # DTB accesses
|
||||
system.cpu.dtb.acv 0 # DTB access violations
|
||||
|
|
@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
|
|||
system.cpu.dtb.write_hits 210794896 # DTB write hits
|
||||
system.cpu.dtb.write_misses 14581 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 2009421071 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 16916.289166 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 13916.289166 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 23421.857305 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 20421.857305 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 2009410475 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 179245000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 248178000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 147457000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 216390000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 2009421071 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 16916.289166 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 13916.289166 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 23421.857305 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 2009410475 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 179245000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 248178000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 147457000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 216390000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 16916.289166 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 13916.289166 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 2009410475 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 179245000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 248178000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 10596 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 147457000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 216390000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 9046 # number of replacements
|
||||
system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1478.550297 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1478.420115 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -160,31 +160,31 @@ system.cpu.itb.acv 0 # IT
|
|||
system.cpu.itb.hits 2009421071 # ITB hits
|
||||
system.cpu.itb.misses 105 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1654896000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3741504000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 71952 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 791472000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2878080000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 71952 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 1468788 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 29320 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 33107764000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 74852336000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.980038 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1439468 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 15834148000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 57578720000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980038 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1439468 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 2835 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22813.403880 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 64676000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51578.130511 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 146224000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 2835 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31185000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 113400000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 2835 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -198,29 +198,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 29320 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 34762660000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 78593840000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.980970 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 1511420 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 16625620000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 60456800000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.980970 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 1511420 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 29320 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 34762660000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 78593840000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.980970 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 1511420 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 16625620000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 60456800000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.980970 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 1511420 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 1473608 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 1506166 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 31923.721558 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 31910.237485 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 35763 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 66899 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 5542075518 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 5629902308 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2008987605 # Number of instructions executed
|
||||
system.cpu.num_refs 722823898 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7007
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7002
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
warn: ignoring syscall sigprocmask(1, 0, ...)
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 21 2008 20:12:56
|
||||
M5 started Mon Jul 21 20:13:00 2008
|
||||
M5 compiled Aug 2 2008 17:07:15
|
||||
M5 started Sat Aug 2 17:07:20 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
|
||||
M5 commit date Tue Jul 15 14:38:51 2008 -0400
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing tests/run.py long/40.perlbmk/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
1375000: 2038431008
|
||||
|
|
|
|||
|
|
@ -368,6 +368,7 @@ cmd=vortex lendian.raw
|
|||
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
|
|
@ -393,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 8028209 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 14249713 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 35529 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 455745 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 10549276 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 16239906 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 1939086 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 108698 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 171788 # Number of bytes of host memory used
|
||||
host_seconds 732.23 # Real time elapsed on the host
|
||||
host_tick_rate 34286652 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 12312682 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 10887004 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 22965315 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 16290741 # Number of stores inserted to the mem dependence unit.
|
||||
global.BPredUnit.BTBHits 8039248 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 14256738 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 34579 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 452707 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 10551562 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 16249458 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 1941929 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 176565 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 212168 # Number of bytes of host memory used
|
||||
host_seconds 450.78 # Real time elapsed on the host
|
||||
host_tick_rate 60195419 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 12835812 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 11558188 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 23001211 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 16328870 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 79591756 # Number of instructions simulated
|
||||
sim_seconds 0.025106 # Number of seconds simulated
|
||||
sim_ticks 25105678500 # Number of ticks simulated
|
||||
sim_seconds 0.027135 # Number of seconds simulated
|
||||
sim_ticks 27134783500 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 13754477 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 3423734 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 3320893 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 48941983
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 51751153
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 20096984 4106.29%
|
||||
1 10996856 2246.92%
|
||||
2 5104227 1042.91%
|
||||
3 3459002 706.76%
|
||||
4 2556441 522.34%
|
||||
5 1507300 307.98%
|
||||
6 975853 199.39%
|
||||
7 821586 167.87%
|
||||
8 3423734 699.55%
|
||||
0 22506428 4348.97%
|
||||
1 11357580 2194.65%
|
||||
2 5114502 988.29%
|
||||
3 3560855 688.07%
|
||||
4 2552506 493.23%
|
||||
5 1532718 296.17%
|
||||
6 1008932 194.96%
|
||||
7 796739 153.96%
|
||||
8 3320893 641.70%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
|
|
@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 20379399 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 35224018 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 360068 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 358406 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 8053439 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 8296832 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.630861 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.630861 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 20452895 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 8143.771495 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4564.311373 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 20307515 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 1183941500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.007108 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 145380 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 83859 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 280801000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003008 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 61521 # number of ReadReq MSHR misses
|
||||
system.cpu.cpi 0.681849 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.681849 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 20425511 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 30386.313820 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20952.491225 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 20275871 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4547008000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.007326 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 149640 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 88104 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1289332500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.003013 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 61536 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 7484.182742 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7344.479005 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 13603341 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 7559294000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.069117 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1010036 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 860217 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1100342500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010252 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 149819 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 165.460856 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 32256.481584 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35750.692621 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 13563056 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 33879659994 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.071874 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1050321 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 900532 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5355060497 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 149789 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs 3166.333333 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets 27000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 165.103746 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 6 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 18998 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 27000 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 35066272 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 7567.175372 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 6535.173181 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 33910856 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 8743235500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.032949 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1155416 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 944076 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 1381143500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.006027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 211340 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 35038888 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 32023.264084 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 33838927 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 38426667994 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.034247 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1199961 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 988636 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 6644392997 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.006031 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 211325 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 35066272 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 7567.175372 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 6535.173181 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 35038888 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 32023.264084 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 31441.585222 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 33910856 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 8743235500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.032949 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1155416 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 944076 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 1381143500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.006027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 211340 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 33838927 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 38426667994 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.034247 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1199961 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 988636 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 6644392997 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.006031 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 211325 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -120,104 +120,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 200914 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 205010 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 200933 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 205029 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4080.749840 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 33921130 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 125269000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 147756 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 1159763 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 96488 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 3648673 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 101620182 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 28148001 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 19589576 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 1262270 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 284391 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 44644 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 36627367 # DTB accesses
|
||||
system.cpu.dcache.tagsinuse 4077.325791 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 33851056 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 183212000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 147760 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 3553972 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 95125 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 3655574 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 101758297 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 28531772 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 19520692 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 1290098 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 284696 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 144718 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 36599686 # DTB accesses
|
||||
system.cpu.dtb.acv 39 # DTB access violations
|
||||
system.cpu.dtb.hits 36456086 # DTB hits
|
||||
system.cpu.dtb.misses 171281 # DTB misses
|
||||
system.cpu.dtb.read_accesses 21562223 # DTB read accesses
|
||||
system.cpu.dtb.hits 36425478 # DTB hits
|
||||
system.cpu.dtb.misses 174208 # DTB misses
|
||||
system.cpu.dtb.read_accesses 21541286 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 37 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 21405571 # DTB read hits
|
||||
system.cpu.dtb.read_misses 156652 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 15065144 # DTB write accesses
|
||||
system.cpu.dtb.read_hits 21383018 # DTB read hits
|
||||
system.cpu.dtb.read_misses 158268 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 15058400 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 2 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 15050515 # DTB write hits
|
||||
system.cpu.dtb.write_misses 14629 # DTB write misses
|
||||
system.cpu.fetch.Branches 16239906 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 13373612 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 33209884 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 156374 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 103204931 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 573221 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.323431 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 13373612 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 9967295 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.055410 # Number of inst fetches per cycle
|
||||
system.cpu.dtb.write_hits 15042460 # DTB write hits
|
||||
system.cpu.dtb.write_misses 15940 # DTB write misses
|
||||
system.cpu.fetch.Branches 16249458 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 13386072 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 33247227 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 153162 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 103308047 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 567638 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.299421 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 13386072 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 9981177 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.903609 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 50204254
|
||||
system.cpu.fetch.rateDist.samples 53041252
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 30393344 6053.94%
|
||||
1 1855009 369.49%
|
||||
2 1535971 305.94%
|
||||
3 1792342 357.01%
|
||||
4 4000264 796.80%
|
||||
5 1878750 374.22%
|
||||
6 697475 138.93%
|
||||
7 1087494 216.61%
|
||||
8 6963605 1387.05%
|
||||
0 33206262 6260.46%
|
||||
1 1871594 352.86%
|
||||
2 1529415 288.34%
|
||||
3 1809626 341.17%
|
||||
4 3985239 751.35%
|
||||
5 1867237 352.03%
|
||||
6 695846 131.19%
|
||||
7 1111736 209.60%
|
||||
8 6964297 1313.00%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 13373612 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 5755.491777 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2760.964989 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 13287028 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 498333500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.006474 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 86584 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 1153 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 235872000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.006388 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 85431 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 13386072 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 9527.365371 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6037.865388 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 13297365 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 845144000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.006627 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 88707 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 2771 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 518870000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.006420 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 85936 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 155.531172 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 154.737476 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 13373612 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 5755.491777 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2760.964989 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 13287028 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 498333500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.006474 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 86584 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 1153 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 235872000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.006388 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 85431 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 13386072 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 9527.365371 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 13297365 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 845144000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.006627 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 88707 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 2771 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 518870000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.006420 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 85936 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 13373612 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 5755.491777 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2760.964989 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 13386072 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 9527.365371 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6037.865388 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 13287028 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 498333500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.006474 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 86584 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 1153 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 235872000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.006388 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 85431 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 13297365 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 845144000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.006627 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 88707 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 2771 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 518870000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.006420 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 85936 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -229,80 +229,80 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 83382 # number of replacements
|
||||
system.cpu.icache.sampled_refs 85430 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 83888 # number of replacements
|
||||
system.cpu.icache.sampled_refs 85935 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1922.332648 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 13287028 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 21794210000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tagsinuse 1916.994932 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 13297365 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 7104 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 14739955 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 9377104 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.689247 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 36969517 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 15298022 # Number of stores executed
|
||||
system.cpu.idleCycles 1228316 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 14745483 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 9395656 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.562958 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 36941990 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 15291391 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 42338801 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 84336475 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.765870 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 42302247 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 84351843 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.765845 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 32426009 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.679629 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 84568976 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 400439 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 20274 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 22965315 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 4986 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 357828 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 16290741 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 98799135 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 21671495 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 539331 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 84819374 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 2040 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 32396966 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.554312 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 84585242 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 398232 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 627280 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 23001211 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 5004 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 362338 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 16328870 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 98972071 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 21650599 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 525286 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 84821030 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 11758 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 162 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 1262270 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 2540 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 8922 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 1290098 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 44030 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 11 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 951318 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 993 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 956127 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 709 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 20550 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1303 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 2585916 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 1446122 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 20550 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 108250 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 292189 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.585135 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.585135 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 85358705 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 16859 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1313 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 2621812 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 1484251 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 16859 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 106828 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 291404 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.466600 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.466600 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 85346316 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
No_OpClass 0 0.00% # Type of FU issued
|
||||
IntAlu 47875288 56.09% # Type of FU issued
|
||||
IntMult 42930 0.05% # Type of FU issued
|
||||
IntAlu 47898540 56.12% # Type of FU issued
|
||||
IntMult 42953 0.05% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 121387 0.14% # Type of FU issued
|
||||
FloatCmp 87 0.00% # Type of FU issued
|
||||
FloatCvt 121941 0.14% # Type of FU issued
|
||||
FloatMult 50 0.00% # Type of FU issued
|
||||
FloatDiv 38534 0.05% # Type of FU issued
|
||||
FloatAdd 121655 0.14% # Type of FU issued
|
||||
FloatCmp 88 0.00% # Type of FU issued
|
||||
FloatCvt 122104 0.14% # Type of FU issued
|
||||
FloatMult 53 0.00% # Type of FU issued
|
||||
FloatDiv 38535 0.05% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 21778158 25.51% # Type of FU issued
|
||||
MemWrite 15380330 18.02% # Type of FU issued
|
||||
MemRead 21753620 25.49% # Type of FU issued
|
||||
MemWrite 15368768 18.01% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 989684 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.011594 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 979635 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.011478 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
No_OpClass 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 96046 9.70% # attempts to use FU when none available
|
||||
IntAlu 97095 9.91% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 0 0.00% # attempts to use FU when none available
|
||||
|
|
@ -311,102 +311,102 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 442273 44.69% # attempts to use FU when none available
|
||||
MemWrite 451365 45.61% # attempts to use FU when none available
|
||||
MemRead 470602 48.04% # attempts to use FU when none available
|
||||
MemWrite 411938 42.05% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 50204254
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 53041252
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 15297066 3046.97%
|
||||
1 13336776 2656.50%
|
||||
2 8168141 1626.98%
|
||||
3 4718425 939.85%
|
||||
4 4728752 941.90%
|
||||
5 2063960 411.11%
|
||||
6 1191217 237.27%
|
||||
7 451074 89.85%
|
||||
8 248843 49.57%
|
||||
0 17563400 3311.27%
|
||||
1 13937997 2627.77%
|
||||
2 8266118 1558.43%
|
||||
3 4784811 902.09%
|
||||
4 4627571 872.45%
|
||||
5 2066742 389.65%
|
||||
6 1112371 209.72%
|
||||
7 454506 85.69%
|
||||
8 227736 42.94%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 1.699988 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 89417045 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 85358705 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 4986 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 9619776 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 47402 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 403 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 6577473 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 13398974 # ITB accesses
|
||||
system.cpu.iq.ISSUE:rate 1.572637 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 89571411 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 85346316 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 5004 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 9777285 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 49836 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 421 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 6793888 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 13412237 # ITB accesses
|
||||
system.cpu.itb.acv 0 # ITB acv
|
||||
system.cpu.itb.hits 13373612 # ITB hits
|
||||
system.cpu.itb.misses 25362 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 143489 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 5477.120197 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2477.120197 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 785906500 # number of ReadExReq miss cycles
|
||||
system.cpu.itb.hits 13386072 # ITB hits
|
||||
system.cpu.itb.misses 26165 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 143494 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.379953 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31233.455754 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 4927207999 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 143489 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 355439500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_misses 143494 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4481813500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 143489 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 146952 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 5163.421419 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2163.421419 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 102374 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 230175000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.303351 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 44578 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 96441000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.303351 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 44578 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 6345 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5226.319937 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2257.919622 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 33161000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 143494 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 147471 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34138.973013 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.558180 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 102894 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1521813000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.302276 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 44577 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1383427500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302276 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 44577 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 6344 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34041.535309 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31034.914880 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 215959500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 6345 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14326500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 6344 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 196885500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 6345 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 147756 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 147756 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 6344 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 147760 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 147760 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs 2000 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.675694 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.678680 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 1 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 2000 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 290441 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 5402.763377 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2402.763377 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 102374 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1016081500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.647522 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 188067 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 290965 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34290.353106 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31186.312616 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 102894 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 6449020999 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.646370 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 188071 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 451880500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.647522 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 188067 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 5865241000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.646370 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 188071 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 290441 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 5402.763377 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2402.763377 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 290965 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34290.353106 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31186.312616 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 102374 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1016081500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.647522 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 188067 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 102894 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 6449020999 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.646370 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 188071 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 451880500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.647522 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 188067 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 5865241000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.646370 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 188071 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -418,31 +418,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 148782 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 173999 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 148779 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 173998 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 18435.407852 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 117570 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 18483.932532 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 118089 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 120646 # number of writebacks
|
||||
system.cpu.numCycles 50211358 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 378329 # Number of cycles rename is blocking
|
||||
system.cpu.l2cache.writebacks 120647 # number of writebacks
|
||||
system.cpu.numCycles 54269568 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 2047036 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 33543 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 28456807 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 636231 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 121456625 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 100818725 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 60666627 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 19319540 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 1262270 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 711864 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 8119746 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 75444 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 5250 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 1518293 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 5248 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 2224 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 64601 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 28934159 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 1281103 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 21 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 121625281 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 100952073 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 60736821 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 19265133 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 1290098 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 1421425 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 8189940 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 83401 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 5265 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 2801985 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 5263 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 42538 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7005
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 21 2008 20:12:56
|
||||
M5 started Mon Jul 21 20:19:28 2008
|
||||
M5 compiled Aug 2 2008 17:07:15
|
||||
M5 started Sat Aug 2 17:08:52 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
|
||||
M5 commit date Tue Jul 15 14:38:51 2008 -0400
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing tests/run.py long/50.vortex/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -166,6 +166,7 @@ cmd=vortex lendian.raw
|
|||
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
|
|
@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 866615 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 218536 # Number of bytes of host memory used
|
||||
host_seconds 101.94 # Real time elapsed on the host
|
||||
host_tick_rate 1271060462 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1478736 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 210524 # Number of bytes of host memory used
|
||||
host_seconds 59.74 # Real time elapsed on the host
|
||||
host_tick_rate 2262580844 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_seconds 0.129569 # Number of seconds simulated
|
||||
sim_ticks 129569130000 # Number of ticks simulated
|
||||
sim_seconds 0.135169 # Number of seconds simulated
|
||||
sim_ticks 135168711000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 21389.665103 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18389.665103 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 37874.302641 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.302641 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 1299743000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 2301432000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1117448000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2119137000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 26999.752992 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.752992 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.752992 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.752992 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 4044374000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 8388371000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3594995000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 7938992000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 25380.735949 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 22380.735949 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 50768.923527 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 47768.923527 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 34679457 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 5344117000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 10689803000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 210558 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 4712443000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 10058129000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 210558 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 25380.735949 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 22380.735949 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 50768.923527 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 47768.923527 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 34679457 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 5344117000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 10689803000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 210558 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 4712443000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 10058129000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 210558 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 200247 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4080.797262 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4078.869222 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 750583000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 947580000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 147714 # number of writebacks
|
||||
system.cpu.dtb.accesses 34987415 # DTB accesses
|
||||
system.cpu.dtb.acv 0 # DTB access violations
|
||||
|
|
@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
|
|||
system.cpu.dtb.write_hits 14613377 # DTB write hits
|
||||
system.cpu.dtb.write_misses 7252 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 15489.023497 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 12489.023497 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 18810.691297 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 15810.691297 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1183919000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 1437814000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 954611000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 1208506000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 88438074 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 15489.023497 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 12489.023497 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 18810.691297 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 88361638 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1183919000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 1437814000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000864 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 954611000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 1208506000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 88438074 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 15489.023497 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 12489.023497 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 18810.691297 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 15810.691297 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 88361638 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1183919000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 1437814000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000864 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 76436 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 954611000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 1208506000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 74391 # number of replacements
|
||||
system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1876.637848 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1871.769418 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 88361638 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -160,31 +160,31 @@ system.cpu.itb.acv 0 # IT
|
|||
system.cpu.itb.hits 88438074 # ITB hits
|
||||
system.cpu.itb.misses 3934 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3302294000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 7466056000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1579358000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743120000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 137201 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 93905 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 995808000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 2251392000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.315566 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 43296 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 476256000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1731840000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.315566 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 43296 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22863.073210 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 142094000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51690.426388 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 321256000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 68365000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248600000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -198,29 +198,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 93905 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 4298102000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 9717448000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.665555 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 186874 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2055614000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 7474960000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.665555 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 186874 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 280779 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 93905 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 4298102000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 9717448000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.665555 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 186874 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2055614000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 7474960000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.665555 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 186874 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 147560 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 172765 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 18265.835561 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 18255.753819 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 120634 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 259138260 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 270337422 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 88340673 # Number of instructions executed
|
||||
system.cpu.num_refs 35321418 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7003
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7006
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -5,10 +5,10 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 21 2008 20:12:56
|
||||
M5 started Mon Jul 21 20:13:07 2008
|
||||
M5 compiled Aug 2 2008 17:07:15
|
||||
M5 started Sat Aug 2 17:10:35 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
|
||||
M5 commit date Tue Jul 15 14:38:51 2008 -0400
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing tests/run.py long/50.vortex/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -166,6 +166,7 @@ cmd=vortex bendian.raw
|
|||
cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
|
||||
gid=100
|
||||
|
|
@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 809753 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 216324 # Number of bytes of host memory used
|
||||
host_seconds 168.12 # Real time elapsed on the host
|
||||
host_tick_rate 1194295397 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1368614 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 211448 # Number of bytes of host memory used
|
||||
host_seconds 99.47 # Real time elapsed on the host
|
||||
host_tick_rate 2062044712 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 136139203 # Number of instructions simulated
|
||||
sim_seconds 0.200790 # Number of seconds simulated
|
||||
sim_ticks 200790381000 # Number of ticks simulated
|
||||
sim_seconds 0.205117 # Number of seconds simulated
|
||||
sim_ticks 205116920000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 21620.738917 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18620.738917 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 38620.848810 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35620.848810 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 983722000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 1757210000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 847225000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1620713000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_hits 15876 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_miss_latency 1080000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.002513 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 960000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.002513 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 26999.835474 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.835474 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.835474 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.835474 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 20754899 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 2953917000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 6126662000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.005244 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 109405 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2625702000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5798447000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 109405 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 25419.866498 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 22419.866498 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 50895.212519 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 57940701 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 3937639000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 7883872000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 154904 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3472927000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 7419160000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 154904 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 25419.866498 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 22419.866498 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 50895.212519 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 57940701 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 3937639000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 7883872000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 154904 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3472927000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 7419160000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002666 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 154904 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 146582 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4089.002644 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4087.433110 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 600016000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 821750000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 107271 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 136293812 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 14908.771067 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11908.771067 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 16936.029600 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 13936.029600 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 136106788 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 2788298000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 3167444000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.001372 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 2227226000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 2606372000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.001372 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 136293812 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 14908.771067 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 11908.771067 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 16936.029600 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 136106788 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 2788298000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 3167444000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.001372 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 2227226000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 2606372000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.001372 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 136293812 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 14908.771067 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 11908.771067 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 16936.029600 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 136106788 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 2788298000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 3167444000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.001372 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 187024 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 2227226000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 2606372000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.001372 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -148,37 +148,37 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 184976 # number of replacements
|
||||
system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 2006.709249 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 2004.068304 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 136106788 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 143009204000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.warmup_cycle 146097762000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2419117000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 5469308000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 105179 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1156969000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4207160000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 105179 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 232523 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 192777 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 914158000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 2066792000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.170934 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 39746 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 437206000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1589840000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.170934 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 39746 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 4266 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22902.953586 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 97704000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51780.590717 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 220896000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 4266 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 46926000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 170640000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 4266 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 107271 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -192,29 +192,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 337702 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 192777 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 3333275000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 7536100000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.429151 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 144925 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1594175000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 5797000000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.429151 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 144925 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 192777 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 3333275000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 7536100000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.429151 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 144925 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1594175000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 5797000000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.429151 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 144925 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -231,12 +231,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 120486 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 139196 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 19341.325901 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 19311.746813 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 199586 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 87413 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 401580762 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 410233840 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 136139203 # Number of instructions executed
|
||||
system.cpu.num_refs 58160249 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7007
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: ignoring syscall time(4026527848, 4026528248, ...)
|
||||
warn: ignoring syscall time(4026527400, 1375098, ...)
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 21 2008 20:33:06
|
||||
M5 started Mon Jul 21 20:36:59 2008
|
||||
M5 compiled Aug 2 2008 17:21:13
|
||||
M5 started Sat Aug 2 17:28:00 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
|
||||
M5 commit date Tue Jul 15 14:38:51 2008 -0400
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing tests/run.py long/50.vortex/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Exiting @ tick 200790381000 because target called exit()
|
||||
Exiting @ tick 205116920000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -368,6 +368,7 @@ cmd=bzip2 input.source 1
|
|||
cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
|
||||
gid=100
|
||||
|
|
@ -393,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 298925307 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 307254403 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 123 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 19461333 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 256954278 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 332748805 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 23332154 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 98561 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 329172 # Number of bytes of host memory used
|
||||
host_seconds 17613.94 # Real time elapsed on the host
|
||||
host_tick_rate 37548074 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 73213571 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 37308198 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 599919223 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 223513381 # Number of stores inserted to the mem dependence unit.
|
||||
global.BPredUnit.BTBHits 312845728 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 319575550 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 136 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 19647323 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 266741487 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 345502581 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 23750301 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 237180 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 201180 # Number of bytes of host memory used
|
||||
host_seconds 7319.53 # Real time elapsed on the host
|
||||
host_tick_rate 101414942 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 127392983 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 67515290 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 621608429 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 234046219 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1736043781 # Number of instructions simulated
|
||||
sim_seconds 0.661370 # Number of seconds simulated
|
||||
sim_ticks 661369625500 # Number of ticks simulated
|
||||
sim_seconds 0.742309 # Number of seconds simulated
|
||||
sim_ticks 742309410500 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 214632552 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 64339411 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 62782580 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 1246869641
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 1379215313
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 606206692 4861.83%
|
||||
1 260350579 2088.03%
|
||||
2 123843780 993.24%
|
||||
3 79587483 638.30%
|
||||
4 49145226 394.15%
|
||||
5 29422011 235.97%
|
||||
6 23247922 186.45%
|
||||
7 10726537 86.03%
|
||||
8 64339411 516.01%
|
||||
0 736540795 5340.29%
|
||||
1 260049510 1885.49%
|
||||
2 126970462 920.60%
|
||||
3 77723430 563.53%
|
||||
4 51327443 372.15%
|
||||
5 27759546 201.27%
|
||||
6 26179569 189.81%
|
||||
7 9881978 71.65%
|
||||
8 62782580 455.21%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
|
|
@ -43,80 +43,80 @@ system.cpu.commit.COM:loads 445666361 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 606571343 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 19460831 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 19646822 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 498311436 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 627314196 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.761927 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.761927 # CPI: Total CPI of All Threads
|
||||
system.cpu.cpi 0.855174 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.855174 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 9500 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 6500 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency
|
||||
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency
|
||||
system.cpu.dcache.LoadLockedReq_hits 2 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 9500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_latency 38500 # number of LoadLockedReq miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate 0.333333 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 6500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles
|
||||
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_accesses 514699566 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 6709.313547 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3665.501336 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 505997425 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 58385392500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.016907 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 8702141 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 1427526 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 26665111000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.014134 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 7274615 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_accesses 523259958 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 16887.800030 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11267.117004 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 512954318 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 174039587500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.019695 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 10305640 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 3030506 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 81969786000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.013903 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 7275134 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 10289.713687 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10117.659004 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 156501908 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 43490442133 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.026296 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 4226594 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 1977957 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 22750942389 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 33917.186217 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37153.824413 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 155297499 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 184204340094 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.033790 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 5431003 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 3182477 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 83541340193 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.013990 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 2248637 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs 2040.681665 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets 2667.920935 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 72.404790 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 71409 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 65111 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 145723037 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 173711000 # number of cycles access was blocked
|
||||
system.cpu.dcache.WriteReq_mshr_misses 2248526 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs 6337.465393 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets 31613.485382 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 73.053389 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 156253 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 65330 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 990247980 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 2065309000 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 675428068 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 7879.799117 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 5188.989369 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 662499333 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 101875834633 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.019142 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 12928735 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 3405483 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 49416053389 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.014100 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9523252 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 683988460 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 22764.952321 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 17378.941100 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 668251817 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 358243927594 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.023007 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 15736643 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 6212983 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 165511126193 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.013924 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9523660 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 675428068 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 7879.799117 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 5188.989369 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 683988460 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 22764.952321 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 17378.941100 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 662499333 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 101875834633 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.019142 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 12928735 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 3405483 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 49416053389 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.014100 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9523252 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 668251817 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 358243927594 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.023007 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 15736643 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 6212983 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 165511126193 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.013924 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9523660 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -128,104 +128,104 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 9155291 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 9159387 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 9155770 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 9159866 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4084.377148 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 663183492 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 6956358000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 2245548 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 25695554 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 564 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 51842469 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 2704061258 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 689853878 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 528999718 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 75857193 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 1673 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 2320492 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 762597100 # DTB accesses
|
||||
system.cpu.dcache.tagsinuse 4082.023671 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 669159252 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 7089291000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 2245448 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 98604485 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 553 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 54363606 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 2810650716 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 726334598 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 549143095 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 93084197 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 1641 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 5133136 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 768331628 # DTB accesses
|
||||
system.cpu.dtb.acv 0 # DTB access violations
|
||||
system.cpu.dtb.hits 747387018 # DTB hits
|
||||
system.cpu.dtb.misses 15210082 # DTB misses
|
||||
system.cpu.dtb.read_accesses 561654782 # DTB read accesses
|
||||
system.cpu.dtb.hits 752318827 # DTB hits
|
||||
system.cpu.dtb.misses 16012801 # DTB misses
|
||||
system.cpu.dtb.read_accesses 566617541 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 552717840 # DTB read hits
|
||||
system.cpu.dtb.read_misses 8936942 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 200942318 # DTB write accesses
|
||||
system.cpu.dtb.read_hits 557381515 # DTB read hits
|
||||
system.cpu.dtb.read_misses 9236026 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 201714087 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 194669178 # DTB write hits
|
||||
system.cpu.dtb.write_misses 6273140 # DTB write misses
|
||||
system.cpu.fetch.Branches 332748805 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 340572268 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 882406365 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 8482299 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 2756699547 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 26531665 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.251560 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 340572268 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 322257461 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.084084 # Number of inst fetches per cycle
|
||||
system.cpu.dtb.write_hits 194937312 # DTB write hits
|
||||
system.cpu.dtb.write_misses 6776775 # DTB write misses
|
||||
system.cpu.fetch.Branches 345502581 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 355180514 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 920206753 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 7941780 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 2863046416 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 28103164 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.232721 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 355180514 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 336596029 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.928472 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 1322726835
|
||||
system.cpu.fetch.rateDist.samples 1472299511
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 780892776 5903.66%
|
||||
1 46232823 349.53%
|
||||
2 32110220 242.76%
|
||||
3 49083369 371.08%
|
||||
4 120415668 910.36%
|
||||
5 67469038 510.08%
|
||||
6 46013556 347.87%
|
||||
7 40168101 303.68%
|
||||
8 140341284 1061.00%
|
||||
0 907273306 6162.29%
|
||||
1 47886355 325.25%
|
||||
2 34613457 235.10%
|
||||
3 52095475 353.84%
|
||||
4 125971052 855.61%
|
||||
5 69335096 470.93%
|
||||
6 50458684 342.72%
|
||||
7 40993758 278.43%
|
||||
8 143672328 975.84%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 340572268 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 9183.349374 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6758.046615 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 340571229 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 9541500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_accesses 355180514 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35446.920583 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35464.523282 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 355179280 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 43741500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 1039 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 138 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 6089000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_misses 1234 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 332 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 31989000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 901 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses 902 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 377992.485017 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 393768.603104 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 340572268 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 9183.349374 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6758.046615 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 340571229 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 9541500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_accesses 355180514 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35446.920583 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 355179280 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 43741500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 1039 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 138 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 6089000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_misses 1234 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 332 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 31989000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 901 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 902 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 340572268 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 9183.349374 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6758.046615 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 355180514 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35446.920583 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35464.523282 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 340571229 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 9541500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_hits 355179280 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 43741500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 1039 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 138 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 6089000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_misses 1234 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 332 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 31989000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 901 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 902 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -238,79 +238,79 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.sampled_refs 901 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 902 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 708.208043 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 340571229 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 711.425376 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 355179280 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 12417 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 272957078 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 123939642 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.684042 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 763895221 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 201165010 # Number of stores executed
|
||||
system.cpu.idleCycles 12319311 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 282186317 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 128796557 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.535065 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 769619313 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 201925300 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 1488939134 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 2188676291 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.814314 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 1531990742 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 2240290220 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.811831 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1212463676 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.654654 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 2210006196 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 21034553 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 2251453 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 599919223 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 23371349 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 223513381 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2521543989 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 562730211 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 40765112 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 2227547936 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 36991 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 1243717846 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.509000 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 2261678921 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 21342133 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 17373691 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 621608429 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 22154841 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 234046219 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 2621719070 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 567694013 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 36858072 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 2278986798 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 339653 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 5661 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 75857193 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 176880 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 40208 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 93084197 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 758573 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 196633 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 37920789 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 331554 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 361643 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 33889592 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 220185 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 439987 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 9 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 154252862 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 62608399 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 439987 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 706308 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 20328245 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.312461 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.312461 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 2268313048 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 3031505 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 6 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 175942068 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 73141237 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 3031505 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 703796 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 20638337 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.169353 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.169353 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 2315844870 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
No_OpClass 0 0.00% # Type of FU issued
|
||||
IntAlu 1489479679 65.66% # Type of FU issued
|
||||
IntMult 80 0.00% # Type of FU issued
|
||||
IntAlu 1532920234 66.19% # Type of FU issued
|
||||
IntMult 99 0.00% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 221 0.00% # Type of FU issued
|
||||
FloatCmp 17 0.00% # Type of FU issued
|
||||
FloatAdd 234 0.00% # Type of FU issued
|
||||
FloatCmp 20 0.00% # Type of FU issued
|
||||
FloatCvt 143 0.00% # Type of FU issued
|
||||
FloatMult 14 0.00% # Type of FU issued
|
||||
FloatMult 16 0.00% # Type of FU issued
|
||||
FloatDiv 24 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 574434192 25.32% # Type of FU issued
|
||||
MemWrite 204398678 9.01% # Type of FU issued
|
||||
MemRead 577889725 24.95% # Type of FU issued
|
||||
MemWrite 205034375 8.85% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 16429831 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.007243 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 14393569 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.006215 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
No_OpClass 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 2410991 14.67% # attempts to use FU when none available
|
||||
IntAlu 2738956 19.03% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 0 0.00% # attempts to use FU when none available
|
||||
|
|
@ -319,102 +319,102 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 10617024 64.62% # attempts to use FU when none available
|
||||
MemWrite 3401816 20.71% # attempts to use FU when none available
|
||||
MemRead 9224843 64.09% # attempts to use FU when none available
|
||||
MemWrite 2429770 16.88% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 1322726835
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 1472299511
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 474192746 3584.96%
|
||||
1 247291499 1869.56%
|
||||
2 221816340 1676.96%
|
||||
3 137127863 1036.71%
|
||||
4 113209815 855.88%
|
||||
5 74495950 563.20%
|
||||
6 43530199 329.09%
|
||||
7 8994308 68.00%
|
||||
8 2068115 15.64%
|
||||
0 577695747 3923.77%
|
||||
1 271543753 1844.35%
|
||||
2 242868164 1649.58%
|
||||
3 139713871 948.95%
|
||||
4 122021081 828.78%
|
||||
5 69652696 473.09%
|
||||
6 39670195 269.44%
|
||||
7 8017830 54.46%
|
||||
8 1116174 7.58%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 1.714860 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 2397604305 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 2268313048 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 42 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 649290621 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 732371 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 261741042 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 340572306 # ITB accesses
|
||||
system.cpu.iq.ISSUE:rate 1.559892 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 2492922470 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 2315844870 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 739697575 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 1501742 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 329349436 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 355180548 # ITB accesses
|
||||
system.cpu.itb.acv 0 # ITB acv
|
||||
system.cpu.itb.hits 340572268 # ITB hits
|
||||
system.cpu.itb.misses 38 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 1884772 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 5864.888697 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2864.888697 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 11053978000 # number of ReadExReq miss cycles
|
||||
system.cpu.itb.hits 355180514 # ITB hits
|
||||
system.cpu.itb.misses 34 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 1884731 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34610.251241 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31460.593787 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 65231013432 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1884772 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 5399662000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_misses 1884731 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 59294756388 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1884772 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 7275516 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 5386.307802 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2386.307802 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5387207 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 10171013500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.259543 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1888309 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 4506086500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259543 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1888309 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 363870 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5746.245912 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2753.549345 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 2090886500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1884731 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 7276037 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34304.499446 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31138.330859 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5387449 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 64787066000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.259563 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1888588 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 58807478000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259563 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1888588 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 363810 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34327.097532 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31261.459886 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 12488541353 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 363870 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1001934000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 363810 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 11373231721 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 363870 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 2245548 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 2245548 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 363810 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 2245448 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 2245448 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs 11899.405570 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 2.418060 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_refs 2.417948 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 39818 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 473810531 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 9160288 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 5625.373932 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2625.373932 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 5387207 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 21224991500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.411895 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 3773081 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 9160768 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34457.219077 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 5387449 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 130018079432 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.411900 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 3773319 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 9905748500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.411895 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 3773081 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 118102234388 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.411900 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 3773319 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 9160288 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 5625.373932 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2625.373932 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 9160768 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34457.219077 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31299.297618 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 5387207 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 21224991500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.411895 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 3773081 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 5387449 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 130018079432 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.411900 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 3773319 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 9905748500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.411895 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 3773081 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 118102234388 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.411900 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 3773319 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -426,32 +426,32 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 2759208 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2783806 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 2759426 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2784020 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 25817.282629 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6731411 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 140102368000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1195679 # number of writebacks
|
||||
system.cpu.numCycles 1322739252 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 10423216 # Number of cycles rename is blocking
|
||||
system.cpu.l2cache.tagsinuse 25902.034995 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6731616 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 154290039500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1195718 # number of writebacks
|
||||
system.cpu.numCycles 1484618822 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 68342800 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 3385420 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 705442707 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 9460872 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 157269 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 3423780434 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 2645446907 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 1985349974 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 515854810 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 75857193 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 15148388 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 609147011 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 521 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:IQFullEvents 5307310 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 744648223 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 20682073 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:ROBFullEvents 1073015 # Number of times rename has blocked due to ROB full
|
||||
system.cpu.rename.RENAME:RenameLookups 3556218268 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 2749142878 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 2059304818 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 535957515 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 93084197 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 30265718 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 683101855 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 1058 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 46 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 33326787 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:skidInsts 60936720 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 44 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 4373 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.timesIdled 457423 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7007
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 21 2008 20:12:56
|
||||
M5 started Mon Jul 21 20:17:14 2008
|
||||
M5 compiled Aug 2 2008 17:07:15
|
||||
M5 started Sat Aug 2 17:08:50 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
|
||||
M5 commit date Tue Jul 15 14:38:51 2008 -0400
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing tests/run.py long/60.bzip2/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -166,6 +166,7 @@ cmd=bzip2 input.source 1
|
|||
cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
|
||||
gid=100
|
||||
|
|
@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1098189 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 373972 # Number of bytes of host memory used
|
||||
host_seconds 1657.07 # Real time elapsed on the host
|
||||
host_tick_rate 1574114309 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 2488083 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 200292 # Number of bytes of host memory used
|
||||
host_seconds 731.40 # Real time elapsed on the host
|
||||
host_tick_rate 3729826518 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_seconds 2.608424 # Number of seconds simulated
|
||||
sim_ticks 2608424230000 # Number of ticks simulated
|
||||
sim_seconds 2.727991 # Number of seconds simulated
|
||||
sim_ticks 2727990505000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 17373.778213 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 14373.778213 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 24899.898843 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21899.898843 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 125480619000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 179837378000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 103813377000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 158170136000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 26999.842958 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23999.842958 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 55999.842958 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.842958 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 158480700 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 60690301000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 125876559000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.013985 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 2247802 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 53946895000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 119133153000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.013985 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 2247802 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 19658.571674 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 16658.571674 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 32281.622404 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 595853949 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 186170920000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 305713937000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.015645 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 9470216 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 157760272000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 277303289000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.015645 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 9470216 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 19658.571674 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 16658.571674 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 32281.622404 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 595853949 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 186170920000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 305713937000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.015645 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 9470216 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 157760272000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 277303289000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.015645 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 9470216 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,9 +76,9 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 9107638 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4079.381693 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 4079.892573 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 40744129000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.warmup_cycle 40991470000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 2244708 # number of writebacks
|
||||
system.cpu.dtb.accesses 611922547 # DTB accesses
|
||||
system.cpu.dtb.acv 0 # DTB access violations
|
||||
|
|
@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
|
|||
system.cpu.dtb.write_hits 160728502 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1701304 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 21654000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 44912000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 19248000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 42506000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 21654000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 44912000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 19248000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 42506000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 1826377708 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 21654000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 44912000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 802 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 19248000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 42506000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 611.562745 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 611.737435 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -160,31 +160,31 @@ system.cpu.itb.acv 0 # IT
|
|||
system.cpu.itb.hits 1826378510 # ITB hits
|
||||
system.cpu.itb.misses 18 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 43454360000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 98244640000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1889320 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 20782520000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 75572800000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1889320 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5348043 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 43128979000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 97508996000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.259604 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1875173 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 20626903000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 75006920000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259604 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1875173 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 358482 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 22977.351722 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 8236967000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 51948.795198 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 18622708000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 358482 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3943302000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14339280000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 358482 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -198,29 +198,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 5348043 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 86583339000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 195753636000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.413111 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 3764493 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 41409423000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 150579720000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.413111 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 3764493 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 5348043 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 86583339000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 195753636000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.413111 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 3764493 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 41409423000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 150579720000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.413111 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 3764493 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 2751986 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 2776586 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 25389.772813 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 25365.544087 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 6685498 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 574940849000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.warmup_cycle 605789077000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 1194738 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 5216848460 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 5455981010 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 1819780127 # Number of instructions executed
|
||||
system.cpu.num_refs 613169725 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7003
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7006
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 21 2008 20:12:56
|
||||
M5 started Mon Jul 21 20:14:59 2008
|
||||
M5 compiled Aug 2 2008 17:07:15
|
||||
M5 started Sat Aug 2 17:11:35 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
|
||||
M5 commit date Tue Jul 15 14:38:51 2008 -0400
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing tests/run.py long/60.bzip2/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
spec_init
|
||||
|
|
|
|||
|
|
@ -368,6 +368,7 @@ cmd=twolf smred
|
|||
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
|
||||
gid=100
|
||||
|
|
@ -393,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 13021521 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 16952662 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 1212 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 1950052 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 14577615 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 19451761 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 1721600 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 82033 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 156240 # Number of bytes of host memory used
|
||||
host_seconds 1026.17 # Real time elapsed on the host
|
||||
host_tick_rate 39719192 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 17804625 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 5077040 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 33854360 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 10604217 # Number of stores inserted to the mem dependence unit.
|
||||
global.BPredUnit.BTBHits 13008791 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 16964874 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 1204 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 1946248 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 14605230 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 19468548 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 1719783 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 157592 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 206456 # Number of bytes of host memory used
|
||||
host_seconds 534.16 # Real time elapsed on the host
|
||||
host_tick_rate 76416157 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 17216078 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 5041116 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 33976826 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 10628051 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 84179709 # Number of instructions simulated
|
||||
sim_seconds 0.040758 # Number of seconds simulated
|
||||
sim_ticks 40758469000 # Number of ticks simulated
|
||||
sim_seconds 0.040819 # Number of seconds simulated
|
||||
sim_ticks 40818658500 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 10240685 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 2850471 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 2855803 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 73485570
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 73457195
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 36241200 4931.74%
|
||||
1 18077968 2460.07%
|
||||
2 7549008 1027.28%
|
||||
3 4015107 546.38%
|
||||
4 2030060 276.25%
|
||||
5 1302937 177.31%
|
||||
6 688676 93.72%
|
||||
7 730143 99.36%
|
||||
8 2850471 387.90%
|
||||
0 36278942 4938.79%
|
||||
1 18156305 2471.69%
|
||||
2 7455514 1014.95%
|
||||
3 3880418 528.26%
|
||||
4 2046448 278.59%
|
||||
5 1301140 177.13%
|
||||
6 721823 98.26%
|
||||
7 760802 103.57%
|
||||
8 2855803 388.77%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
|
|
@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 20034413 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 26537108 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 1937588 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 1933797 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 55772540 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 56152215 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
|
||||
system.cpu.cpi 0.968368 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.968368 # CPI: Total CPI of All Threads
|
||||
system.cpu.cpi 0.969798 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 0.969798 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.LoadLockedReq_accesses 7 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_hits 7 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.ReadReq_accesses 23271115 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 9301.109350 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6675.196850 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 23270484 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 5869000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 631 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3391000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses 23402422 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 30625.144175 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32084.980237 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 23401555 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 26552000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000037 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 867 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 361 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 16235000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 508 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 7925.428784 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7197.950378 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 6493057 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 63768000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.001238 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 8046 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 6192 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 13345000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 35738.919918 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36175.579146 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 6492799 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 296775991 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.001277 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 8304 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 6453 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 66960997 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1854 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1851 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs 2649.700000 # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 13269.627731 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.avg_refs 13345.816518 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 10 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 26497 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 29772218 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 8025.469632 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 7085.520745 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 29763541 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 69637000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000291 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 8677 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 6315 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 16736000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_accesses 29903525 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 35255.478247 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 35297.410692 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 29894354 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 323327991 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000307 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 9171 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 6814 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 83195997 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2362 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 2357 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 29772218 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 8025.469632 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 7085.520745 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 29903525 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 35255.478247 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 35297.410692 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 29763541 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 69637000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000291 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 8677 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 6315 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 16736000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_hits 29894354 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 323327991 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000307 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 9171 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 6814 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 83195997 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2362 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 2357 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -121,103 +121,103 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 159 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 1461.984287 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 29763775 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 1458.381237 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 29894629 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 105 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 3862301 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 12627 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 3048985 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 162336287 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 39537926 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 29896024 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 8028470 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 45209 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 189320 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 31783723 # DTB accesses
|
||||
system.cpu.decode.DECODE:BlockedCycles 3781084 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 12597 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 3039308 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 162679523 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 39569073 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 29917869 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 8071146 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 45156 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 189170 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 31911121 # DTB accesses
|
||||
system.cpu.dtb.acv 0 # DTB access violations
|
||||
system.cpu.dtb.hits 31332689 # DTB hits
|
||||
system.cpu.dtb.misses 451034 # DTB misses
|
||||
system.cpu.dtb.read_accesses 24575603 # DTB read accesses
|
||||
system.cpu.dtb.hits 31454022 # DTB hits
|
||||
system.cpu.dtb.misses 457099 # DTB misses
|
||||
system.cpu.dtb.read_accesses 24718123 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 24125563 # DTB read hits
|
||||
system.cpu.dtb.read_misses 450040 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 7208120 # DTB write accesses
|
||||
system.cpu.dtb.read_hits 24262026 # DTB read hits
|
||||
system.cpu.dtb.read_misses 456097 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 7192998 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 7207126 # DTB write hits
|
||||
system.cpu.dtb.write_misses 994 # DTB write misses
|
||||
system.cpu.fetch.Branches 19451761 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 19219800 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 50154718 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 536931 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 167137455 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 2059472 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.238622 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 19219800 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 14743121 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.050340 # Number of inst fetches per cycle
|
||||
system.cpu.dtb.write_hits 7191996 # DTB write hits
|
||||
system.cpu.dtb.write_misses 1002 # DTB write misses
|
||||
system.cpu.fetch.Branches 19468548 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 19230003 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 50198038 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 519723 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 167554902 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 2079597 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.238476 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 19230003 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 14728574 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 2.052430 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 81514041
|
||||
system.cpu.fetch.rateDist.samples 81528342
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 50579197 6204.97%
|
||||
1 3119637 382.71%
|
||||
2 2009848 246.56%
|
||||
3 3519871 431.81%
|
||||
4 4617609 566.48%
|
||||
5 1511564 185.44%
|
||||
6 2006119 246.11%
|
||||
7 1828029 224.26%
|
||||
8 12322167 1511.66%
|
||||
0 50560377 6201.57%
|
||||
1 3114212 381.98%
|
||||
2 2012618 246.86%
|
||||
3 3505366 429.96%
|
||||
4 4590613 563.07%
|
||||
5 1506961 184.84%
|
||||
6 2028359 248.79%
|
||||
7 1846743 226.52%
|
||||
8 12363093 1516.42%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 19219800 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 6448.716735 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3507.077806 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 19209241 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 68092000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000549 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 10559 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 457 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 35428500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000526 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 10102 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 19230003 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 15782.750498 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 11914.180589 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 19218965 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 174210000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000574 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 11038 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 982 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 119809000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000523 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 10056 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 1901.528509 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 1911.193815 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 19219800 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 6448.716735 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 3507.077806 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 19209241 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 68092000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000549 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 10559 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 457 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 35428500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000526 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 10102 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 19230003 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 15782.750498 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 19218965 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 174210000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000574 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 11038 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 982 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 119809000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000523 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 10056 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 19219800 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 6448.716735 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 3507.077806 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 19230003 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 15782.750498 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 11914.180589 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 19209241 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 68092000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000549 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 10559 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 457 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 35428500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000526 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 10102 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 19218965 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 174210000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000574 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 11038 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 982 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 119809000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000523 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 10056 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -229,184 +229,184 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 8191 # number of replacements
|
||||
system.cpu.icache.sampled_refs 10102 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 8143 # number of replacements
|
||||
system.cpu.icache.sampled_refs 10056 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1547.575549 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 19209241 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1543.991602 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 19218965 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 2898 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 12781978 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 12589139 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.246896 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 31834864 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 7209747 # Number of stores executed
|
||||
system.cpu.idleCycles 108976 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 12812003 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 12599027 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 1.247521 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 31962516 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 7194632 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 91092089 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 99774116 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.721851 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 90937299 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 99943821 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.723990 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 65754876 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.223968 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 100649675 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 2112266 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 284242 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 33854360 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 429 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 1723654 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 10604217 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 147674740 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 24625117 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 2113526 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 101643128 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 120911 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 65837671 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 1.224242 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 100859242 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 2125730 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 254811 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 33976826 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 426 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 1734651 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 10628051 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 148053720 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 24767884 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 2184370 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 101844271 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 121216 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 5 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 8028470 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 165624 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewLSQFullEvents 222 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 8071146 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 160195 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 844640 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 2772 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 849805 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 2830 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 223466 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 9801 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 13819947 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 4101522 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 223466 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 201477 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 1910789 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.032665 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.032665 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 103756654 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 248254 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 9784 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 13942413 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 4125356 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 248254 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 218646 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 1907084 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 1.031143 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 1.031143 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 104028641 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
No_OpClass 7 0.00% # Type of FU issued
|
||||
IntAlu 64328227 62.00% # Type of FU issued
|
||||
IntMult 474807 0.46% # Type of FU issued
|
||||
IntAlu 64430040 61.93% # Type of FU issued
|
||||
IntMult 475055 0.46% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 2783435 2.68% # Type of FU issued
|
||||
FloatCmp 115619 0.11% # Type of FU issued
|
||||
FloatCvt 2381566 2.30% # Type of FU issued
|
||||
FloatMult 305730 0.29% # Type of FU issued
|
||||
FloatDiv 755065 0.73% # Type of FU issued
|
||||
FloatSqrt 322 0.00% # Type of FU issued
|
||||
MemRead 25279956 24.36% # Type of FU issued
|
||||
MemWrite 7331920 7.07% # Type of FU issued
|
||||
FloatAdd 2782164 2.67% # Type of FU issued
|
||||
FloatCmp 115645 0.11% # Type of FU issued
|
||||
FloatCvt 2377276 2.29% # Type of FU issued
|
||||
FloatMult 305748 0.29% # Type of FU issued
|
||||
FloatDiv 755245 0.73% # Type of FU issued
|
||||
FloatSqrt 323 0.00% # Type of FU issued
|
||||
MemRead 25462424 24.48% # Type of FU issued
|
||||
MemWrite 7324714 7.04% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 1948888 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.018783 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 1933128 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.018583 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
No_OpClass 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 297234 15.25% # attempts to use FU when none available
|
||||
IntAlu 274346 14.19% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 492 0.03% # attempts to use FU when none available
|
||||
FloatAdd 31 0.00% # attempts to use FU when none available
|
||||
FloatCmp 0 0.00% # attempts to use FU when none available
|
||||
FloatCvt 3359 0.17% # attempts to use FU when none available
|
||||
FloatMult 1274 0.07% # attempts to use FU when none available
|
||||
FloatDiv 828421 42.51% # attempts to use FU when none available
|
||||
FloatCvt 6547 0.34% # attempts to use FU when none available
|
||||
FloatMult 2333 0.12% # attempts to use FU when none available
|
||||
FloatDiv 832912 43.09% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 745957 38.28% # attempts to use FU when none available
|
||||
MemWrite 72151 3.70% # attempts to use FU when none available
|
||||
MemRead 743147 38.44% # attempts to use FU when none available
|
||||
MemWrite 73812 3.82% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 81514041
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 81528342
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 35401194 4342.96%
|
||||
1 18638593 2286.55%
|
||||
2 11850080 1453.75%
|
||||
3 6738129 826.62%
|
||||
4 5072118 622.24%
|
||||
5 2314380 283.92%
|
||||
6 1219789 149.64%
|
||||
7 213656 26.21%
|
||||
8 66102 8.11%
|
||||
0 35305774 4330.49%
|
||||
1 18904883 2318.81%
|
||||
2 11574998 1419.75%
|
||||
3 6762756 829.50%
|
||||
4 5075415 622.53%
|
||||
5 2394533 293.71%
|
||||
6 1208963 148.29%
|
||||
7 250769 30.76%
|
||||
8 50251 6.16%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 1.272823 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 135085172 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 103756654 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 429 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 50298713 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 225846 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 47102449 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 19219874 # ITB accesses
|
||||
system.cpu.iq.ISSUE:rate 1.274278 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 135454267 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 104028641 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 426 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 50669408 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 244059 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 47385393 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 19230073 # ITB accesses
|
||||
system.cpu.itb.acv 0 # ITB acv
|
||||
system.cpu.itb.hits 19219800 # ITB hits
|
||||
system.cpu.itb.misses 74 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 1736 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 5751.440092 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2751.440092 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 9984500 # number of ReadExReq miss cycles
|
||||
system.cpu.itb.hits 19230003 # ITB hits
|
||||
system.cpu.itb.misses 70 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 1735 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.302594 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31521.902017 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 60179000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1736 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 4776500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_misses 1735 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 54690500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1736 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 10609 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 5363.488784 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2363.488784 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 7221 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 18171500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.319351 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 3388 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 8007500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319351 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 3388 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 122 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5704.918033 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2704.918033 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 696000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1735 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 10561 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34278.518519 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31080.296296 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 7186 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 115690000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.319572 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 3375 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 104896000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319572 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 3375 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34390.243902 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31260.162602 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 4230000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 122 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 330000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3845000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 122 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs 1500 # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 2.154260 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.avg_refs 2.152807 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 2 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 3000 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 12345 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 5494.925839 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2494.925839 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 7221 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 28156000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.415067 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 5124 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 12296 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34416.634051 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.234834 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 7186 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 175869000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.415582 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 5110 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 12784000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.415067 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 5124 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 159586500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.415582 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 5110 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 12345 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 5494.925839 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2494.925839 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 12296 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34416.634051 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.234834 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 7221 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 28156000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.415067 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 5124 # number of overall misses
|
||||
system.cpu.l2cache.overall_hits 7186 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 175869000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.415582 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 5110 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 12784000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.415067 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 5124 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 159586500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.415582 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 5110 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -419,30 +419,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 3345 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 3331 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 2257.557113 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 7206 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tagsinuse 2244.752447 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 7171 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 81516939 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 1780351 # Number of cycles rename is blocking
|
||||
system.cpu.numCycles 81637318 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 1761024 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IQFullEvents 1047628 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 40793393 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 942240 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 202632347 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 157116893 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 115707927 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 28822360 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 8028470 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 2084695 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 47280566 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 4772 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 463 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 4626500 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 452 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 687 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 964182 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 40833182 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 973065 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 202958583 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 157334532 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 115929564 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 28833296 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 8071146 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 2024389 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 47502203 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 5305 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 457 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 4572167 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 446 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 2428 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 21 2008 20:12:56
|
||||
M5 started Mon Jul 21 20:14:27 2008
|
||||
M5 compiled Aug 2 2008 17:07:15
|
||||
M5 started Sat Aug 2 17:15:05 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
|
||||
M5 commit date Tue Jul 15 14:38:51 2008 -0400
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing tests/run.py long/70.twolf/alpha/tru64/o3-timing
|
||||
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav
|
||||
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
|
||||
|
|
|
|||
|
|
@ -166,6 +166,7 @@ cmd=twolf smred
|
|||
cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
|
||||
gid=100
|
||||
|
|
@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1053450 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 201692 # Number of bytes of host memory used
|
||||
host_seconds 87.24 # Real time elapsed on the host
|
||||
host_tick_rate 1359521857 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1888440 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 205224 # Number of bytes of host memory used
|
||||
host_seconds 48.67 # Real time elapsed on the host
|
||||
host_tick_rate 2440025498 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_seconds 0.118605 # Number of seconds simulated
|
||||
sim_ticks 118605062000 # Number of ticks simulated
|
||||
sim_seconds 0.118747 # Number of seconds simulated
|
||||
sim_ticks 118747191000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 25546.413502 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22546.413502 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 51303.797468 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48303.797468 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 19995724 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 12109000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 24318000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 474 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 10687000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 22896000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 474 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 50193000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 104104000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 44616000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 98527000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 26704.672096 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23704.672096 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 55045.863695 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 52045.863695 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 26494968 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 62302000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 128422000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 2333 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 55303000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 121423000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 2333 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 26704.672096 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23704.672096 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 55045.863695 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 52045.863695 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 26494968 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 62302000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 128422000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 2333 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 55303000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 121423000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 2333 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 157 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 2222 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 1441.428133 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 1441.023190 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 26495079 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 104 # number of writebacks
|
||||
|
|
@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
|
|||
system.cpu.dtb.write_hits 6501103 # DTB write hits
|
||||
system.cpu.dtb.write_misses 23 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 18003.877791 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 15003.877791 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 153213000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 229222000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 127683000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 18003.877791 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 15003.877791 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 153213000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 127683000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 203692000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 18003.877791 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 15003.877791 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 91894580 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 153213000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 8510 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 127683000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 6681 # number of replacements
|
||||
system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1418.444669 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1418.026644 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -160,31 +160,31 @@ system.cpu.itb.acv 0 # IT
|
|||
system.cpu.itb.hits 91903090 # ITB hits
|
||||
system.cpu.itb.misses 47 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 40204000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 90896000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 19228000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 69920000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 8984 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 69966000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 158184000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.338602 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 3042 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 33462000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 121680000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338602 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 3042 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 2553000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 5772000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1221000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4440000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -198,29 +198,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 10732 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 5942 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 110170000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 249080000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.446329 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 4790 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 52690000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 191600000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.446329 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 4790 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 10732 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 5942 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 110170000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 249080000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.446329 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 4790 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 52690000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 191600000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.446329 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 4790 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 3009 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 2021.668860 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 2021.060296 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 5928 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 237210124 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 237494382 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 91903056 # Number of instructions executed
|
||||
system.cpu.num_refs 26537141 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7003
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7004
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 21 2008 20:12:56
|
||||
M5 started Mon Jul 21 20:15:31 2008
|
||||
M5 compiled Aug 2 2008 17:07:15
|
||||
M5 started Sat Aug 2 17:07:25 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
|
||||
M5 commit date Tue Jul 15 14:38:51 2008 -0400
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing tests/run.py long/70.twolf/alpha/tru64/simple-timing
|
||||
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sav
|
||||
Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
|
||||
|
|
|
|||
|
|
@ -192,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,41 +1,41 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1517830 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 218636 # Number of bytes of host memory used
|
||||
host_seconds 127.45 # Real time elapsed on the host
|
||||
host_tick_rate 2121861871 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1409829 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 207084 # Number of bytes of host memory used
|
||||
host_seconds 137.21 # Real time elapsed on the host
|
||||
host_tick_rate 1971980655 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 193444769 # Number of instructions simulated
|
||||
sim_seconds 0.270428 # Number of seconds simulated
|
||||
sim_ticks 270428013000 # Number of ticks simulated
|
||||
sim_seconds 0.270579 # Number of seconds simulated
|
||||
sim_ticks 270578958000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 57734571 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 13446000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 27888000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 498 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 11952000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 26394000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 27000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 24000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
|
||||
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
|
||||
system.cpu.dcache.SwapReq_hits 22404 # number of SwapReq hits
|
||||
system.cpu.dcache.SwapReq_miss_latency 54000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_latency 112000 # number of SwapReq miss cycles
|
||||
system.cpu.dcache.SwapReq_miss_rate 0.000089 # miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_misses 2 # number of SwapReq misses
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 48000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_latency 106000 # number of SwapReq MSHR miss cycles
|
||||
system.cpu.dcache.SwapReq_mshr_miss_rate 0.000089 # mshr miss rate for SwapReq accesses
|
||||
system.cpu.dcache.SwapReq_mshr_misses 2 # number of SwapReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 18975331 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 29916000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 62048000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000058 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 1108 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 26592000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 58724000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000058 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 1108 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -47,29 +47,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 76709902 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 43362000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 89936000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1606 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 38544000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 85118000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1606 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 76709902 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 43362000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 89936000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.000021 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1606 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 38544000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 85118000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1606 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -86,18 +86,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 26 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1583 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 1235.387438 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 1235.200907 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 76732331 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 23 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 193445787 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 17805.419922 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 14805.419922 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 193433499 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 218793000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 323106000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000064 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 12288 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 181929000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 286242000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -109,29 +109,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 193445787 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 17805.419922 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 14805.419922 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 26294.433594 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 193433499 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 218793000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 323106000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000064 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 12288 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 181929000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 286242000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 12288 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 193445787 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 17805.419922 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 14805.419922 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 193433499 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 218793000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 323106000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 12288 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 181929000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 286242000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 12288 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -148,37 +148,37 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 10362 # number of replacements
|
||||
system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1591.780933 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1591.567399 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 193433499 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 1085 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 24955000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 56420000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 1085 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 11935000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 43400000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 1085 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 12786 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 8691 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 94185000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 212940000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.320272 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 4095 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 45045000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 163800000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320272 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 4095 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 25 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 575000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 1300000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 25 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 275000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1000000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 23 # number of Writeback accesses(hits+misses)
|
||||
|
|
@ -192,29 +192,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 13871 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 8691 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 119140000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 269360000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.373441 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 5180 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 56980000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 207200000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.373441 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 5180 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 13871 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 8691 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 119140000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 269360000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.373441 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 5180 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 56980000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 207200000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.373441 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 5180 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -231,12 +231,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 4086 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 2657.731325 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 2657.336317 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 540856026 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 541157916 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 193444769 # Number of instructions executed
|
||||
system.cpu.num_refs 76733959 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 401 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7005
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7002
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 23 2008 16:00:51
|
||||
M5 started Wed Jul 23 16:02:07 2008
|
||||
M5 executing on blue
|
||||
M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf
|
||||
M5 commit date Wed Jul 23 15:35:08 2008 -0700
|
||||
M5 compiled Aug 2 2008 17:21:13
|
||||
M5 started Sat Aug 2 17:29:26 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing tests/run.py long/70.twolf/sparc/linux/simple-timing
|
||||
Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav
|
||||
Couldn't unlink build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2
|
||||
|
|
@ -27,4 +27,4 @@ Authors: Carl Sechen, Bill Swartz
|
|||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124 Exiting @ tick 270428013000 because target called exit()
|
||||
122 123 124 Exiting @ tick 270578958000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -394,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 665 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 1852 # Number of BTB lookups
|
||||
global.BPredUnit.BTBHits 649 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 1748 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 424 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 1300 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 2168 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 288 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 54768 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 209744 # Number of bytes of host memory used
|
||||
host_seconds 0.12 # Real time elapsed on the host
|
||||
host_tick_rate 47820234 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 35 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 112 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 2210 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 1280 # Number of stores inserted to the mem dependence unit.
|
||||
global.BPredUnit.condIncorrect 420 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 1246 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 2108 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 301 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 87257 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 198272 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_tick_rate 171219532 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 36 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 28 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 2214 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 1262 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 6297 # Number of instructions simulated
|
||||
sim_seconds 0.000006 # Number of seconds simulated
|
||||
sim_ticks 5506500 # Number of ticks simulated
|
||||
sim_seconds 0.000012 # Number of seconds simulated
|
||||
sim_ticks 12391500 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 1012 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 113 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 120 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 9764
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 12114
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 7128 7300.29%
|
||||
1 1385 1418.48%
|
||||
2 452 462.93%
|
||||
3 225 230.44%
|
||||
4 157 160.79%
|
||||
5 102 104.47%
|
||||
6 106 108.56%
|
||||
7 96 98.32%
|
||||
8 113 115.73%
|
||||
0 9249 7634.97%
|
||||
1 1607 1326.56%
|
||||
2 479 395.41%
|
||||
3 271 223.71%
|
||||
4 137 113.09%
|
||||
5 121 99.88%
|
||||
6 87 71.82%
|
||||
7 43 35.50%
|
||||
8 120 99.06%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
|
|
@ -43,70 +43,70 @@ system.cpu.commit.COM:loads 1168 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 2030 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 352 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 350 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 6314 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 4192 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 4365 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 6297 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 6297 # Number of Instructions Simulated
|
||||
system.cpu.cpi 1.749087 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 1.749087 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 1758 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 10996.240602 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8551.020408 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1625 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 1462500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.075654 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 35 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 838000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.055745 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses
|
||||
system.cpu.cpi 3.935842 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 3.935842 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 1738 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 34857.142857 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36237.373737 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1577 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 5612000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.092635 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 161 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 62 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3587500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.056962 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 99 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 862 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 8662.162162 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7459.770115 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 492 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 3205000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.429234 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 370 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 649000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 35059.055118 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35660.919540 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 481 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 13357500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.441995 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 381 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 294 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3102500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.100928 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 12.605882 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 12.156977 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 2620 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 9279.324056 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 8037.837838 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 2117 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 4667500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.191985 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 503 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 318 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 1487000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.070611 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_accesses 2600 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 34999.077491 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 35967.741935 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 2058 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 18969500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.208462 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 542 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 6690000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.071538 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 2620 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 9279.324056 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 8037.837838 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 2600 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 34999.077491 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 35967.741935 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 2117 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 4667500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.191985 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 503 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 318 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 1487000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.070611 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 185 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 2058 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 18969500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.208462 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 542 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 356 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 6690000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.071538 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 186 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -119,103 +119,103 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 170 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 172 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 109.392910 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2143 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 109.051613 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 2091 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 463 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 170 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 12212 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 7007 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 2262 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 791 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 224 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 33 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 2901 # DTB accesses
|
||||
system.cpu.decode.DECODE:BlockedCycles 1043 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 71 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 168 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 11945 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 8815 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 2203 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 855 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 208 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 54 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 2892 # DTB accesses
|
||||
system.cpu.dtb.acv 0 # DTB access violations
|
||||
system.cpu.dtb.hits 2837 # DTB hits
|
||||
system.cpu.dtb.misses 64 # DTB misses
|
||||
system.cpu.dtb.read_accesses 1842 # DTB read accesses
|
||||
system.cpu.dtb.hits 2831 # DTB hits
|
||||
system.cpu.dtb.misses 61 # DTB misses
|
||||
system.cpu.dtb.read_accesses 1821 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 1799 # DTB read hits
|
||||
system.cpu.dtb.read_misses 43 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 1059 # DTB write accesses
|
||||
system.cpu.dtb.read_hits 1785 # DTB read hits
|
||||
system.cpu.dtb.read_misses 36 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 1071 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 1038 # DTB write hits
|
||||
system.cpu.dtb.write_misses 21 # DTB write misses
|
||||
system.cpu.fetch.Branches 2168 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1670 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 4064 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 235 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 13177 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 485 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.196840 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1670 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 953 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.196386 # Number of inst fetches per cycle
|
||||
system.cpu.dtb.write_hits 1046 # DTB write hits
|
||||
system.cpu.dtb.write_misses 25 # DTB write misses
|
||||
system.cpu.fetch.Branches 2108 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 1704 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 4044 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 12761 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 482 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.085055 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 1704 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 950 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.514889 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 10556
|
||||
system.cpu.fetch.rateDist.samples 12970
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 8192 7760.52%
|
||||
1 236 223.57%
|
||||
2 214 202.73%
|
||||
3 172 162.94%
|
||||
4 242 229.25%
|
||||
5 149 141.15%
|
||||
6 203 192.31%
|
||||
7 118 111.78%
|
||||
8 1030 975.75%
|
||||
0 10663 8221.28%
|
||||
1 241 185.81%
|
||||
2 214 165.00%
|
||||
3 169 130.30%
|
||||
4 208 160.37%
|
||||
5 163 125.67%
|
||||
6 215 165.77%
|
||||
7 128 98.69%
|
||||
8 969 747.11%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 1670 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 9198.550725 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6610.932476 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1325 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 3173500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.206587 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 345 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 34 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 2056000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.186228 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 311 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 1704 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35319.248826 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35254.870130 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 1278 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 15046000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.250000 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 426 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 118 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 10858500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.180751 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 4.260450 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 4.149351 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 1670 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 9198.550725 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6610.932476 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1325 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 3173500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.206587 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 345 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 34 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 2056000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.186228 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 311 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 1704 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35319.248826 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35254.870130 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 1278 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 15046000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.250000 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 426 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 118 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 10858500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.180751 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 308 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 1670 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 9198.550725 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6610.932476 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 1704 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35319.248826 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35254.870130 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 1325 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 3173500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.206587 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 345 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 34 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 2056000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.186228 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 311 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 1278 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 15046000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.250000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 426 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 118 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 10858500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.180751 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 308 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -228,61 +228,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 311 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 308 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 166.219676 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1325 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 160.409405 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 1278 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 458 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 1365 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 69 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.792628 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 2907 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 1061 # Number of stores executed
|
||||
system.cpu.idleCycles 11814 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 1375 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 76 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.355148 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 2900 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 1073 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 5886 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 8407 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.745158 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 5878 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 8512 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.747873 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 4386 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.763301 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 8526 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 417 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 4 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 2210 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 24 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 183 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 1280 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 10601 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 1846 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 353 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 8730 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 4396 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.343447 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 8611 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 406 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 66 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 2214 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 23 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 181 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 1262 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 10713 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 1827 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 299 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 8802 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 791 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewSquashCycles 855 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 40 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 67 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 1042 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 418 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 67 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.571727 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.571727 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 9083 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 1046 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 400 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 116 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.254075 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.254075 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 9101 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
No_OpClass 2 0.02% # Type of FU issued
|
||||
IntAlu 6020 66.28% # Type of FU issued
|
||||
IntAlu 6072 66.72% # Type of FU issued
|
||||
IntMult 1 0.01% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 2 0.02% # Type of FU issued
|
||||
|
|
@ -291,16 +291,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|||
FloatMult 0 0.00% # Type of FU issued
|
||||
FloatDiv 0 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 1973 21.72% # Type of FU issued
|
||||
MemWrite 1085 11.95% # Type of FU issued
|
||||
MemRead 1928 21.18% # Type of FU issued
|
||||
MemWrite 1096 12.04% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 107 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.011780 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 93 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.010219 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
No_OpClass 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 1 0.93% # attempts to use FU when none available
|
||||
IntAlu 2 2.15% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 0 0.00% # attempts to use FU when none available
|
||||
|
|
@ -309,100 +309,100 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 72 67.29% # attempts to use FU when none available
|
||||
MemWrite 34 31.78% # attempts to use FU when none available
|
||||
MemRead 56 60.22% # attempts to use FU when none available
|
||||
MemWrite 35 37.63% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 10556
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 12970
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 6842 6481.62%
|
||||
1 1288 1220.16%
|
||||
2 888 841.23%
|
||||
3 723 684.92%
|
||||
4 456 431.98%
|
||||
5 198 187.57%
|
||||
6 106 100.42%
|
||||
7 40 37.89%
|
||||
8 15 14.21%
|
||||
0 8890 6854.28%
|
||||
1 1667 1285.27%
|
||||
2 1037 799.54%
|
||||
3 696 536.62%
|
||||
4 340 262.14%
|
||||
5 189 145.72%
|
||||
6 103 79.41%
|
||||
7 35 26.99%
|
||||
8 13 10.02%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 0.824678 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 10508 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 9083 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 24 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 3829 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 25 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 2415 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 1700 # ITB accesses
|
||||
system.cpu.iq.ISSUE:rate 0.367213 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 10614 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 9101 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 23 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 3909 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 43 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 2399 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 1737 # ITB accesses
|
||||
system.cpu.itb.acv 0 # ITB acv
|
||||
system.cpu.itb.hits 1670 # ITB hits
|
||||
system.cpu.itb.misses 30 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 72 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 6111.111111 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 3111.111111 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 440000 # number of ReadExReq miss cycles
|
||||
system.cpu.itb.hits 1704 # ITB hits
|
||||
system.cpu.itb.misses 33 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34404.109589 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31294.520548 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2511500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 72 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 224000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2284500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 72 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 409 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 5746.323529 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2746.323529 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 407 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34399.014778 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31224.137931 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 2344500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.997555 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 408 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1120500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997555 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 408 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5633.333333 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2633.333333 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 84500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 13966000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.997543 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 406 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 12677000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997543 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 406 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 39500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.002551 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 5801.041667 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2801.041667 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_accesses 480 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34399.791232 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31234.864301 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 2784500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_miss_latency 16477500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.997917 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 479 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1344500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 14961500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.997917 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 479 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 5801.041667 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2801.041667 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 480 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34399.791232 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31234.864301 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 2784500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 480 # number of overall misses
|
||||
system.cpu.l2cache.overall_miss_latency 16477500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.997917 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 479 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1344500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 14961500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.997917 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 479 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -415,29 +415,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 392 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 220.053695 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 215.607487 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 11014 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 85 # Number of cycles rename is blocking
|
||||
system.cpu.numCycles 24784 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 319 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 4537 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IdleCycles 7177 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 73 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 14809 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 11658 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 8660 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 2106 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 791 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 116 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 4123 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 281 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 27 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 539 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 21 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 80 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 8 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 8963 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 264 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 14577 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 11538 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 8602 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 2108 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 855 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 294 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 4065 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 431 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 26 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 719 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 20 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 242 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7004
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -5,12 +5,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 23 2008 15:48:11
|
||||
M5 started Wed Jul 23 15:48:39 2008
|
||||
M5 executing on blue
|
||||
M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf
|
||||
M5 commit date Wed Jul 23 15:35:08 2008 -0700
|
||||
M5 compiled Aug 2 2008 17:07:15
|
||||
M5 started Sat Aug 2 17:08:49 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing tests/run.py quick/00.hello/alpha/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Hello world!
|
||||
Exiting @ tick 5506500 because target called exit()
|
||||
Exiting @ tick 12391500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -192,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 65172 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 209040 # Number of bytes of host memory used
|
||||
host_seconds 0.10 # Real time elapsed on the host
|
||||
host_tick_rate 208535003 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 496189 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 197472 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_tick_rate 2580329636 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 6315 # Number of instructions simulated
|
||||
sim_seconds 0.000020 # Number of seconds simulated
|
||||
sim_ticks 20250000 # Number of ticks simulated
|
||||
sim_seconds 0.000034 # Number of seconds simulated
|
||||
sim_ticks 33503000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 1168 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1076 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 2484000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 5152000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.078767 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 92 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2208000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 4876000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.078767 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 92 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 862 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 775 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 2349000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 4872000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.100928 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2088000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 4611000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.100928 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 2030 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1851 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 4833000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 10024000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.088177 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 179 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 4296000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 9487000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.088177 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 179 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 2030 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1851 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 4833000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 10024000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.088177 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 179 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 4296000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 9487000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.088177 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 179 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 165 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 104.470522 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 102.087516 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1865 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
|
|
@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
|
|||
system.cpu.dtb.write_hits 862 # DTB write hits
|
||||
system.cpu.dtb.write_misses 3 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 6326 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 26953.405018 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23953.405018 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 6047 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 7520000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.044104 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 6683000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.044104 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 6326 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 26953.405018 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 23953.405018 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 6047 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 7520000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.044104 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 279 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 6683000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 14745000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.044104 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 6326 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 26953.405018 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 23953.405018 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 6047 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 7520000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.044104 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 279 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 6683000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 14745000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.044104 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 133.005587 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 129.637082 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 6047 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -160,31 +160,31 @@ system.cpu.itb.acv 0 # IT
|
|||
system.cpu.itb.hits 6326 # ITB hits
|
||||
system.cpu.itb.misses 17 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1679000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 3796000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 803000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 371 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 8510000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 19240000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.997305 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 370 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 4070000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 14800000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997305 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 370 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 322000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -196,29 +196,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 10189000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 23036000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.997748 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 443 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 4873000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 17720000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.997748 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 443 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 444 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 10189000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 23036000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.997748 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 443 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 4873000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 17720000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.997748 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 443 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -235,12 +235,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 356 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 183.192305 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 178.910312 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 40500 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 67006 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 6315 # Number of instructions executed
|
||||
system.cpu.num_refs 2040 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7006
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -5,12 +5,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 23 2008 15:48:11
|
||||
M5 started Wed Jul 23 15:50:09 2008
|
||||
M5 executing on blue
|
||||
M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf
|
||||
M5 commit date Wed Jul 23 15:35:08 2008 -0700
|
||||
M5 compiled Aug 2 2008 17:07:15
|
||||
M5 started Sat Aug 2 17:10:34 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing tests/run.py quick/00.hello/alpha/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Hello world!
|
||||
Exiting @ tick 20250000 because target called exit()
|
||||
Exiting @ tick 33503000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -368,6 +368,7 @@ cmd=hello
|
|||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
|
|
@ -393,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 155 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 639 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.BTBHits 198 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 684 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 209 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 405 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 821 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 162 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 39438 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 151264 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_tick_rate 44410086 # Simulator tick rate (ticks/s)
|
||||
global.BPredUnit.condPredicted 447 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 859 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 165 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 67408 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 197188 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_tick_rate 201701674 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 7 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 703 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 408 # Number of stores inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedLoads 738 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 411 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2387 # Number of instructions simulated
|
||||
sim_seconds 0.000003 # Number of seconds simulated
|
||||
sim_ticks 2700000 # Number of ticks simulated
|
||||
sim_seconds 0.000007 # Number of seconds simulated
|
||||
sim_ticks 7183000 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 396 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 39 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 38 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 4866
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 6196
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 3922 8060.01%
|
||||
1 255 524.04%
|
||||
2 327 672.01%
|
||||
3 133 273.33%
|
||||
4 67 137.69%
|
||||
5 70 143.86%
|
||||
6 33 67.82%
|
||||
7 20 41.10%
|
||||
8 39 80.15%
|
||||
0 5239 8455.46%
|
||||
1 263 424.47%
|
||||
2 334 539.06%
|
||||
3 134 216.27%
|
||||
4 73 117.82%
|
||||
5 63 101.68%
|
||||
6 32 51.65%
|
||||
7 20 32.28%
|
||||
8 38 61.33%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
|
|
@ -43,69 +43,69 @@ system.cpu.commit.COM:loads 415 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 709 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 131 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 132 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 1414 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 1733 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 2387 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
|
||||
system.cpu.cpi 2.262673 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 2.262673 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 542 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 9881.944444 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7311.475410 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 470 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 711500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.132841 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 72 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 446000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.112546 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.cpi 6.018852 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 6.018852 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 573 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 35755.813953 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35680.327869 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 487 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 3075000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.150087 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 86 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 25 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2176500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.106457 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 9732.673267 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7662.162162 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 193 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 983000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.343537 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 101 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 64 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 283500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 37200.934579 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37675.675676 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 187 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 3980500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.363946 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 107 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 70 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1394000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.125850 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 8.164706 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 8.411765 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 836 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 9794.797688 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 7443.877551 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 663 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 1694500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.206938 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 173 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 75 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 729500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.117225 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_accesses 867 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 36556.994819 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 674 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 7055500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.222607 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 193 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 95 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3570500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.113033 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 836 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 9794.797688 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 7443.877551 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_accesses 867 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 36556.994819 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 663 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 1694500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.206938 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 173 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 75 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 729500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.117225 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_hits 674 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 7055500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.222607 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 193 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 95 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3570500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.113033 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
|
|
@ -121,101 +121,101 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 46.627422 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 694 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 45.884316 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 715 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 100 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 81 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 133 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 4610 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 3877 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 889 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 290 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 293 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:BlockedCycles 171 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction
|
||||
system.cpu.decode.DECODE:BranchResolved 127 # Number of times decode resolved a branch
|
||||
system.cpu.decode.DECODE:DecodedInsts 4722 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 5096 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 929 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 331 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode
|
||||
system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking
|
||||
system.cpu.dtb.accesses 936 # DTB accesses
|
||||
system.cpu.dtb.accesses 971 # DTB accesses
|
||||
system.cpu.dtb.acv 1 # DTB access violations
|
||||
system.cpu.dtb.hits 911 # DTB hits
|
||||
system.cpu.dtb.hits 946 # DTB hits
|
||||
system.cpu.dtb.misses 25 # DTB misses
|
||||
system.cpu.dtb.read_accesses 578 # DTB read accesses
|
||||
system.cpu.dtb.read_accesses 611 # DTB read accesses
|
||||
system.cpu.dtb.read_acv 1 # DTB read access violations
|
||||
system.cpu.dtb.read_hits 567 # DTB read hits
|
||||
system.cpu.dtb.read_hits 600 # DTB read hits
|
||||
system.cpu.dtb.read_misses 11 # DTB read misses
|
||||
system.cpu.dtb.write_accesses 358 # DTB write accesses
|
||||
system.cpu.dtb.write_accesses 360 # DTB write accesses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_hits 344 # DTB write hits
|
||||
system.cpu.dtb.write_hits 346 # DTB write hits
|
||||
system.cpu.dtb.write_misses 14 # DTB write misses
|
||||
system.cpu.fetch.Branches 821 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 705 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 1625 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 104 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 5290 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 238 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.152009 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 705 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 317 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.979448 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.Branches 859 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 747 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 1709 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 115 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 5393 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 240 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.059790 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 747 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 363 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 0.375374 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 5157
|
||||
system.cpu.fetch.rateDist.samples 6528
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 4266 8272.25%
|
||||
1 34 65.93%
|
||||
2 85 164.82%
|
||||
3 67 129.92%
|
||||
4 115 223.00%
|
||||
5 55 106.65%
|
||||
6 41 79.50%
|
||||
7 48 93.08%
|
||||
8 446 864.84%
|
||||
0 5595 8570.77%
|
||||
1 36 55.15%
|
||||
2 100 153.19%
|
||||
3 69 105.70%
|
||||
4 130 199.14%
|
||||
5 72 110.29%
|
||||
6 45 68.93%
|
||||
7 48 73.53%
|
||||
8 433 663.30%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 705 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 8914.634146 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6417.582418 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 500 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 1827500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.290780 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 205 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 23 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 1168000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.258156 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 182 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 747 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 35989.361702 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35298.342541 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 512 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 8457500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.314592 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 235 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 6389000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.242303 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 2.747253 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 2.828729 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 705 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 8914.634146 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6417.582418 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 500 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 1827500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.290780 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 205 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 23 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 1168000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.258156 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 747 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 35989.361702 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 512 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 8457500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.314592 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 235 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 6389000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.242303 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 705 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 8914.634146 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6417.582418 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 747 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 35989.361702 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 35298.342541 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 500 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 1827500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.290780 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 205 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 23 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 1168000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.258156 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 182 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 512 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 8457500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.314592 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 235 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 6389000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.242303 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -228,61 +228,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 182 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 91.765219 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 500 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 88.727286 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 512 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 244 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 542 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 277 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.591187 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 939 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 358 # Number of stores executed
|
||||
system.cpu.idleCycles 7839 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 584 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 286 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.236862 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 974 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 360 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 1788 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 3104 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.790828 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 1896 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 3311 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.795886 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 1414 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.574708 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 3141 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 150 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 703 # Number of dispatched load instructions
|
||||
system.cpu.iew.WB:producers 1509 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.230459 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 3349 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 151 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 10 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 738 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 408 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 4070 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 581 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 98 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 3193 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewDispSquashedInsts 57 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 411 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 4323 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 614 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 3403 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 290 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewSquashCycles 331 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 25 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 27 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 11 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 16 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 288 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 114 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 98 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 52 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.441955 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.441955 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 3291 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 323 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 117 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 97 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.166145 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.166145 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 3514 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
No_OpClass 0 0.00% # Type of FU issued
|
||||
IntAlu 2327 70.71% # Type of FU issued
|
||||
IntAlu 2506 71.31% # Type of FU issued
|
||||
IntMult 1 0.03% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 0 0.00% # Type of FU issued
|
||||
|
|
@ -291,16 +291,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|||
FloatMult 0 0.00% # Type of FU issued
|
||||
FloatDiv 0 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 599 18.20% # Type of FU issued
|
||||
MemWrite 364 11.06% # Type of FU issued
|
||||
MemRead 639 18.18% # Type of FU issued
|
||||
MemWrite 368 10.47% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.010635 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 34 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.009676 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
No_OpClass 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 1 2.86% # attempts to use FU when none available
|
||||
IntAlu 1 2.94% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 0 0.00% # attempts to use FU when none available
|
||||
|
|
@ -309,63 +309,63 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 12 34.29% # attempts to use FU when none available
|
||||
MemWrite 22 62.86% # attempts to use FU when none available
|
||||
MemRead 11 32.35% # attempts to use FU when none available
|
||||
MemWrite 22 64.71% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 5157
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 6528
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 3776 7322.09%
|
||||
1 540 1047.12%
|
||||
2 304 589.49%
|
||||
3 226 438.24%
|
||||
4 166 321.89%
|
||||
5 89 172.58%
|
||||
6 40 77.56%
|
||||
7 12 23.27%
|
||||
8 4 7.76%
|
||||
0 5051 7737.44%
|
||||
1 569 871.63%
|
||||
2 331 507.05%
|
||||
3 253 387.56%
|
||||
4 172 263.48%
|
||||
5 97 148.59%
|
||||
6 39 59.74%
|
||||
7 11 16.85%
|
||||
8 5 7.66%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 0.609332 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 3787 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 3291 # Number of instructions issued
|
||||
system.cpu.iq.ISSUE:rate 0.244588 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 4031 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 3514 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 1261 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedInstsExamined 1447 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 732 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 734 # ITB accesses
|
||||
system.cpu.iq.iqSquashedOperandsExamined 766 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.itb.accesses 776 # ITB accesses
|
||||
system.cpu.itb.acv 0 # ITB acv
|
||||
system.cpu.itb.hits 705 # ITB hits
|
||||
system.cpu.itb.hits 747 # ITB hits
|
||||
system.cpu.itb.misses 29 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 5854.166667 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2854.166667 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 140500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34604.166667 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31500 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 830500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 68500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 756000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 243 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 5440.329218 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2440.329218 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 1322000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34316.115702 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.165289 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 8304500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 243 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 593000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 7533500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 243 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5571.428571 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2571.428571 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 78000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34178.571429 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 478500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 36000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -376,32 +376,32 @@ system.cpu.l2cache.blocked_no_targets 0 # nu
|
|||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 267 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 5477.528090 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2477.528090 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34342.105263 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 1462500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 9135000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 267 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 661500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 8289500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 267 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 267 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 5477.528090 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2477.528090 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34342.105263 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 1462500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 9135000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 267 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses 266 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 661500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 8289500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 267 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -414,28 +414,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 229 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 228 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 114.387820 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 110.762790 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 5401 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 14367 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 14 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IdleCycles 3954 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 5170 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 2 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 5025 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 4444 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 3187 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 813 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 290 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 9 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 1419 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 91 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:RenameLookups 5184 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 4576 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 3269 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 856 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 331 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 11 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 1501 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 60 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:skidInsts 65 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 46 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7007
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
|
||||
|
|
|
|||
|
|
@ -5,12 +5,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 21 2008 20:12:56
|
||||
M5 started Mon Jul 21 20:12:59 2008
|
||||
M5 compiled Aug 2 2008 17:07:15
|
||||
M5 started Sat Aug 2 17:08:50 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
|
||||
M5 commit date Tue Jul 15 14:38:51 2008 -0400
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing tests/run.py quick/00.hello/alpha/tru64/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Hello world!
|
||||
Exiting @ tick 2700000 because target called exit()
|
||||
Exiting @ tick 7183000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -166,6 +166,7 @@ cmd=hello
|
|||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
|
||||
gid=100
|
||||
|
|
@ -191,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 99969 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 193012 # Number of bytes of host memory used
|
||||
host_inst_rate 96492 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 196528 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
host_tick_rate 383001655 # Simulator tick rate (ticks/s)
|
||||
host_tick_rate 644436202 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2577 # Number of instructions simulated
|
||||
sim_seconds 0.000010 # Number of seconds simulated
|
||||
sim_ticks 9950000 # Number of ticks simulated
|
||||
sim_seconds 0.000017 # Number of seconds simulated
|
||||
sim_ticks 17374000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 1485000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1320000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 1026000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 2128000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 912000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2014000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 2511000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 5208000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 2232000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 4929000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 616 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 2511000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 5208000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.131171 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 93 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 2232000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 4929000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 48.703722 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 47.575114 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
|
|
@ -93,13 +93,13 @@ system.cpu.dtb.write_acv 0 # DT
|
|||
system.cpu.dtb.write_hits 294 # DTB write hits
|
||||
system.cpu.dtb.write_misses 4 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 4401000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 9128000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 3912000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 8639000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -111,29 +111,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 4401000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 9128000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 163 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 3912000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 8639000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 2423 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 4401000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 9128000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 163 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 3912000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 8639000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -150,7 +150,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 83.077797 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 80.437325 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 2423 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -160,30 +160,30 @@ system.cpu.itb.acv 0 # IT
|
|||
system.cpu.itb.hits 2586 # ITB hits
|
||||
system.cpu.itb.misses 11 # ITB misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 621000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1404000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 297000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1080000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 5014000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_miss_latency 11336000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 2398000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 253000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 121000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 440000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 11 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -195,29 +195,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 5635000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 12740000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 2695000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 9800000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 0 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 5635000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 12740000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 245 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 2695000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 9800000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -234,12 +234,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 106.181819 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 102.857609 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 19900 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 34748 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2577 # Number of instructions executed
|
||||
system.cpu.num_refs 717 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7003
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7004
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
warn: ignoring syscall sigprocmask(1, 18446744073709547831, ...)
|
||||
|
|
|
|||
|
|
@ -5,12 +5,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 21 2008 20:12:56
|
||||
M5 started Mon Jul 21 20:24:22 2008
|
||||
M5 compiled Aug 2 2008 17:07:15
|
||||
M5 started Sat Aug 2 17:07:25 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
|
||||
M5 commit date Tue Jul 15 14:38:51 2008 -0400
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing tests/run.py quick/00.hello/alpha/tru64/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Hello world!
|
||||
Exiting @ tick 9950000 because target called exit()
|
||||
Exiting @ tick 17374000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -226,6 +226,7 @@ cmd=hello
|
|||
cwd=
|
||||
egid=100
|
||||
env=
|
||||
errout=cerr
|
||||
euid=100
|
||||
executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
|
||||
gid=100
|
||||
|
|
@ -251,7 +252,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 11117 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 195308 # Number of bytes of host memory used
|
||||
host_seconds 0.51 # Real time elapsed on the host
|
||||
host_tick_rate 38035865 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 142745 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 198836 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
host_tick_rate 810420480 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5656 # Number of instructions simulated
|
||||
sim_seconds 0.000019 # Number of seconds simulated
|
||||
sim_ticks 19359000 # Number of ticks simulated
|
||||
sim_seconds 0.000032 # Number of seconds simulated
|
||||
sim_ticks 32322000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 1130 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 1048 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 2214000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 4592000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.072566 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 82 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1968000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 4346000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.072566 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 82 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 860 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 1728000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 3584000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.069264 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 1536000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3392000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.069264 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 2054 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 3942000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 8176000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.071081 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 146 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3504000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 7738000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.071081 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 2054 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1908 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 3942000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 8176000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.071081 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 146 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3504000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 7738000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.071081 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,7 +76,7 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 132 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 84.621729 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 83.826869 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1922 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
|
|
@ -90,13 +90,13 @@ system.cpu.dtb.write_accesses 0 # DT
|
|||
system.cpu.dtb.write_hits 0 # DTB write hits
|
||||
system.cpu.dtb.write_misses 0 # DTB write misses
|
||||
system.cpu.icache.ReadReq_accesses 5658 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 26914.191419 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23914.191419 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 5355 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 8155000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.053552 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 7246000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.053552 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -108,29 +108,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 5658 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 26914.191419 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 23914.191419 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 5355 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 8155000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.053552 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 7246000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.053552 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 5658 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 26914.191419 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 23914.191419 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 5355 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 8155000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.053552 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 303 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 7246000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.053552 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -147,7 +147,7 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 13 # number of replacements
|
||||
system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 135.855992 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 134.976151 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 5355 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
|
|
@ -162,31 +162,31 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.l2cache.ReadExReq_accesses 50 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1150000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2600000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 50 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 550000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2000000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 385 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 8809000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 19916000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.994805 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 383 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 4213000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 15320000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994805 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 383 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 322000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 154000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -198,29 +198,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 435 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 9959000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 22516000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.995402 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 433 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 4763000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 17320000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.995402 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 433 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 435 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 2 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 9959000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 22516000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.995402 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 433 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 4763000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 17320000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.995402 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 433 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -237,12 +237,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 369 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 183.190154 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 181.998644 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 38718 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 64644 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 5656 # Number of instructions executed
|
||||
system.cpu.num_refs 2055 # Number of memory references
|
||||
system.cpu.tlb.accesses 0 # DTB accesses
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7007
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -5,12 +5,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 21 2008 20:31:07
|
||||
M5 started Mon Jul 21 20:31:09 2008
|
||||
M5 compiled Aug 2 2008 17:07:38
|
||||
M5 started Sat Aug 2 17:07:42 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5508:992aeed1374332d0933a68d1f1fe749e2fec0881
|
||||
M5 commit date Tue Jul 15 14:38:51 2008 -0400
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing tests/run.py quick/00.hello/mips/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Hello World!
|
||||
Exiting @ tick 19359000 because target called exit()
|
||||
Exiting @ tick 32322000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -192,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,31 +1,31 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 56962 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 210220 # Number of bytes of host memory used
|
||||
host_seconds 0.09 # Real time elapsed on the host
|
||||
host_tick_rate 184294275 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 288337 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 198672 # Number of bytes of host memory used
|
||||
host_seconds 0.02 # Real time elapsed on the host
|
||||
host_tick_rate 1546587822 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5340 # Number of instructions simulated
|
||||
sim_seconds 0.000017 # Number of seconds simulated
|
||||
sim_ticks 17315000 # Number of ticks simulated
|
||||
sim_seconds 0.000029 # Number of seconds simulated
|
||||
sim_ticks 29031000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 26759.259259 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 23759.259259 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 55222.222222 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 662 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 1445000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 2982000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.075419 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1283000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2820000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 2592000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 5376000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.142645 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 96 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2304000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5088000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.142645 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -37,29 +37,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 26913.333333 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 55720 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 52720 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 1239 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 4037000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 8358000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.107991 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 150 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3587000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 7908000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.107991 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 26913.333333 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 23913.333333 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 55720 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 52720 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 1239 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 4037000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 8358000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.107991 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 150 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3587000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 7908000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.107991 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -76,18 +76,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 83.359749 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 82.357482 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 5384 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 26898.832685 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23898.832685 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 55673.151751 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52673.151751 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 5127 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 6913000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 14308000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.047734 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 257 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 6142000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 13537000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.047734 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 257 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 5384 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 26898.832685 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 23898.832685 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 55673.151751 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 5127 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 6913000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 14308000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.047734 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 257 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 6142000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 13537000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.047734 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 257 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 26898.832685 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 23898.832685 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 55673.151751 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 5127 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 6913000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 14308000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.047734 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 257 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 6142000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 13537000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.047734 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 257 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -138,37 +138,37 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 118.738905 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 117.715481 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 5127 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1863000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 4212000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 891000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3240000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 311 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 7084000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 16016000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.990354 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 308 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 3388000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 12320000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990354 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 345000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 780000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 165000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 600000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -180,29 +180,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 392 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 8947000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 20228000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.992347 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 389 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 4279000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 15560000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.992347 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 3 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 8947000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 20228000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.992347 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 389 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 4279000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 15560000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.992347 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -219,12 +219,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 293 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 138.022706 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 136.844792 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 34630 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 58062 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 5340 # Number of instructions executed
|
||||
system.cpu.num_refs 1402 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7002
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 23 2008 16:00:51
|
||||
M5 started Wed Jul 23 16:00:56 2008
|
||||
M5 executing on blue
|
||||
M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf
|
||||
M5 commit date Wed Jul 23 15:35:08 2008 -0700
|
||||
M5 compiled Aug 2 2008 17:21:13
|
||||
M5 started Sat Aug 2 17:29:40 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing tests/run.py quick/00.hello/sparc/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Hello World!Exiting @ tick 17315000 because target called exit()
|
||||
Hello World!Exiting @ tick 29031000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -413,7 +413,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,5 +1,5 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7003
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7008
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: Increasing stack size by one page.
|
||||
warn: Increasing stack size by one page.
|
||||
|
|
|
|||
|
|
@ -5,13 +5,13 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 23 2008 15:48:11
|
||||
M5 started Wed Jul 23 15:49:40 2008
|
||||
M5 executing on blue
|
||||
M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf
|
||||
M5 commit date Wed Jul 23 15:35:08 2008 -0700
|
||||
M5 compiled Aug 2 2008 17:07:15
|
||||
M5 started Sat Aug 2 17:13:24 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing tests/run.py quick/01.hello-2T-smt/alpha/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Hello world!
|
||||
Hello world!
|
||||
Exiting @ tick 7085500 because target called exit()
|
||||
Exiting @ tick 14042500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -394,7 +394,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,40 +1,40 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
global.BPredUnit.BTBHits 4364 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 10024 # Number of BTB lookups
|
||||
global.BPredUnit.BTBHits 4398 # Number of BTB hits
|
||||
global.BPredUnit.BTBLookups 9844 # Number of BTB lookups
|
||||
global.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
|
||||
global.BPredUnit.condIncorrect 2911 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 11601 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 11601 # Number of BP lookups
|
||||
global.BPredUnit.condIncorrect 2923 # Number of conditional branches incorrect
|
||||
global.BPredUnit.condPredicted 11413 # Number of conditional branches predicted
|
||||
global.BPredUnit.lookups 11413 # Number of BP lookups
|
||||
global.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
|
||||
host_inst_rate 6832 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 210732 # Number of bytes of host memory used
|
||||
host_seconds 2.11 # Real time elapsed on the host
|
||||
host_tick_rate 10370738 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 29 # Number of conflicting loads.
|
||||
host_inst_rate 50656 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 199212 # Number of bytes of host memory used
|
||||
host_seconds 0.29 # Real time elapsed on the host
|
||||
host_tick_rate 97240761 # Simulator tick rate (ticks/s)
|
||||
memdepunit.memDep.conflictingLoads 26 # Number of conflicting loads.
|
||||
memdepunit.memDep.conflictingStores 0 # Number of conflicting stores.
|
||||
memdepunit.memDep.insertedLoads 4977 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 3503 # Number of stores inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedLoads 4960 # Number of loads inserted to the mem dependence unit.
|
||||
memdepunit.memDep.insertedStores 3415 # Number of stores inserted to the mem dependence unit.
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 14449 # Number of instructions simulated
|
||||
sim_seconds 0.000022 # Number of seconds simulated
|
||||
sim_ticks 21933500 # Number of ticks simulated
|
||||
sim_seconds 0.000028 # Number of seconds simulated
|
||||
sim_ticks 27756500 # Number of ticks simulated
|
||||
system.cpu.commit.COM:branches 3359 # Number of branches committed
|
||||
system.cpu.commit.COM:bw_lim_events 105 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_lim_events 103 # number cycles where commit BW limit reached
|
||||
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
|
||||
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 39346
|
||||
system.cpu.commit.COM:committed_per_cycle.samples 42766
|
||||
system.cpu.commit.COM:committed_per_cycle.min_value 0
|
||||
0 31195 7928.38%
|
||||
1 4789 1217.15%
|
||||
2 1729 439.43%
|
||||
3 717 182.23%
|
||||
4 416 105.73%
|
||||
5 147 37.36%
|
||||
6 198 50.32%
|
||||
7 50 12.71%
|
||||
8 105 26.69%
|
||||
0 34594 8089.14%
|
||||
1 4804 1123.32%
|
||||
2 1741 407.10%
|
||||
3 720 168.36%
|
||||
4 413 96.57%
|
||||
5 144 33.67%
|
||||
6 196 45.83%
|
||||
7 51 11.93%
|
||||
8 103 24.08%
|
||||
system.cpu.commit.COM:committed_per_cycle.max_value 8
|
||||
system.cpu.commit.COM:committed_per_cycle.end_dist
|
||||
|
||||
|
|
@ -43,72 +43,72 @@ system.cpu.commit.COM:loads 2226 # Nu
|
|||
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
|
||||
system.cpu.commit.COM:refs 3674 # Number of memory references committed
|
||||
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
|
||||
system.cpu.commit.branchMispredicts 2911 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.branchMispredicts 2923 # The number of times a branch was mispredicted
|
||||
system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
|
||||
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
|
||||
system.cpu.commit.commitSquashedInsts 20100 # The number of squashed insts skipped by commit
|
||||
system.cpu.commit.commitSquashedInsts 19906 # The number of squashed insts skipped by commit
|
||||
system.cpu.committedInsts 14449 # Number of Instructions Simulated
|
||||
system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
|
||||
system.cpu.cpi 3.036058 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 3.036058 # CPI: Total CPI of All Threads
|
||||
system.cpu.cpi 3.842065 # CPI: Cycles Per Instruction
|
||||
system.cpu.cpi_total 3.842065 # CPI: Total CPI of All Threads
|
||||
system.cpu.dcache.ReadReq_accesses 3844 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 9408.602151 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7113.636364 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 3751 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 875000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.024194 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 93 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 469500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.017170 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 66 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 35152.173913 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35569.230769 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 3729 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4042500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.029917 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 115 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits 50 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2312000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.016909 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 9957.589286 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 7000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 1218 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 2230500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.155340 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 224 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 122 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 714000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 31253.950339 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35632.352941 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 999 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 13845500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.307212 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 443 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits 341 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 3634500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 33.590604 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.avg_refs 32.229730 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 5286 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 9796.529968 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 7044.642857 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 4969 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 3105500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.059970 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 317 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 149 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 1183500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.031782 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_avg_miss_latency 32057.347670 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 4728 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 17888000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.105562 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 558 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 391 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 5946500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.031593 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 167 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 5286 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 9796.529968 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 7044.642857 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 32057.347670 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 35607.784431 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 4969 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 3105500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.059970 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 317 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 149 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 1183500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.031782 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_hits 4728 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 17888000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.105562 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 558 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 391 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 5946500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.031593 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 167 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -121,88 +121,88 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 114.768529 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 5005 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 108.665251 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 4770 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.decode.DECODE:BlockedCycles 5414 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 52959 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 18733 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 15067 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 4338 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 132 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 11601 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 7392 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 24155 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 764 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 59501 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 3008 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.264452 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 7392 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 4364 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.356365 # Number of inst fetches per cycle
|
||||
system.cpu.decode.DECODE:BlockedCycles 7143 # Number of cycles decode is blocked
|
||||
system.cpu.decode.DECODE:DecodedInsts 51830 # Number of instructions handled by decode
|
||||
system.cpu.decode.DECODE:IdleCycles 20508 # Number of cycles decode is idle
|
||||
system.cpu.decode.DECODE:RunCycles 14980 # Number of cycles decode is running
|
||||
system.cpu.decode.DECODE:SquashCycles 4324 # Number of cycles decode is squashing
|
||||
system.cpu.decode.DECODE:UnblockCycles 135 # Number of cycles decode is unblocking
|
||||
system.cpu.fetch.Branches 11413 # Number of branches that fetch encountered
|
||||
system.cpu.fetch.CacheLines 7356 # Number of cache lines fetched
|
||||
system.cpu.fetch.Cycles 24020 # Number of cycles fetch has run and was not squashing or blocked
|
||||
system.cpu.fetch.IcacheSquashes 845 # Number of outstanding Icache misses that were squashed
|
||||
system.cpu.fetch.Insts 58247 # Number of instructions fetch has processed
|
||||
system.cpu.fetch.SquashCycles 3019 # Number of cycles fetch has spent squashing
|
||||
system.cpu.fetch.branchRate 0.205588 # Number of branch fetches per cycle
|
||||
system.cpu.fetch.icacheStallCycles 7356 # Number of cycles fetch is stalled on an Icache miss
|
||||
system.cpu.fetch.predictedBranches 4398 # Number of branches that fetch has predicted taken
|
||||
system.cpu.fetch.rate 1.049231 # Number of inst fetches per cycle
|
||||
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
|
||||
system.cpu.fetch.rateDist.samples 43684
|
||||
system.cpu.fetch.rateDist.samples 47090
|
||||
system.cpu.fetch.rateDist.min_value 0
|
||||
0 26944 6167.93%
|
||||
1 7490 1714.59%
|
||||
2 1209 276.76%
|
||||
3 1044 238.99%
|
||||
4 1055 241.51%
|
||||
5 1191 272.64%
|
||||
6 698 159.78%
|
||||
7 326 74.63%
|
||||
8 3727 853.17%
|
||||
0 30448 6465.92%
|
||||
1 7532 1599.49%
|
||||
2 1217 258.44%
|
||||
3 1059 224.89%
|
||||
4 1060 225.10%
|
||||
5 1193 253.34%
|
||||
6 711 150.99%
|
||||
7 327 69.44%
|
||||
8 3543 752.39%
|
||||
system.cpu.fetch.rateDist.max_value 8
|
||||
system.cpu.fetch.rateDist.end_dist
|
||||
|
||||
system.cpu.icache.ReadReq_accesses 7392 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 8917.690418 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 6472.527473 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 6985 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 3629500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.055060 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 407 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 2356000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.049242 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 364 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_accesses 7356 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 33620.560748 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 34869.080780 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 6821 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 17987000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.072730 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 535 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_hits 176 # number of ReadReq MSHR hits
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 12518000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.048804 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 19.189560 # Average number of references to valid blocks.
|
||||
system.cpu.icache.avg_refs 19.053073 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 7392 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 8917.690418 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 6472.527473 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 6985 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 3629500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.055060 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 407 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 43 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 2356000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.049242 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 364 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_accesses 7356 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 33620.560748 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 6821 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 17987000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.072730 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 535 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 176 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 12518000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.048804 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 359 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 7392 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 8917.690418 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 6472.527473 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_accesses 7356 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 33620.560748 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 6985 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 3629500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.055060 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 407 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 43 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 2356000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.049242 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 364 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_hits 6821 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 17987000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.072730 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 535 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 176 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 12518000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.048804 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 359 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -215,61 +215,61 @@ system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 1 # number of replacements
|
||||
system.cpu.icache.sampled_refs 364 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.sampled_refs 358 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 247.187481 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 6985 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 226.836007 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 6821 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idleCycles 184 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 4855 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 2093 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.570211 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 6456 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 2482 # Number of stores executed
|
||||
system.cpu.idleCycles 8424 # Total number of cycles that the CPU has spent unscheduled due to idling
|
||||
system.cpu.iew.EXEC:branches 4842 # Number of branches executed
|
||||
system.cpu.iew.EXEC:nop 2091 # number of nop insts executed
|
||||
system.cpu.iew.EXEC:rate 0.447815 # Inst execution rate
|
||||
system.cpu.iew.EXEC:refs 6412 # number of memory reference insts executed
|
||||
system.cpu.iew.EXEC:stores 2454 # Number of stores executed
|
||||
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
|
||||
system.cpu.iew.WB:consumers 13185 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 24031 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.826773 # average fanout of values written-back
|
||||
system.cpu.iew.WB:consumers 13039 # num instructions consuming a value
|
||||
system.cpu.iew.WB:count 23891 # cumulative count of insts written-back
|
||||
system.cpu.iew.WB:fanout 0.827287 # average fanout of values written-back
|
||||
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
|
||||
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
||||
system.cpu.iew.WB:producers 10901 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.547802 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 24254 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 3206 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 4977 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 772 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 3232 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 3503 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 35402 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 3974 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 4417 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 25014 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.WB:producers 10787 # num instructions producing a value
|
||||
system.cpu.iew.WB:rate 0.430360 # insts written-back per cycle
|
||||
system.cpu.iew.WB:sent 24098 # cumulative count of insts sent to commit
|
||||
system.cpu.iew.branchMispredicts 3211 # Number of branch mispredicts detected at execute
|
||||
system.cpu.iew.iewBlockCycles 24 # Number of cycles IEW is blocking
|
||||
system.cpu.iew.iewDispLoadInsts 4960 # Number of dispatched load instructions
|
||||
system.cpu.iew.iewDispNonSpecInsts 773 # Number of dispatched non-speculative instructions
|
||||
system.cpu.iew.iewDispSquashedInsts 3053 # Number of squashed instructions skipped by dispatch
|
||||
system.cpu.iew.iewDispStoreInsts 3415 # Number of dispatched store instructions
|
||||
system.cpu.iew.iewDispatchedInsts 35166 # Number of instructions dispatched to IQ
|
||||
system.cpu.iew.iewExecLoadInsts 3958 # Number of load instructions executed
|
||||
system.cpu.iew.iewExecSquashedInsts 4360 # Number of squashed instructions skipped in execute
|
||||
system.cpu.iew.iewExecutedInsts 24860 # Number of executed instructions
|
||||
system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall
|
||||
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
||||
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
||||
system.cpu.iew.iewSquashCycles 4338 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.iewSquashCycles 4324 # Number of cycles IEW is squashing
|
||||
system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
|
||||
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
||||
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.forwLoads 34 # Number of loads that had data forwarded from stores
|
||||
system.cpu.iew.lsq.thread.0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
|
||||
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 58 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.memOrderViolation 53 # Number of memory ordering violations
|
||||
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 2751 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 2055 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 58 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 769 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 2437 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.329374 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.329374 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 29431 # Type of FU issued
|
||||
system.cpu.iew.lsq.thread.0.squashedLoads 2734 # Number of loads squashed
|
||||
system.cpu.iew.lsq.thread.0.squashedStores 1967 # Number of stores squashed
|
||||
system.cpu.iew.memOrderViolationEvents 53 # Number of memory order violations
|
||||
system.cpu.iew.predictedNotTakenIncorrect 758 # Number of branches that were predicted not taken incorrectly
|
||||
system.cpu.iew.predictedTakenIncorrect 2453 # Number of branches that were predicted taken incorrectly
|
||||
system.cpu.ipc 0.260277 # IPC: Instructions Per Cycle
|
||||
system.cpu.ipc_total 0.260277 # IPC: Total IPC of All Threads
|
||||
system.cpu.iq.ISSUE:FU_type_0 29220 # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.start_dist
|
||||
No_OpClass 0 0.00% # Type of FU issued
|
||||
IntAlu 21547 73.21% # Type of FU issued
|
||||
IntAlu 21395 73.22% # Type of FU issued
|
||||
IntMult 0 0.00% # Type of FU issued
|
||||
IntDiv 0 0.00% # Type of FU issued
|
||||
FloatAdd 0 0.00% # Type of FU issued
|
||||
|
|
@ -278,16 +278,16 @@ system.cpu.iq.ISSUE:FU_type_0.start_dist
|
|||
FloatMult 0 0.00% # Type of FU issued
|
||||
FloatDiv 0 0.00% # Type of FU issued
|
||||
FloatSqrt 0 0.00% # Type of FU issued
|
||||
MemRead 4739 16.10% # Type of FU issued
|
||||
MemWrite 3145 10.69% # Type of FU issued
|
||||
MemRead 4720 16.15% # Type of FU issued
|
||||
MemWrite 3105 10.63% # Type of FU issued
|
||||
IprAccess 0 0.00% # Type of FU issued
|
||||
InstPrefetch 0 0.00% # Type of FU issued
|
||||
system.cpu.iq.ISSUE:FU_type_0.end_dist
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 188 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.006388 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_busy_cnt 173 # FU busy when requested
|
||||
system.cpu.iq.ISSUE:fu_busy_rate 0.005921 # FU busy rate (busy events/executed inst)
|
||||
system.cpu.iq.ISSUE:fu_full.start_dist
|
||||
No_OpClass 0 0.00% # attempts to use FU when none available
|
||||
IntAlu 49 26.06% # attempts to use FU when none available
|
||||
IntAlu 40 23.12% # attempts to use FU when none available
|
||||
IntMult 0 0.00% # attempts to use FU when none available
|
||||
IntDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatAdd 0 0.00% # attempts to use FU when none available
|
||||
|
|
@ -296,96 +296,96 @@ system.cpu.iq.ISSUE:fu_full.start_dist
|
|||
FloatMult 0 0.00% # attempts to use FU when none available
|
||||
FloatDiv 0 0.00% # attempts to use FU when none available
|
||||
FloatSqrt 0 0.00% # attempts to use FU when none available
|
||||
MemRead 25 13.30% # attempts to use FU when none available
|
||||
MemWrite 114 60.64% # attempts to use FU when none available
|
||||
MemRead 20 11.56% # attempts to use FU when none available
|
||||
MemWrite 113 65.32% # attempts to use FU when none available
|
||||
IprAccess 0 0.00% # attempts to use FU when none available
|
||||
InstPrefetch 0 0.00% # attempts to use FU when none available
|
||||
system.cpu.iq.ISSUE:fu_full.end_dist
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 43684
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.samples 47090
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
|
||||
0 30754 7040.11%
|
||||
1 5431 1243.25%
|
||||
2 3052 698.65%
|
||||
3 2131 487.82%
|
||||
4 1026 234.87%
|
||||
5 660 151.09%
|
||||
6 361 82.64%
|
||||
7 219 50.13%
|
||||
8 50 11.45%
|
||||
0 34112 7244.00%
|
||||
1 5516 1171.37%
|
||||
2 3070 651.94%
|
||||
3 2146 455.72%
|
||||
4 997 211.72%
|
||||
5 653 138.67%
|
||||
6 342 72.63%
|
||||
7 211 44.81%
|
||||
8 43 9.13%
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
|
||||
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
|
||||
|
||||
system.cpu.iq.ISSUE:rate 0.670899 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 32537 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 29431 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 772 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 16058 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 100 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 297 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 12535 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.iq.ISSUE:rate 0.526354 # Inst issue rate
|
||||
system.cpu.iq.iqInstsAdded 32302 # Number of instructions added to the IQ (excludes non-spec)
|
||||
system.cpu.iq.iqInstsIssued 29220 # Number of instructions issued
|
||||
system.cpu.iq.iqNonSpecInstsAdded 773 # Number of non-speculative instructions added to the IQ
|
||||
system.cpu.iq.iqSquashedInstsExamined 15806 # Number of squashed instructions iterated over during squash; mainly for profiling
|
||||
system.cpu.iq.iqSquashedInstsIssued 120 # Number of squashed instructions issued
|
||||
system.cpu.iq.iqSquashedNonSpecRemoved 298 # Number of squashed non-spec instructions that were removed
|
||||
system.cpu.iq.iqSquashedOperandsExamined 12375 # Number of squashed operands that are examined and possibly removed from graph
|
||||
system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 5795.180723 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2795.180723 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 481000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 34409.638554 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31307.228916 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 2856000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 232000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2598500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 430 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 5433.098592 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2433.098592 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_accesses 424 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 34221.428571 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31008.333333 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 2314500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.990698 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 426 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1036500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990698 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 426 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 14373000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.990566 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 420 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 13023500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990566 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 420 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 5578.947368 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2578.947368 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 106000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 34394.736842 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31210.526316 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 653500 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 49000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 593000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.009828 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_refs 0.010000 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 513 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 5492.141454 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 2492.141454 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_accesses 507 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 34252.485089 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 2795500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.992203 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 509 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_miss_latency 17229000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.992110 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 503 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1268500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.992203 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 509 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 15622000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.992110 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 503 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 513 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 5492.141454 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 2492.141454 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 34252.485089 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 31057.654076 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 4 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 2795500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.992203 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 509 # number of overall misses
|
||||
system.cpu.l2cache.overall_miss_latency 17229000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.992110 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 503 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1268500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.992203 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 509 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 15622000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.992110 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 503 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -398,27 +398,30 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 273.898723 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 251.642612 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.numCycles 43868 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 55514 # number of cpu cycles simulated
|
||||
system.cpu.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking
|
||||
system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed
|
||||
system.cpu.rename.RENAME:IdleCycles 20565 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:RenameLookups 76206 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 43436 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 36362 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 13390 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 4338 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 306 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 22530 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 5085 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 899 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 5188 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 833 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 58 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.rename.RENAME:IQFullEvents 1 # Number of times rename has blocked due to IQ full
|
||||
system.cpu.rename.RENAME:IdleCycles 22322 # Number of cycles rename is idle
|
||||
system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full
|
||||
system.cpu.rename.RENAME:RenameLookups 74771 # Number of register rename lookups that rename has made
|
||||
system.cpu.rename.RENAME:RenamedInsts 42575 # Number of instructions processed by rename
|
||||
system.cpu.rename.RENAME:RenamedOperands 35749 # Number of destination operands rename has renamed
|
||||
system.cpu.rename.RENAME:RunCycles 13324 # Number of cycles rename is running
|
||||
system.cpu.rename.RENAME:SquashCycles 4324 # Number of cycles rename is squashing
|
||||
system.cpu.rename.RENAME:UnblockCycles 311 # Number of cycles rename is unblocking
|
||||
system.cpu.rename.RENAME:UndoneMaps 21917 # Number of HB maps that are undone due to squashing
|
||||
system.cpu.rename.RENAME:serializeStallCycles 6777 # count of cycles rename stalled for serializing inst
|
||||
system.cpu.rename.RENAME:serializingInsts 888 # count of serializing insts renamed
|
||||
system.cpu.rename.RENAME:skidInsts 5129 # count of insts added to the skid buffer
|
||||
system.cpu.rename.RENAME:tempSerializingInsts 820 # count of temporary serializing insts renamed
|
||||
system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
||||
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 23 2008 16:00:51
|
||||
M5 started Wed Jul 23 16:00:53 2008
|
||||
M5 executing on blue
|
||||
M5 revision 5515:47bf96eec2c6221cf91de8a078897c1b5e46cfbf
|
||||
M5 commit date Wed Jul 23 15:35:08 2008 -0700
|
||||
M5 compiled Aug 2 2008 17:21:13
|
||||
M5 started Sat Aug 2 17:29:40 2008
|
||||
M5 executing on zizzer
|
||||
M5 revision 5517:3ad997252dd241f919fe7d9071a0a136e29ac424
|
||||
M5 commit date Thu Jul 31 08:01:38 2008 -0700
|
||||
command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing tests/run.py quick/02.insttest/sparc/linux/o3-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
Begining test of difficult SPARC instructions...
|
||||
|
|
@ -23,4 +23,4 @@ LDTX: Passed
|
|||
LDTW: Passed
|
||||
STTW: Passed
|
||||
Done
|
||||
Exiting @ tick 21933500 because target called exit()
|
||||
Exiting @ tick 27756500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -192,7 +192,7 @@ port=system.physmem.port[0] system.cpu.l2cache.mem_side
|
|||
[system.physmem]
|
||||
type=PhysicalMemory
|
||||
file=
|
||||
latency=1
|
||||
latency=30000
|
||||
latency_var=0
|
||||
null=false
|
||||
range=0:134217727
|
||||
|
|
|
|||
|
|
@ -1,33 +1,33 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 26211 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 210104 # Number of bytes of host memory used
|
||||
host_seconds 0.58 # Real time elapsed on the host
|
||||
host_tick_rate 52105150 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 494493 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 198556 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
host_tick_rate 1381087807 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 15175 # Number of instructions simulated
|
||||
sim_seconds 0.000030 # Number of seconds simulated
|
||||
sim_ticks 30178000 # Number of ticks simulated
|
||||
sim_seconds 0.000043 # Number of seconds simulated
|
||||
sim_ticks 42735000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 27000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 24000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 2173 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 1431000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency 2968000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.023810 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 53 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 1272000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 2809000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.023810 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 53 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
|
||||
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
|
||||
system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 27000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 1340 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 2754000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency 5712000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.070735 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 102 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 2448000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 5406000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -39,29 +39,29 @@ system.cpu.dcache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 3513 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 4185000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency 8680000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.042257 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 155 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3720000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 8215000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.042257 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 27000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 24000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 3513 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 4185000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency 8680000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.042257 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 155 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3720000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 8215000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.042257 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -78,18 +78,18 @@ system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.dcache.replacements 0 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 102.837167 # Cycle average of tags in use
|
||||
system.cpu.dcache.tagsinuse 97.747327 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 0 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 15221 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 26907.142857 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23907.142857 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 55700 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52700 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 14941 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 7534000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency 15596000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.018396 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 280 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 6694000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 14756000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.018396 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 280 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -101,29 +101,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
|
|||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 15221 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 26907.142857 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 23907.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 55700 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 52700 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 14941 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 7534000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 15596000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.018396 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 280 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 6694000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 14756000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.018396 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 280 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 26907.142857 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 23907.142857 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 14941 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 7534000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 15596000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.018396 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 280 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 6694000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 14756000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.018396 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 280 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -140,37 +140,37 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 0 # number of replacements
|
||||
system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 165.376172 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 153.073222 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 14941 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadExReq_accesses 85 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 23000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 11000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 1955000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_miss_latency 4420000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_misses 85 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 935000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency 3400000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_misses 85 # number of ReadExReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_accesses 333 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 23000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 11000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 7613000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 17212000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.993994 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 331 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 3641000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 13240000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993994 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 331 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 23000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 11000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 391000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
|
||||
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
|
||||
system.cpu.l2cache.UpgradeReq_miss_latency 884000 # number of UpgradeReq miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 187000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 680000 # number of UpgradeReq MSHR miss cycles
|
||||
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
|
|
@ -182,29 +182,29 @@ system.cpu.l2cache.blocked_cycles_no_mshrs 0 #
|
|||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 418 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 9568000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 21632000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.995215 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 416 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 4576000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 16640000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.995215 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 416 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 23000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 11000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 2 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 9568000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency 21632000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.995215 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 416 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 4576000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 16640000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.995215 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 416 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -221,12 +221,12 @@ system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 314 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 187.735043 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 174.433606 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 60356 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 85470 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 15175 # Number of instructions executed
|
||||
system.cpu.num_refs 3684 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
0: system.remote_gdb.listener: listening for remote gdb on port 7001
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue