X86: Change the I8259 from a subdevice into a real SimObject.

--HG--
rename : src/dev/x86/south_bridge/i8259.cc => src/dev/x86/i8259.cc
rename : src/dev/x86/south_bridge/i8259.hh => src/dev/x86/i8259.hh
This commit is contained in:
Gabe Black 2008-10-11 01:22:20 -07:00
parent f22c7d48f3
commit 2753c07dc5
8 changed files with 81 additions and 30 deletions

37
src/dev/x86/I8259.py Normal file
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@ -0,0 +1,37 @@
# Copyright (c) 2008 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
from m5.params import *
from m5.proxy import *
from Device import BasicPioDevice
class I8259(BasicPioDevice):
type = 'I8259'
cxx_class='X86ISA::I8259'
pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
master = Param.Bool(True, 'If this PIC is the master or slave')

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@ -32,6 +32,7 @@ from m5.proxy import *
from Cmos import Cmos
from Device import IsaFake
from Pci import PciConfigAll
from I8259 import I8259
from Platform import Platform
from SouthBridge import SouthBridge
from Terminal import Terminal
@ -49,6 +50,8 @@ class PC(Platform):
south_bridge = SouthBridge()
cmos = Cmos(pio_addr=x86IOAddress(0x70))
pic1 = I8259(pio_addr=x86IOAddress(0x20), master=True)
pic2 = I8259(pio_addr=x86IOAddress(0xA0), master=False)
# "Non-existant" port used for timing purposes by the linux kernel
i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
@ -66,6 +69,8 @@ class PC(Platform):
def attachIO(self, bus):
self.south_bridge.pio = bus.port
self.cmos.pio = bus.port
self.pic1.pio = bus.port
self.pic2.pio = bus.port
self.i_dont_exist.pio = bus.port
self.behind_pci.pio = bus.port
self.com_1.pio = bus.port

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@ -37,3 +37,7 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
SimObject('Cmos.py')
Source('cmos.cc')
TraceFlag('CMOS', 'Accesses to CMOS devices')
SimObject('I8259.py')
Source('i8259.cc')
TraceFlag('I8259', 'Accesses to the I8259 PIC devices')

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@ -28,18 +28,24 @@
* Authors: Gabe Black
*/
#include "dev/x86/south_bridge/i8259.hh"
#include "dev/x86/i8259.hh"
Tick
X86ISA::I8259::read(PacketPtr pkt)
{
warn("Reading from PIC device.\n");
return SubDevice::read(pkt);
DPRINTF(I8259, "Reading from PIC device.\n");
return latency;
}
Tick
X86ISA::I8259::write(PacketPtr pkt)
{
warn("Writing to PIC device.\n");
return SubDevice::write(pkt);
DPRINTF(I8259, "Writing to PIC device.\n");
return latency;
}
X86ISA::I8259 *
I8259Params::create()
{
return new X86ISA::I8259(this);
}

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@ -28,27 +28,36 @@
* Authors: Gabe Black
*/
#ifndef __DEV_X86_SOUTH_BRIDGE_I8259_HH__
#define __DEV_X86_SOUTH_BRIDGE_I8259_HH__
#ifndef __DEV_X86_I8259_HH__
#define __DEV_X86_I8259_HH__
#include "arch/x86/x86_traits.hh"
#include "base/range.hh"
#include "dev/x86/south_bridge/sub_device.hh"
#include "dev/io_device.hh"
#include "params/I8259.hh"
namespace X86ISA
{
class I8259 : public SubDevice
class I8259 : public BasicPioDevice
{
public:
protected:
Tick latency;
bool master;
I8259()
{}
I8259(Tick _latency) : SubDevice(_latency)
{}
I8259(Addr start, Addr size, Tick _latency) :
SubDevice(start, size, _latency)
{}
public:
typedef I8259Params Params;
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
I8259(Params * p) : BasicPioDevice(p)
{
pioSize = 2;
latency = p->pio_latency;
master = p->master;
}
Tick read(PacketPtr pkt);
@ -57,4 +66,4 @@ class I8259 : public SubDevice
}; // namespace X86ISA
#endif //__DEV_X86_SOUTH_BRIDGE_I8259_HH__
#endif //__DEV_X86_I8259_HH__

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@ -37,7 +37,6 @@ if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
# Sub devices
Source('i8254.cc')
Source('i8259.cc')
Source('speaker.cc')
TraceFlag('PCSpeaker')

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@ -67,13 +67,9 @@ SouthBridge::write(PacketPtr pkt)
}
SouthBridge::SouthBridge(const Params *p) : PioDevice(p),
pic1(0x20, 2, p->pio_latency),
pic2(0xA0, 2, p->pio_latency),
pit(this, p->name + ".pit", 0x40, 4, p->pio_latency),
speaker(&pit, 0x61, 1, p->pio_latency)
{
addDevice(pic1);
addDevice(pic2);
addDevice(pit);
addDevice(speaker);

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@ -34,7 +34,6 @@
#include "base/range_map.hh"
#include "dev/io_device.hh"
#include "dev/x86/south_bridge/i8254.hh"
#include "dev/x86/south_bridge/i8259.hh"
#include "dev/x86/south_bridge/speaker.hh"
#include "dev/x86/south_bridge/sub_device.hh"
#include "params/SouthBridge.hh"
@ -52,10 +51,6 @@ class SouthBridge : public PioDevice
void addDevice(X86ISA::SubDevice &);
public:
// PICs
X86ISA::I8259 pic1;
X86ISA::I8259 pic2;
// I8254 Programmable Interval Timer
X86ISA::I8254 pit;