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ARM: Fix PC operand handling.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:02 -05:00
parent 7eb3ea2798
commit b6e7029dd5
2 changed files with 13 additions and 6 deletions
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12
src/arch/arm/insts/static_inst.hh
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@ -139,6 +139,18 @@ class ArmStaticInstBase : public StaticInst
return ((spsr & ~bitMask) | (val & bitMask));
}
template<class XC>
static Addr
readPC(XC *xc)
{
Addr pc = xc->readPC();
Addr tBit = pc & (ULL(1) << PcTBitShift);
if (tBit)
return pc + 4;
else
return pc + 8;
}
template<class XC>
static void
setNextPC(XC *xc, Addr val)

7
src/arch/arm/isa/operands.isa
View file

@ -53,7 +53,7 @@ def operand_types {{
let {{
maybePCRead = '''
((%(reg_idx)s == PCReg) ? ((xc->readPC() & ~PcModeMask) + 8) :
((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) :
xc->%(func)s(this, %(op_idx)s))
'''
maybePCWrite = '''
@ -61,9 +61,6 @@ let {{
xc->%(func)s(this, %(op_idx)s, %(final_val)s))
'''
readPC = 'xc->readPC() & ~PcModeMask'
writePC = 'setPC(xc, %(final_val)s)'
readNPC = 'xc->readNextPC() & ~PcModeMask'
writeNPC = 'setNextPC(xc, %(final_val)s)'
}};
@ -117,8 +114,6 @@ def operands {{
'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
'PC': ('PC', 'ud', None, (None, None, 'IsControl'), 50,
readPC, writePC),
'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
readNPC, writeNPC),
}};