X86: Do a merge for the zero extension microop.

src/arch/x86/isa/insts/general_purpose/data_conversion/translate.py

@@ -55,7 +55,7 @@
 
 microcode = '''
 def macroop XLAT {
-    zexti t1, rax, 7
+    zexti t1, rax, 7, dataSize=8
     # Here, t1 can be used directly. The value of al is supposed to be treated
     # as unsigned. Since we zero extended it from 8 bits above and the address
     # size has to be at least 16 bits, t1 will not be sign extended.

src/arch/x86/isa/insts/general_purpose/data_transfer/move.py

@@ -215,7 +215,7 @@ def macroop MOV_P_S {
 };
 
 def macroop MOV_REAL_S_R {
-    zext t2, regm, 15
+    zext t2, regm, 15, dataSize=8
     slli t3, t2, 2, dataSize=8
     wrsel reg, regm
     wrbase reg, t3
@@ -223,7 +223,7 @@ def macroop MOV_REAL_S_R {
 
 def macroop MOV_REAL_S_M {
     ld t1, seg, sib, disp, dataSize=2
-    zext t2, t1, 15
+    zext t2, t1, 15, dataSize=8
     slli t3, t2, 2, dataSize=8
     wrsel reg, t1
     wrbase reg, t3
@@ -232,7 +232,7 @@ def macroop MOV_REAL_S_M {
 def macroop MOV_REAL_S_P {
     rdip t7
     ld t1, seg, riprel, disp, dataSize=2
-    zext t2, t1, 15
+    zext t2, t1, 15, dataSize=8
     slli t3, t2, 2, dataSize=8
     wrsel reg, t1
     wrbase reg, t3

src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py

@@ -162,9 +162,9 @@ def macroop ENTER_I_I {
 
     # Pull the different components out of the immediate
     limm t1, imm
-    zexti t2, t1, 15, dataSize=2
+    zexti t2, t1, 15, dataSize=8
     srl t1, t1, 16
-    zexti t1, t1, 5
+    zexti t1, t1, 5, dataSize=8
     # t1 is now the masked nesting level, and t2 is the amount of storage.
 
     # Push rbp.

src/arch/x86/isa/insts/general_purpose/input_output/general_io.py

@@ -89,7 +89,7 @@ microcode = '''
     };
 
     def macroop IN_R_R {
-        zexti t2, regm, 15, dataSize=2
+        zexti t2, regm, 15, dataSize=8
         ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4
     };
 
@@ -100,7 +100,7 @@ microcode = '''
     };
 
     def macroop OUT_R_R {
-        zexti t2, reg, 15, dataSize=2
+        zexti t2, reg, 15, dataSize=8
         st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4
     };
 '''

src/arch/x86/isa/insts/general_purpose/input_output/string_io.py

@@ -61,7 +61,7 @@ def macroop INS_M_R {
     subi t4, t0, dsz, dataSize=asz
     mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
 
-    zexti t2, reg, 15, dataSize=2
+    zexti t2, reg, 15, dataSize=8
 
     ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
     st t6, es, [1, t0, rdi]
@@ -78,7 +78,7 @@ def macroop INS_E_M_R {
     subi t4, t0, dsz, dataSize=asz
     mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
 
-    zexti t2, reg, 15, dataSize=2
+    zexti t2, reg, 15, dataSize=8
 
 topOfLoop:
     ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
@@ -98,7 +98,7 @@ def macroop OUTS_R_M {
     subi t4, t0, dsz, dataSize=asz
     mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
 
-    zexti t2, reg, 15, dataSize=2
+    zexti t2, reg, 15, dataSize=8
 
     ld t6, ds, [1, t0, rsi]
     st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
@@ -115,7 +115,7 @@ def macroop OUTS_E_R_M {
     subi t4, t0, dsz, dataSize=asz
     mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
 
-    zexti t2, reg, 15, dataSize=2
+    zexti t2, reg, 15, dataSize=8
 
 topOfLoop:
     ld t6, ds, [1, t0, rsi]

src/arch/x86/isa/insts/system/segmentation.py

@@ -92,7 +92,7 @@ def macroop LGDT_16_M
     ld t1, seg, sib, disp, dataSize=2
     # Get the base
     ld t2, seg, sib, 'adjustedDisp + 2', dataSize=4
-    zexti t2, t2, 23
+    zexti t2, t2, 23, dataSize=8
     wrbase tsg, t2
     wrlimit tsg, t1
 };
@@ -106,7 +106,7 @@ def macroop LGDT_16_P
     ld t1, seg, riprel, disp, dataSize=2
     # Get the base
     ld t2, seg, riprel, 'adjustedDisp + 2', dataSize=4
-    zexti t2, t2, 23
+    zexti t2, t2, 23, dataSize=8
     wrbase tsg, t2
     wrlimit tsg, t1
 };
@@ -149,7 +149,7 @@ def macroop LIDT_16_M
     ld t1, seg, sib, disp, dataSize=2
     # Get the base
     ld t2, seg, sib, 'adjustedDisp + 2', dataSize=4
-    zexti t2, t2, 23
+    zexti t2, t2, 23, dataSize=8
     wrbase idtr, t2
     wrlimit idtr, t1
 };
@@ -163,7 +163,7 @@ def macroop LIDT_16_P
     ld t1, seg, riprel, disp, dataSize=2
     # Get the base
     ld t2, seg, riprel, 'adjustedDisp + 2', dataSize=4
-    zexti t2, t2, 23
+    zexti t2, t2, 23, dataSize=8
     wrbase idtr, t2
     wrlimit idtr, t1
 };

src/arch/x86/isa/microops/regop.isa

@@ -921,7 +921,7 @@ let {{
             '''
 
     class Zext(RegOp):
-        code = 'DestReg = bits(psrc1, op2, 0);'
+        code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);'
 
     class Rddr(RegOp):
         def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):