sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

ARM: Flesh out the 32 bit thumb store single instructions.

Browse source
This commit is contained in:
Gabe Black 2010-06-02 12:58:01 -05:00
parent 386424ccb5
commit 4ebd44dc4f
3 changed files with 28 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/arch/arm/isa/bitfields.isa
View file

@ -144,6 +144,7 @@ def bitfield HTOPCODE_8_7 htopcode8_7;
def bitfield HTOPCODE_8_6 htopcode8_6;
def bitfield HTOPCODE_8_5 htopcode8_5;
def bitfield HTOPCODE_7 htopcode7;
def bitfield HTOPCODE_7_5 htopcode7_5;
def bitfield HTOPCODE_6_5 htopcode6_5;
def bitfield HTOPCODE_5_4 htopcode5_4;
def bitfield HTOPCODE_4 htopcode4;

27
src/arch/arm/isa/thumbdecode.isa
View file

@ -388,7 +388,32 @@
0x3: decode HTOPCODE_10_9 {
0x0: decode HTOPCODE_4 {
0x0: decode HTOPCODE_8 {
0x0: WarnUnimpl::Store_single_data_item();
0x0: decode HTOPCODE_7_5 {
0x0: decode LTOPCODE_11_8 {
0x0: decode LTOPCODE_7_6 {
0x0: WarnUnimpl::strb(); // register
}
0x9, 0xb, 0xc, 0xd, 0xf: WarnUnimpl::strb(); // immediate thumb
0xe: WarnUnimpl::strbt();
}
0x1: decode LTOPCODE_11_8 {
0x0: decode LTOPCODE_7_6 {
0x0: WarnUnimpl::strh(); // register
}
0x9, 0xb, 0xc, 0xd, 0xf: WarnUnimpl::strh(); // immediate thumb
0xe: WarnUnimpl::strht();
}
0x2: decode LTOPCODE_11_8 {
0x0: decode LTOPCODE_7_6 {
0x0: WarnUnimpl::str(); // register
}
0x9, 0xb, 0xc, 0xd, 0xf: WarnUnimpl::str(); // immediate thumb
0xe: WarnUnimpl::strt();
}
0x4: WarnUnimpl::strb(); // immediate, thumb
0x5: WarnUnimpl::strh(); // immediate, thumb
0x6: WarnUnimpl::str(); // immediate, thumb
}
0x1: WarnUnimpl::Advanced_SIMD_or_structure_load_store();
}
0x1: decode HTOPCODE_6_5 {

1
src/arch/arm/types.hh
View file

@ -156,6 +156,7 @@ namespace ArmISA
Bitfield<24, 22> htopcode8_6;
Bitfield<24, 21> htopcode8_5;
Bitfield<23> htopcode7;
Bitfield<23, 21> htopcode7_5;
Bitfield<22, 21> htopcode6_5;
Bitfield<21, 20> htopcode5_4;
Bitfield<20> htopcode4;