i8254xGBe: major style overhaul.
Moved DescCache template functions from .hh to .cc file. Also fixed lots of line-wrapping problems, and some irregular indentation.
This commit is contained in:
Steve Reinhardt
parent
7b40c36fbd
commit
e7fa4f2f8e
2 changed files with 673 additions and 555 deletions
File diff suppressed because it is too large
Load diff
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@ -96,7 +96,8 @@ class IGbE : public EtherDevice
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// Event and function to deal with RDTR timer expiring
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void rdtrProcess() {
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rxDescCache.writeback(0);
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DPRINTF(EthernetIntr, "Posting RXT interrupt because RDTR timer expired\n");
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DPRINTF(EthernetIntr,
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"Posting RXT interrupt because RDTR timer expired\n");
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postInterrupt(iGbReg::IT_RXT);
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}
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@ -106,7 +107,8 @@ class IGbE : public EtherDevice
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// Event and function to deal with RADV timer expiring
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void radvProcess() {
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rxDescCache.writeback(0);
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DPRINTF(EthernetIntr, "Posting RXT interrupt because RADV timer expired\n");
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DPRINTF(EthernetIntr,
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"Posting RXT interrupt because RADV timer expired\n");
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postInterrupt(iGbReg::IT_RXT);
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}
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@ -116,7 +118,8 @@ class IGbE : public EtherDevice
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// Event and function to deal with TADV timer expiring
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void tadvProcess() {
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txDescCache.writeback(0);
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DPRINTF(EthernetIntr, "Posting TXDW interrupt because TADV timer expired\n");
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DPRINTF(EthernetIntr,
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"Posting TXDW interrupt because TADV timer expired\n");
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postInterrupt(iGbReg::IT_TXDW);
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}
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@ -126,7 +129,8 @@ class IGbE : public EtherDevice
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// Event and function to deal with TIDV timer expiring
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void tidvProcess() {
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txDescCache.writeback(0);
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DPRINTF(EthernetIntr, "Posting TXDW interrupt because TIDV timer expired\n");
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DPRINTF(EthernetIntr,
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"Posting TXDW interrupt because TIDV timer expired\n");
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postInterrupt(iGbReg::IT_TXDW);
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}
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//friend class EventWrapper<IGbE, &IGbE::tidvProcess>;
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@ -251,28 +255,19 @@ class IGbE : public EtherDevice
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// What the alignment is of the next descriptor writeback
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Addr wbAlignment;
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/** The packet that is currently being dmad to memory if any
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*/
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/** The packet that is currently being dmad to memory if any */
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EthPacketPtr pktPtr;
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/** Shortcut for DMA address translation */
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Addr pciToDma(Addr a) { return igbe->platform->pciToDma(a); }
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public:
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/** Annotate sm*/
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std::string annSmFetch, annSmWb, annUnusedDescQ, annUsedCacheQ,
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annUsedDescQ, annUnusedCacheQ, annDescQ;
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DescCache(IGbE *i, const std::string n, int s)
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: igbe(i), _name(n), cachePnt(0), size(s), curFetching(0), wbOut(0),
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pktPtr(NULL), wbDelayEvent(this), fetchDelayEvent(this),
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fetchEvent(this), wbEvent(this)
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{
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fetchBuf = new T[size];
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wbBuf = new T[size];
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}
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virtual ~DescCache()
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{
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reset();
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}
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DescCache(IGbE *i, const std::string n, int s);
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virtual ~DescCache();
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std::string name() { return _name; }
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@ -280,265 +275,27 @@ class IGbE : public EtherDevice
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* dirty that is very bad. This function checks that we don't and if we
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* do panics.
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*/
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void areaChanged()
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{
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if (usedCache.size() > 0 || curFetching || wbOut)
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panic("Descriptor Address, Length or Head changed. Bad\n");
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reset();
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void areaChanged();
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}
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void writeback(Addr aMask)
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{
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int curHead = descHead();
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int max_to_wb = usedCache.size();
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// Check if this writeback is less restrictive that the previous
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// and if so setup another one immediately following it
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if (wbOut) {
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if (aMask < wbAlignment) {
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moreToWb = true;
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wbAlignment = aMask;
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}
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DPRINTF(EthernetDesc, "Writing back already in process, returning\n");
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return;
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}
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moreToWb = false;
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wbAlignment = aMask;
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DPRINTF(EthernetDesc, "Writing back descriptors head: %d tail: "
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"%d len: %d cachePnt: %d max_to_wb: %d descleft: %d\n",
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curHead, descTail(), descLen(), cachePnt, max_to_wb,
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descLeft());
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if (max_to_wb + curHead >= descLen()) {
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max_to_wb = descLen() - curHead;
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moreToWb = true;
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// this is by definition aligned correctly
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} else if (wbAlignment != 0) {
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// align the wb point to the mask
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max_to_wb = max_to_wb & ~wbAlignment;
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}
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DPRINTF(EthernetDesc, "Writing back %d descriptors\n", max_to_wb);
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if (max_to_wb <= 0) {
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if (usedCache.size())
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igbe->anBegin(annSmWb, "Wait Alignment", CPA::FL_WAIT);
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else
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igbe->anWe(annSmWb, annUsedCacheQ);
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return;
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}
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wbOut = max_to_wb;
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assert(!wbDelayEvent.scheduled());
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igbe->schedule(wbDelayEvent, curTick + igbe->wbDelay);
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igbe->anBegin(annSmWb, "Prepare Writeback Desc");
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}
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void writeback1()
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{
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// If we're draining delay issuing this DMA
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if (igbe->getState() != SimObject::Running) {
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igbe->schedule(wbDelayEvent, curTick + igbe->wbDelay);
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return;
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}
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DPRINTF(EthernetDesc, "Begining DMA of %d descriptors\n", wbOut);
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for (int x = 0; x < wbOut; x++) {
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assert(usedCache.size());
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memcpy(&wbBuf[x], usedCache[x], sizeof(T));
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igbe->anPq(annSmWb, annUsedCacheQ);
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igbe->anPq(annSmWb, annDescQ);
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igbe->anQ(annSmWb, annUsedDescQ);
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}
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igbe->anBegin(annSmWb, "Writeback Desc DMA");
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assert(wbOut);
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igbe->dmaWrite(igbe->platform->pciToDma(descBase() + descHead() * sizeof(T)),
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wbOut * sizeof(T), &wbEvent, (uint8_t*)wbBuf,
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igbe->wbCompDelay);
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}
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void writeback(Addr aMask);
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void writeback1();
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EventWrapper<DescCache, &DescCache::writeback1> wbDelayEvent;
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/** Fetch a chunk of descriptors into the descriptor cache.
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* Calls fetchComplete when the memory system returns the data
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*/
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void fetchDescriptors()
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{
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size_t max_to_fetch;
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if (curFetching) {
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DPRINTF(EthernetDesc, "Currently fetching %d descriptors, returning\n", curFetching);
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return;
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}
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if (descTail() >= cachePnt)
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max_to_fetch = descTail() - cachePnt;
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else
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max_to_fetch = descLen() - cachePnt;
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size_t free_cache = size - usedCache.size() - unusedCache.size();
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if (!max_to_fetch)
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igbe->anWe(annSmFetch, annUnusedDescQ);
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else
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igbe->anPq(annSmFetch, annUnusedDescQ, max_to_fetch);
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if (max_to_fetch) {
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if (!free_cache)
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igbe->anWf(annSmFetch, annDescQ);
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else
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igbe->anRq(annSmFetch, annDescQ, free_cache);
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}
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max_to_fetch = std::min(max_to_fetch, free_cache);
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DPRINTF(EthernetDesc, "Fetching descriptors head: %d tail: "
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"%d len: %d cachePnt: %d max_to_fetch: %d descleft: %d\n",
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descHead(), descTail(), descLen(), cachePnt,
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max_to_fetch, descLeft());
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// Nothing to do
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if (max_to_fetch == 0)
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return;
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// So we don't have two descriptor fetches going on at once
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curFetching = max_to_fetch;
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assert(!fetchDelayEvent.scheduled());
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igbe->schedule(fetchDelayEvent, curTick + igbe->fetchDelay);
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igbe->anBegin(annSmFetch, "Prepare Fetch Desc");
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}
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void fetchDescriptors1()
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{
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// If we're draining delay issuing this DMA
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if (igbe->getState() != SimObject::Running) {
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igbe->schedule(fetchDelayEvent, curTick + igbe->fetchDelay);
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return;
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}
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igbe->anBegin(annSmFetch, "Fetch Desc");
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DPRINTF(EthernetDesc, "Fetching descriptors at %#x (%#x), size: %#x\n",
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descBase() + cachePnt * sizeof(T),
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igbe->platform->pciToDma(descBase() + cachePnt * sizeof(T)),
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curFetching * sizeof(T));
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assert(curFetching);
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igbe->dmaRead(igbe->platform->pciToDma(descBase() + cachePnt * sizeof(T)),
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curFetching * sizeof(T), &fetchEvent, (uint8_t*)fetchBuf,
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igbe->fetchCompDelay);
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}
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void fetchDescriptors();
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void fetchDescriptors1();
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EventWrapper<DescCache, &DescCache::fetchDescriptors1> fetchDelayEvent;
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/** Called by event when dma to read descriptors is completed
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*/
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void fetchComplete()
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{
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T *newDesc;
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igbe->anBegin(annSmFetch, "Fetch Complete");
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for (int x = 0; x < curFetching; x++) {
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newDesc = new T;
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memcpy(newDesc, &fetchBuf[x], sizeof(T));
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unusedCache.push_back(newDesc);
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igbe->anDq(annSmFetch, annUnusedDescQ);
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igbe->anQ(annSmFetch, annUnusedCacheQ);
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igbe->anQ(annSmFetch, annDescQ);
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}
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#ifndef NDEBUG
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int oldCp = cachePnt;
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#endif
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cachePnt += curFetching;
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assert(cachePnt <= descLen());
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if (cachePnt == descLen())
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cachePnt = 0;
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curFetching = 0;
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DPRINTF(EthernetDesc, "Fetching complete cachePnt %d -> %d\n",
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oldCp, cachePnt);
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if ((descTail() >= cachePnt ? (descTail() - cachePnt) : (descLen() -
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cachePnt)) == 0)
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{
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igbe->anWe(annSmFetch, annUnusedDescQ);
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} else if (!(size - usedCache.size() - unusedCache.size())) {
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igbe->anWf(annSmFetch, annDescQ);
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} else {
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igbe->anBegin(annSmFetch, "Wait", CPA::FL_WAIT);
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}
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enableSm();
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igbe->checkDrain();
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}
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void fetchComplete();
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EventWrapper<DescCache, &DescCache::fetchComplete> fetchEvent;
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/** Called by event when dma to writeback descriptors is completed
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*/
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void wbComplete()
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{
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igbe->anBegin(annSmWb, "Finish Writeback");
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long curHead = descHead();
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#ifndef NDEBUG
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long oldHead = curHead;
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#endif
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for (int x = 0; x < wbOut; x++) {
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assert(usedCache.size());
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delete usedCache[0];
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usedCache.pop_front();
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igbe->anDq(annSmWb, annUsedCacheQ);
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igbe->anDq(annSmWb, annDescQ);
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}
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curHead += wbOut;
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wbOut = 0;
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if (curHead >= descLen())
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curHead -= descLen();
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// Update the head
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updateHead(curHead);
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DPRINTF(EthernetDesc, "Writeback complete curHead %d -> %d\n",
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oldHead, curHead);
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// If we still have more to wb, call wb now
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actionAfterWb();
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if (moreToWb) {
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moreToWb = false;
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DPRINTF(EthernetDesc, "Writeback has more todo\n");
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writeback(wbAlignment);
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}
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if (!wbOut) {
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igbe->checkDrain();
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if (usedCache.size())
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igbe->anBegin(annSmWb, "Wait", CPA::FL_WAIT);
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else
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igbe->anWe(annSmWb, annUsedCacheQ);
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}
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fetchAfterWb();
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}
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void wbComplete();
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EventWrapper<DescCache, &DescCache::wbComplete> wbEvent;
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/* Return the number of descriptors left in the ring, so the device has
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@ -564,95 +321,16 @@ class IGbE : public EtherDevice
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/* Get into a state where the descriptor address/head/etc colud be
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* changed */
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void reset()
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{
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DPRINTF(EthernetDesc, "Reseting descriptor cache\n");
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for (int x = 0; x < usedCache.size(); x++)
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delete usedCache[x];
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for (int x = 0; x < unusedCache.size(); x++)
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delete unusedCache[x];
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void reset();
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usedCache.clear();
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unusedCache.clear();
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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cachePnt = 0;
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}
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virtual void serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(cachePnt);
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SERIALIZE_SCALAR(curFetching);
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SERIALIZE_SCALAR(wbOut);
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SERIALIZE_SCALAR(moreToWb);
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SERIALIZE_SCALAR(wbAlignment);
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int usedCacheSize = usedCache.size();
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SERIALIZE_SCALAR(usedCacheSize);
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for(int x = 0; x < usedCacheSize; x++) {
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arrayParamOut(os, csprintf("usedCache_%d", x),
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(uint8_t*)usedCache[x],sizeof(T));
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}
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int unusedCacheSize = unusedCache.size();
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SERIALIZE_SCALAR(unusedCacheSize);
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for(int x = 0; x < unusedCacheSize; x++) {
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arrayParamOut(os, csprintf("unusedCache_%d", x),
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(uint8_t*)unusedCache[x],sizeof(T));
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}
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Tick fetch_delay = 0, wb_delay = 0;
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if (fetchDelayEvent.scheduled())
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fetch_delay = fetchDelayEvent.when();
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SERIALIZE_SCALAR(fetch_delay);
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if (wbDelayEvent.scheduled())
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wb_delay = wbDelayEvent.when();
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SERIALIZE_SCALAR(wb_delay);
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}
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virtual void unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(cachePnt);
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UNSERIALIZE_SCALAR(curFetching);
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UNSERIALIZE_SCALAR(wbOut);
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UNSERIALIZE_SCALAR(moreToWb);
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UNSERIALIZE_SCALAR(wbAlignment);
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int usedCacheSize;
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UNSERIALIZE_SCALAR(usedCacheSize);
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T *temp;
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for(int x = 0; x < usedCacheSize; x++) {
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temp = new T;
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arrayParamIn(cp, section, csprintf("usedCache_%d", x),
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(uint8_t*)temp,sizeof(T));
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usedCache.push_back(temp);
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}
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int unusedCacheSize;
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UNSERIALIZE_SCALAR(unusedCacheSize);
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for(int x = 0; x < unusedCacheSize; x++) {
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temp = new T;
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arrayParamIn(cp, section, csprintf("unusedCache_%d", x),
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(uint8_t*)temp,sizeof(T));
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unusedCache.push_back(temp);
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}
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Tick fetch_delay = 0, wb_delay = 0;
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UNSERIALIZE_SCALAR(fetch_delay);
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UNSERIALIZE_SCALAR(wb_delay);
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if (fetch_delay)
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igbe->schedule(fetchDelayEvent, fetch_delay);
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if (wb_delay)
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igbe->schedule(wbDelayEvent, wb_delay);
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}
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virtual bool hasOutstandingEvents() {
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return wbEvent.scheduled() || fetchEvent.scheduled();
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}
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};
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};
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class RxDescCache : public DescCache<iGbReg::RxDesc>
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@ -674,7 +352,8 @@ class IGbE : public EtherDevice
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/** Variable to head with header/data completion events */
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int splitCount;
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/** Bytes of packet that have been copied, so we know when to set EOP */
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/** Bytes of packet that have been copied, so we know when to
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set EOP */
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int bytesCopied;
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public:
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@ -771,7 +450,7 @@ class IGbE : public EtherDevice
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* operations.
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*/
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int descInBlock(int num_desc) { return num_desc /
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igbe->cacheBlockSize() / sizeof(iGbReg::TxDesc); }
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igbe->cacheBlockSize() / sizeof(iGbReg::TxDesc); }
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/** Ask if the packet has been transfered so the state machine can give
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* it to the fifo.
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* @return packet available in descriptor cache
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@ -801,7 +480,8 @@ class IGbE : public EtherDevice
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void completionWriteback(Addr a, bool enabled) {
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DPRINTF(EthernetDesc, "Completion writeback Addr: %#x enabled: %d\n",
|
||||
DPRINTF(EthernetDesc,
|
||||
"Completion writeback Addr: %#x enabled: %d\n",
|
||||
a, enabled);
|
||||
completionAddress = a;
|
||||
completionEnabled = enabled;
|
||||
|
|
@ -809,7 +489,9 @@ class IGbE : public EtherDevice
|
|||
|
||||
virtual bool hasOutstandingEvents();
|
||||
|
||||
void nullCallback() { DPRINTF(EthernetDesc, "Completion writeback complete\n"); }
|
||||
void nullCallback() {
|
||||
DPRINTF(EthernetDesc, "Completion writeback complete\n");
|
||||
}
|
||||
EventWrapper<TxDescCache, &TxDescCache::nullCallback> nullEvent;
|
||||
|
||||
virtual void serialize(std::ostream &os);
|
||||
|
|
@ -823,10 +505,10 @@ class IGbE : public EtherDevice
|
|||
public:
|
||||
typedef IGbEParams Params;
|
||||
const Params *
|
||||
params() const
|
||||
{
|
||||
params() const {
|
||||
return dynamic_cast<const Params *>(_params);
|
||||
}
|
||||
|
||||
IGbE(const Params *params);
|
||||
~IGbE() {}
|
||||
virtual void init();
|
||||
|
|
|
|||
Loading…
Reference in a new issue