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inorder-miscregs: Fix indexing for misc. reg operands and update result-types for better tracing of these types of values

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This commit is contained in:
Korey Sewell 2009-05-12 15:01:14 -04:00
parent 2012202b06
commit 98b1452058
6 changed files with 115 additions and 47 deletions
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1
src/cpu/inorder/cpu.hh
View file

@ -247,6 +247,7 @@ class InOrderCPU : public BaseCPU
/** The Pipeline Stages for the CPU */
PipelineStage *pipelineStage[ThePipeline::NumStages];
/** Program Counters */
TheISA::IntReg PC[ThePipeline::MaxThreads];
TheISA::IntReg nextPC[ThePipeline::MaxThreads];
TheISA::IntReg nextNPC[ThePipeline::MaxThreads];

63
src/cpu/inorder/inorder_dyn_inst.cc
View file

@ -359,7 +359,7 @@ void
InOrderDynInst::setFloatSrc(int idx, FloatReg val, int width)
{
if (width == 32)
instSrc[idx].fp = val;
instSrc[idx].dbl = val;
else if (width == 64)
instSrc[idx].dbl = val;
else
@ -386,7 +386,14 @@ InOrderDynInst::readIntRegOperand(const StaticInst *si, int idx, unsigned tid)
FloatReg
InOrderDynInst::readFloatRegOperand(const StaticInst *si, int idx, int width)
{
return instSrc[idx].fp;
if (width == 32)
return (float)instSrc[idx].dbl;
else if (width == 64)
return instSrc[idx].dbl;
else {
panic("Unsupported Floating Point Width!");
return 0;
}
}
@ -417,8 +424,10 @@ InOrderDynInst::readMiscRegNoEffect(int misc_reg)
MiscReg
InOrderDynInst::readMiscRegOperandNoEffect(const StaticInst *si, int idx)
{
int reg = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return cpu->readMiscRegNoEffect(reg, this->threadNumber);
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Misc. Reg Source Value %i"
" read as %#x.\n", threadNumber, seqNum, idx,
instSrc[idx].integer);
return instSrc[idx].integer;
}
/** Reads a misc. register, including any side-effects the read
@ -427,20 +436,23 @@ InOrderDynInst::readMiscRegOperandNoEffect(const StaticInst *si, int idx)
MiscReg
InOrderDynInst::readMiscRegOperand(const StaticInst *si, int idx)
{
int reg = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return this->cpu->readMiscReg(reg, this->threadNumber);
// For In-Order, the side-effect of reading a register happens
// when explicitly executing a "ReadSrc" command. This simply returns
// a value.
return readMiscRegOperandNoEffect(si, idx);
}
/** Sets a misc. register. */
void
InOrderDynInst::setMiscRegOperandNoEffect(const StaticInst * si, int idx, const MiscReg &val)
InOrderDynInst::setMiscRegOperandNoEffect(const StaticInst * si, int idx,
const MiscReg &val)
{
instResult[si->destRegIdx(idx)].val.integer = val;
instResult[si->destRegIdx(idx)].tick = curTick;
instResult[idx].type = Integer;
instResult[idx].val.integer = val;
instResult[idx].tick = curTick;
this->cpu->setMiscRegNoEffect(
si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
val, this->threadNumber);
DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting Misc Reg. Operand %i "
"being set to %#x.\n", threadNumber, seqNum, idx, val);
}
/** Sets a misc. register, including any side-effects the write
@ -450,12 +462,10 @@ void
InOrderDynInst::setMiscRegOperand(const StaticInst *si, int idx,
const MiscReg &val)
{
instResult[si->destRegIdx(idx)].val.integer = val;
instResult[si->destRegIdx(idx)].tick = curTick;
this->cpu->setMiscReg(
si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag,
val, this->threadNumber);
// For In-Order, the side-effect of setting a register happens
// when explicitly writing back the register value. This
// simply maintains the operand value.
setMiscRegOperandNoEffect(si, idx, val);
}
MiscReg
@ -480,6 +490,7 @@ InOrderDynInst::readRegOtherThread(unsigned reg_idx, int tid)
void
InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val)
{
instResult[idx].type = Integer;
instResult[idx].val.integer = val;
instResult[idx].tick = curTick;
}
@ -488,12 +499,15 @@ InOrderDynInst::setIntRegOperand(const StaticInst *si, int idx, IntReg val)
void
InOrderDynInst::setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, int width)
{
if (width == 32)
instResult[idx].val.fp = val;
else if (width == 64)
if (width == 32) {
instResult[idx].val.dbl = (float)val;
instResult[idx].type = Float;
} else if (width == 64) {
instResult[idx].val.dbl = val;
else
instResult[idx].type = Double;
} else {
panic("Unsupported Floating Point Width!");
}
instResult[idx].tick = curTick;
}
@ -503,6 +517,11 @@ void
InOrderDynInst::setFloatRegOperandBits(const StaticInst *si, int idx,
FloatRegBits val, int width)
{
if (width == 32)
instResult[idx].type = Float;
else if (width == 64)
instResult[idx].type = Double;
instResult[idx].val.integer = val;
instResult[idx].tick = curTick;
}

46
src/cpu/inorder/inorder_dyn_inst.hh
View file

@ -226,14 +226,27 @@ class InOrderDynInst : public FastAlloc, public RefCounted
/** An instruction src/dest has to be one of these types */
union InstValue {
uint64_t integer;
float fp;
double dbl;
};
//@TODO: Naming Convention for Enums?
enum ResultType {
None,
Integer,
Float,
Double
};
/** Result of an instruction execution */
struct InstResult {
ResultType type;
InstValue val;
Tick tick;
InstResult()
: type(None), tick(0)
{}
};
/** The source of the instruction; assumes for now that there's only one
@ -315,6 +328,9 @@ class InOrderDynInst : public FastAlloc, public RefCounted
// BASE INSTRUCTION INFORMATION.
//
////////////////////////////////////////////////////////////
std::string instName() { return staticInst->getName(); }
void setMachInst(ExtMachInst inst);
/** Sets the StaticInst. */
@ -827,9 +843,31 @@ class InOrderDynInst : public FastAlloc, public RefCounted
MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx);
/** Returns the result value instruction. */
uint64_t readIntResult(int idx) { return instResult[idx].val.integer; }
float readFloatResult(int idx) { return instResult[idx].val.fp; }
double readDoubleResult(int idx) { return instResult[idx].val.dbl; }
ResultType resultType(int idx)
{
return instResult[idx].type;
}
uint64_t readIntResult(int idx)
{
return instResult[idx].val.integer;
}
/** Depending on type, return Float or Double */
double readFloatResult(int idx)
{
//assert(instResult[idx].type != Integer && instResult[idx].type != None);
//@todo: TypeCast FLOAT onto DOUBLE instead of separate value
return (instResult[idx].type == Float) ?
(float) instResult[idx].val.dbl : instResult[idx].val.dbl;
}
double readDoubleResult(int idx)
{
assert(instResult[idx].type == Double);
return instResult[idx].val.dbl;
}
Tick readResultTime(int idx) { return instResult[idx].tick; }
uint64_t* getIntResultPtr(int idx) { return &instResult[idx].val.integer; }

5
src/cpu/inorder/resources/cache_unit.cc
View file

@ -483,6 +483,9 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
DPRINTF(InOrderCachePort,
"[tid:%u]: [sn:%i]: Data loaded was: %08p\n",
tid, inst->seqNum, inst->readIntResult(0));
DPRINTF(InOrderCachePort,
"[tid:%u]: [sn:%i]: FP Data loaded was: %08p\n",
tid, inst->seqNum, inst->readFloatResult(0));
} else if(inst->isStore()) {
assert(cache_pkt->isWrite());
@ -594,7 +597,7 @@ CacheUnit::getMemData(Packet *packet)
case 32:
return packet->get<uint32_t>();
case 864:
case 64:
return packet->get<uint64_t>();
default:

15
src/cpu/inorder/resources/execution_unit.cc
View file

@ -68,8 +68,8 @@ ExecutionUnit::execute(int slot_num)
exec_req->fault = NoFault;
DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%#x] .\n",
tid, seq_num, inst->readPC());
DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%#x] %s.\n",
tid, seq_num, inst->readPC(), inst->instName());
switch (exec_req->cmd)
{
@ -163,11 +163,9 @@ ExecutionUnit::execute(int slot_num)
}
} else {
DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Prediction Correct.\n",
inst->readTid(), seq_num, inst->readIntResult(0));
inst->readTid(), seq_num);
}
DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result of execution is 0x%x.\n",
inst->readTid(), seq_num, inst->readIntResult(0));
exec_req->done();
} else {
warn("inst [sn:%i] had a %s fault", seq_num, fault->name());
@ -178,10 +176,13 @@ ExecutionUnit::execute(int slot_num)
if (fault == NoFault) {
inst->setExecuted();
exec_req->done();
DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: The result of execution is 0x%x.\n",
inst->readTid(), seq_num, inst->readIntResult(0));
inst->readTid(), seq_num, (inst->resultType(0) == InOrderDynInst::Float) ?
inst->readFloatResult(0) : (inst->resultType(0) == InOrderDynInst::Double) ?
inst->readDoubleResult(0) : inst->readIntResult(0));
exec_req->done();
} else {
warn("inst [sn:%i] had a %s fault", seq_num, fault->name());
cpu->trap(fault, tid);

32
src/cpu/inorder/resources/use_def.cc
View file

@ -119,28 +119,28 @@ UseDefUnit::execute(int slot_idx)
{
int reg_idx = inst->_srcRegIdx[ud_idx];
DPRINTF(InOrderUseDef, "[tid:%i]: Attempting to read source register idx %i.\n",
tid, ud_idx);
DPRINTF(InOrderUseDef, "[tid:%i]: Attempting to read source register idx %i (reg #%i).\n",
tid, ud_idx, reg_idx);
// Ask register dependency map if it is OK to read from Arch. Reg. File
if (regDepMap[tid]->canRead(reg_idx, inst)) {
// Read From Register File
if (inst->seqNum <= outReadSeqNum[tid]) {
if (reg_idx <= FP_Base_DepTag) {
DPRINTF(InOrderUseDef, "[tid:%i]: Reading Int Reg %i from Register File.\n",
tid, reg_idx);
DPRINTF(InOrderUseDef, "[tid:%i]: Reading Int Reg %i from Register File:%i.\n",
tid, reg_idx, cpu->readIntReg(reg_idx,inst->readTid()));
inst->setIntSrc(ud_idx,
cpu->readIntReg(reg_idx,inst->readTid()));
} else if (reg_idx <= Ctrl_Base_DepTag) {
reg_idx -= FP_Base_DepTag;
DPRINTF(InOrderUseDef, "[tid:%i]: Reading Float Reg %i from Register File.\n",
tid, reg_idx);
DPRINTF(InOrderUseDef, "[tid:%i]: Reading Float Reg %i from Register File:%x.\n",
tid, reg_idx, cpu->readFloatRegBits(reg_idx, inst->readTid()));
inst->setIntSrc(ud_idx, // Always Read FloatRegBits For Now
cpu->readFloatRegBits(reg_idx, inst->readTid()));
} else {
reg_idx -= Ctrl_Base_DepTag;
DPRINTF(InOrderUseDef, "[tid:%i]: Reading Misc Reg %i from Register File.\n",
tid, reg_idx);
DPRINTF(InOrderUseDef, "[tid:%i]: Reading Misc Reg %i from Register File:%i.\n",
tid, reg_idx, cpu->readMiscReg(reg_idx, inst->readTid()));
inst->setIntSrc(ud_idx,
cpu->readMiscReg(reg_idx, inst->readTid()));
}
@ -208,12 +208,12 @@ UseDefUnit::execute(int slot_idx)
int reg_idx = inst->_destRegIdx[ud_idx];
if (regDepMap[tid]->canWrite(reg_idx, inst)) {
DPRINTF(InOrderUseDef, "[tid:%i]: Attempting to write to Register File.\n",
tid);
DPRINTF(InOrderUseDef, "[tid:%i]: Flattening register idx %i & Attempting to write to Register File.\n",
tid, reg_idx);
if (inst->seqNum <= outReadSeqNum[tid]) {
if (reg_idx <= FP_Base_DepTag) {
DPRINTF(InOrderUseDef, "[tid:%i]: Writing 0x%x to register idx %i.\n",
DPRINTF(InOrderUseDef, "[tid:%i]: Writing Int. Result 0x%x to register idx %i.\n",
tid, inst->readIntResult(ud_idx), reg_idx);
// Remove Dependencies
@ -223,6 +223,8 @@ UseDefUnit::execute(int slot_idx)
inst->readIntResult(ud_idx),
inst->readTid());
} else if(reg_idx <= Ctrl_Base_DepTag) {
DPRINTF(InOrderUseDef, "[tid:%i]: Writing FP Result 0x%x (bits:0x%x) to register idx %i.\n",
tid, inst->readFloatResult(ud_idx), inst->readIntResult(ud_idx), reg_idx);
// Remove Dependencies
regDepMap[tid]->removeFront(reg_idx, inst);
@ -233,13 +235,17 @@ UseDefUnit::execute(int slot_idx)
inst->readFloatResult(ud_idx),
inst->readTid());
} else {
DPRINTF(InOrderUseDef, "[tid:%i]: Writing Misc. 0x%x to register idx %i.\n",
tid, inst->readIntResult(ud_idx), reg_idx);
// Remove Dependencies
regDepMap[tid]->removeFront(reg_idx, inst);
reg_idx -= Ctrl_Base_DepTag;
cpu->setMiscReg(reg_idx,
inst->readIntResult(ud_idx),
inst->readTid());
inst->readIntResult(ud_idx),
inst->readTid());
}
outWriteSeqNum[tid] = maxSeqNum;