configs/inorder: add options for switch-on-miss to inorder cpu
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3 changed files with 24 additions and 2 deletions
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@ -30,10 +30,15 @@ from m5.params import *
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from m5.proxy import *
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from BaseCPU import BaseCPU
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class ThreadModel(Enum):
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vals = ['Single', 'SMT', 'SwitchOnCacheMiss']
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class InOrderCPU(BaseCPU):
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type = 'InOrderCPU'
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activity = Param.Unsigned(0, "Initial count")
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threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)")
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cachePorts = Param.Unsigned(2, "Cache Ports")
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stageWidth = Param.Unsigned(1, "Stage width")
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@ -197,7 +197,7 @@ InOrderCPU::InOrderCPU(Params *params)
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deferRegistration(false/*params->deferRegistration*/),
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stageTracing(params->stageTracing),
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numVirtProcs(1)
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{
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{
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ThreadID active_threads;
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cpu_params = params;
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@ -216,6 +216,15 @@ InOrderCPU::InOrderCPU(Params *params)
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"in your InOrder implementation or "
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"edit your workload size.");
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}
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if (active_threads > 1) {
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threadModel = (InOrderCPU::ThreadModel) params->threadModel;
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} else {
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threadModel = Single;
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}
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#endif
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// Bind the fetch & data ports from the resource pool.
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@ -100,6 +100,15 @@ class InOrderCPU : public BaseCPU
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/** Type of core that this is */
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std::string coreType;
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// Only need for SE MODE
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enum ThreadModel {
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Single,
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SMT,
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SwitchOnCacheMiss
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};
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ThreadModel threadModel;
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int readCpuId() { return cpu_id; }
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void setCpuId(int val) { cpu_id = val; }
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@ -117,7 +126,6 @@ class InOrderCPU : public BaseCPU
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/** Overall CPU status. */
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Status _status;
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private:
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/** Define TickEvent for the CPU */
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class TickEvent : public Event
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