sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

X86: (Re)Implemented SHRD.

Browse source
This commit is contained in:
Gabe Black 2009-08-07 10:13:33 -07:00
parent 4f5270f946
commit 7c606e3835
2 changed files with 32 additions and 21 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/arch/x86/isa/decoder/two_byte_opcodes.isa
View file

@ -831,7 +831,7 @@
0x2: rsm_smm();
0x3: Inst::BTS(Ev,Gv);
0x4: Inst::SHRD(Ev,Gv,Ib);
0x5: shrd_Ev_Gv_rCl();
0x5: Inst::SHRD(Ev,Gv);
//0x6: group16();
0x6: decode MODRM_REG {
0x0: fxsave();

51
src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py
View file

@ -220,38 +220,49 @@ def macroop SHR_P_R
st t1, seg, riprel, disp
};
# SHRD will not set OF correctly when the shift count is 1.
def macroop SHRD_R_R_I
def macroop SHRD_R_R
{
srli t1, reg, imm, flags=(CF,)
rori t2, regm, imm
srli t3, regm, imm
xor t2, t2, t3
or reg, t1, t2
mdbi regm, 0
srd reg, reg, rcx, flags=(CF,OF,SF,ZF,PF)
};
# SHRD will not set OF correctly when the shift count is 1.
def macroop SHRD_M_R_I
def macroop SHRD_M_R
{
ldst t1, seg, sib, disp
srli t1, t1, imm, flags=(CF,)
rori t2, reg, imm
srli t3, reg, imm
xor t2, t2, t3
or t1, t1, t2
mdbi reg, 0
srd t1, t1, rcx, flags=(CF,OF,SF,ZF,PF)
st t1, seg, sib, disp
};
def macroop SHRD_P_R
{
rdip t7
ldst t1, seg, riprel, disp
mdbi reg, 0
srd t1, t1, rcx, flags=(CF,OF,SF,ZF,PF)
st t1, seg, riprel, disp
};
def macroop SHRD_R_R_I
{
mdbi regm, 0
srdi reg, reg, imm, flags=(CF,OF,SF,ZF,PF)
};
def macroop SHRD_M_R_I
{
ldst t1, seg, sib, disp
mdbi reg, 0
srdi t1, t1, imm, flags=(CF,OF,SF,ZF,PF)
st t1, seg, sib, disp
};
# SHRD will not set OF correctly when the shift count is 1.
def macroop SHRD_P_R_I
{
rdip t7
ldst t1, seg, riprel, disp
srli t1, t1, imm, flags=(CF,)
rori t2, reg, imm
srli t3, reg, imm
xor t2, t2, t3
or t1, t1, t2
mdbi reg, 0
srdi t1, t1, imm, flags=(CF,OF,SF,ZF,PF)
st t1, seg, riprel, disp
};