inorder-mdu: multiplier latency fix
mdu was workign incorrectly for 4+ latency due to incorrectly assuming multiply was finished the next stage
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@ -91,7 +91,32 @@ MultDivUnit::freeSlot(int slot_idx)
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Resource::freeSlot(slot_idx);
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}
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//@TODO: Should we push this behavior into base-class to generically
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// accomodate all multicyle resources?
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void
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MultDivUnit::requestAgain(DynInstPtr inst, bool &service_request)
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{
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ResReqPtr mult_div_req = findRequest(inst);
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assert(mult_div_req);
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service_request = true;
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// Check to see if this instruction is requesting the same command
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// or a different one
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if (mult_div_req->cmd != inst->resSched.top()->cmd) {
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// If different, then update command in the request
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mult_div_req->cmd = inst->resSched.top()->cmd;
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DPRINTF(InOrderMDU,
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"[tid:%i]: [sn:%i]: Updating the command for this instruction\n",
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inst->readTid(), inst->seqNum);
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} else {
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// If same command, just check to see if memory access was completed
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// but dont try to re-execute
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DPRINTF(InOrderMDU,
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"[tid:%i]: [sn:%i]: requesting this resource again\n",
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inst->readTid(), inst->seqNum);
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}
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}
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int
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MultDivUnit::getSlot(DynInstPtr inst)
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{
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@ -232,8 +257,13 @@ MultDivUnit::execute(int slot_num)
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// counting down the time
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{
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DPRINTF(InOrderMDU, "End MDU called ...\n");
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if (mult_div_req->getInst()->isExecuted())
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if (mult_div_req->getInst()->isExecuted()) {
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DPRINTF(InOrderMDU, "Mult/Div finished.\n");
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mult_div_req->done();
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} else {
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mult_div_req->setCompleted(false);
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}
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}
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break;
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@ -82,6 +82,8 @@ class MultDivUnit : public Resource {
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/** Register extra resource stats */
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virtual void regStats();
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void requestAgain(DynInstPtr inst, bool &try_request);
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protected:
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/** Latency & Repeat Rate for Multiply Insts */
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unsigned multRepeatRate;
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