sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

ARM: Get rid of unnecessary Re operand.

Browse source
This commit is contained in:
Gabe Black 2009-06-21 09:48:44 -07:00
parent 7d4ef8a398
commit 4415e2dcd6
2 changed files with 0 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/arch/arm/isa/bitfields.isa
View file

@ -70,8 +70,6 @@ def bitfield SHIFT_SIZE <11: 7>;
def bitfield SHIFT < 6: 5>;
def bitfield RM < 3: 0>;
def bitfield RE <20:16>;
def bitfield RS <11: 8>;
def bitfield RDUP <19:16>;

1
src/arch/arm/isa/operands.isa
View file

@ -46,7 +46,6 @@ def operands {{
'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2),
'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3),
'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4),
'Re': ('IntReg', 'uw', 'RE', 'IsInteger', 5),
'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 5),
'R0': ('IntReg', 'uw', '0', 'IsInteger', 5),