sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

merge

Browse source
This commit is contained in:
Derek Hower 2009-07-20 09:41:28 -05:00
commit 225de2eaff
15 changed files with 590 additions and 294 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/arch/sparc/SConscript
View file

@ -35,11 +35,14 @@ if env['TARGET_ISA'] == 'sparc':
Source('asi.cc')
Source('faults.cc')
Source('isa.cc')
Source('nativetrace.cc')
Source('pagetable.cc')
Source('remote_gdb.cc')
Source('tlb.cc')
Source('utility.cc')
SimObject('SparcNativeTrace.py')
SimObject('SparcTLB.py')
TraceFlag('Sparc', "Generic SPARC ISA stuff")
TraceFlag('RegisterWindows', "Register window manipulation")

35
src/arch/sparc/SparcNativeTrace.py Normal file
View file

@ -0,0 +1,35 @@
# Copyright (c) 2009 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
from m5.SimObject import SimObject
from m5.params import *
from NativeTrace import NativeTrace
class SparcNativeTrace(NativeTrace):
type = 'SparcNativeTrace'
cxx_class = 'Trace::SparcNativeTrace'

98
src/arch/sparc/nativetrace.cc Normal file
View file

@ -0,0 +1,98 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/sparc/isa_traits.hh"
#include "arch/sparc/registers.hh"
#include "arch/sparc/nativetrace.hh"
#include "cpu/thread_context.hh"
#include "params/SparcNativeTrace.hh"
namespace Trace {
static char *intRegNames[SparcISA::NumIntArchRegs] = {
//Global registers
"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
//Output registers
"o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
//Local registers
"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
//Input registers
"i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
};
void
Trace::SparcNativeTrace::check(NativeTraceRecord *record)
{
ThreadContext *tc = record->getThread();
uint64_t regVal, realRegVal;
// Integer registers
// I doubt a real SPARC will describe more integer registers than this.
assert(SparcISA::NumIntArchRegs == 32);
char **regName = intRegNames;
for (int i = 0; i < SparcISA::NumIntArchRegs; i++) {
regVal = tc->readIntReg(i);
read(&realRegVal, sizeof(realRegVal));
realRegVal = SparcISA::gtoh(realRegVal);
checkReg(*(regName++), regVal, realRegVal);
}
// PC
read(&realRegVal, sizeof(realRegVal));
realRegVal = SparcISA::gtoh(realRegVal);
regVal = tc->readNextPC();
checkReg("pc", regVal, realRegVal);
// NPC
read(&realRegVal, sizeof(realRegVal));
realRegVal = SparcISA::gtoh(realRegVal);
regVal = tc->readNextNPC();
checkReg("npc", regVal, realRegVal);
// CCR
read(&realRegVal, sizeof(realRegVal));
realRegVal = SparcISA::gtoh(realRegVal);
regVal = tc->readIntReg(SparcISA::NumIntArchRegs + 2);
checkReg("ccr", regVal, realRegVal);
}
} /* namespace Trace */
////////////////////////////////////////////////////////////////////////
//
// ExeTracer Simulation Object
//
Trace::SparcNativeTrace *
SparcNativeTraceParams::create()
{
return new Trace::SparcNativeTrace(this);
};

52
src/arch/sparc/nativetrace.hh Normal file
View file

@ -0,0 +1,52 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_SPARC_NATIVETRACE_HH__
#define __ARCH_SPARC_NATIVETRACE_HH__
#include "base/types.hh"
#include "cpu/nativetrace.hh"
class ThreadContext;
namespace Trace {
class SparcNativeTrace : public NativeTrace
{
public:
SparcNativeTrace(const Params *p) : NativeTrace(p)
{}
void check(NativeTraceRecord *record);
};
} /* namespace Trace */
#endif // __CPU_NATIVETRACE_HH__

3
src/arch/x86/SConscript
View file

@ -95,6 +95,7 @@ if env['TARGET_ISA'] == 'x86':
Source('insts/microregop.cc')
Source('insts/static_inst.cc')
Source('isa.cc')
Source('nativetrace.cc')
Source('pagetable.cc')
Source('predecoder.cc')
Source('predecoder_tables.cc')
@ -102,6 +103,8 @@ if env['TARGET_ISA'] == 'x86':
Source('tlb.cc')
Source('utility.cc')
SimObject('X86NativeTrace.py')
SimObject('X86TLB.py')
TraceFlag('Predecoder', "Predecoder debug output")
TraceFlag('X86', "Generic X86 ISA debugging")

35
src/arch/x86/X86NativeTrace.py Normal file
View file

@ -0,0 +1,35 @@
# Copyright (c) 2009 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
from m5.SimObject import SimObject
from m5.params import *
from NativeTrace import NativeTrace
class X86NativeTrace(NativeTrace):
type = 'X86NativeTrace'
cxx_class = 'Trace::X86NativeTrace'

11
src/arch/x86/miscregs.hh
View file

@ -374,6 +374,17 @@ namespace X86ISA
MISCREG_X87_TOP =
MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS,
MISCREG_MXCSR,
MISCREG_FCW,
MISCREG_FSW,
MISCREG_FTW,
MISCREG_FTAG,
MISCREG_FISEG,
MISCREG_FIOFF,
MISCREG_FOSEG,
MISCREG_FOOFF,
MISCREG_FOP,
//XXX Add "Model-Specific Registers"
MISCREG_APIC_BASE,

198
src/arch/x86/nativetrace.cc Normal file
View file

@ -0,0 +1,198 @@
/*
* Copyright (c) 2007-2009 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/x86/isa_traits.hh"
#include "arch/x86/floatregs.hh"
#include "arch/x86/intregs.hh"
#include "arch/x86/nativetrace.hh"
#include "cpu/thread_context.hh"
#include "params/X86NativeTrace.hh"
namespace Trace {
void
X86NativeTrace::ThreadState::update(NativeTrace *parent)
{
parent->read(this, sizeof(*this));
rax = X86ISA::gtoh(rax);
rcx = X86ISA::gtoh(rcx);
rdx = X86ISA::gtoh(rdx);
rbx = X86ISA::gtoh(rbx);
rsp = X86ISA::gtoh(rsp);
rbp = X86ISA::gtoh(rbp);
rsi = X86ISA::gtoh(rsi);
rdi = X86ISA::gtoh(rdi);
r8 = X86ISA::gtoh(r8);
r9 = X86ISA::gtoh(r9);
r10 = X86ISA::gtoh(r10);
r11 = X86ISA::gtoh(r11);
r12 = X86ISA::gtoh(r12);
r13 = X86ISA::gtoh(r13);
r14 = X86ISA::gtoh(r14);
r15 = X86ISA::gtoh(r15);
rip = X86ISA::gtoh(rip);
//This should be expanded if x87 registers are considered
for (int i = 0; i < 8; i++)
mmx[i] = X86ISA::gtoh(mmx[i]);
for (int i = 0; i < 32; i++)
xmm[i] = X86ISA::gtoh(xmm[i]);
}
void
X86NativeTrace::ThreadState::update(ThreadContext *tc)
{
rax = tc->readIntReg(X86ISA::INTREG_RAX);
rcx = tc->readIntReg(X86ISA::INTREG_RCX);
rdx = tc->readIntReg(X86ISA::INTREG_RDX);
rbx = tc->readIntReg(X86ISA::INTREG_RBX);
rsp = tc->readIntReg(X86ISA::INTREG_RSP);
rbp = tc->readIntReg(X86ISA::INTREG_RBP);
rsi = tc->readIntReg(X86ISA::INTREG_RSI);
rdi = tc->readIntReg(X86ISA::INTREG_RDI);
r8 = tc->readIntReg(X86ISA::INTREG_R8);
r9 = tc->readIntReg(X86ISA::INTREG_R9);
r10 = tc->readIntReg(X86ISA::INTREG_R10);
r11 = tc->readIntReg(X86ISA::INTREG_R11);
r12 = tc->readIntReg(X86ISA::INTREG_R12);
r13 = tc->readIntReg(X86ISA::INTREG_R13);
r14 = tc->readIntReg(X86ISA::INTREG_R14);
r15 = tc->readIntReg(X86ISA::INTREG_R15);
rip = tc->readNextPC();
//This should be expanded if x87 registers are considered
for (int i = 0; i < 8; i++)
mmx[i] = tc->readFloatRegBits(X86ISA::FLOATREG_MMX(i));
for (int i = 0; i < 32; i++)
xmm[i] = tc->readFloatRegBits(X86ISA::FLOATREG_XMM_BASE + i);
}
X86NativeTrace::X86NativeTrace(const Params *p)
: NativeTrace(p)
{
checkRcx = true;
checkR11 = true;
}
bool
X86NativeTrace::checkRcxReg(const char * name, uint64_t &mVal, uint64_t &nVal)
{
if(!checkRcx)
checkRcx = (mVal != oldRcxVal || nVal != oldRealRcxVal);
if(checkRcx)
return checkReg(name, mVal, nVal);
return true;
}
bool
X86NativeTrace::checkR11Reg(const char * name, uint64_t &mVal, uint64_t &nVal)
{
if(!checkR11)
checkR11 = (mVal != oldR11Val || nVal != oldRealR11Val);
if(checkR11)
return checkReg(name, mVal, nVal);
return true;
}
bool
X86NativeTrace::checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[])
{
if (mXmmBuf[num * 2] != nXmmBuf[num * 2] ||
mXmmBuf[num * 2 + 1] != nXmmBuf[num * 2 + 1]) {
DPRINTF(ExecRegDelta,
"Register xmm%d should be 0x%016x%016x but is 0x%016x%016x.\n",
num, nXmmBuf[num * 2 + 1], nXmmBuf[num * 2],
mXmmBuf[num * 2 + 1], mXmmBuf[num * 2]);
return false;
}
return true;
}
void
X86NativeTrace::check(NativeTraceRecord *record)
{
nState.update(this);
mState.update(record->getThread());
if(record->getStaticInst()->isSyscall())
{
checkRcx = false;
checkR11 = false;
oldRcxVal = mState.rcx;
oldRealRcxVal = nState.rcx;
oldR11Val = mState.r11;
oldRealR11Val = nState.r11;
}
checkReg("rax", mState.rax, nState.rax);
checkRcxReg("rcx", mState.rcx, nState.rcx);
checkReg("rdx", mState.rdx, nState.rdx);
checkReg("rbx", mState.rbx, nState.rbx);
checkReg("rsp", mState.rsp, nState.rsp);
checkReg("rbp", mState.rbp, nState.rbp);
checkReg("rsi", mState.rsi, nState.rsi);
checkReg("rdi", mState.rdi, nState.rdi);
checkReg("r8", mState.r8, nState.r8);
checkReg("r9", mState.r9, nState.r9);
checkReg("r10", mState.r10, nState.r10);
checkR11Reg("r11", mState.r11, nState.r11);
checkReg("r12", mState.r12, nState.r12);
checkReg("r13", mState.r13, nState.r13);
checkReg("r14", mState.r14, nState.r14);
checkReg("r15", mState.r15, nState.r15);
checkReg("rip", mState.rip, nState.rip);
checkXMM(0, mState.xmm, nState.xmm);
checkXMM(1, mState.xmm, nState.xmm);
checkXMM(2, mState.xmm, nState.xmm);
checkXMM(3, mState.xmm, nState.xmm);
checkXMM(4, mState.xmm, nState.xmm);
checkXMM(5, mState.xmm, nState.xmm);
checkXMM(6, mState.xmm, nState.xmm);
checkXMM(7, mState.xmm, nState.xmm);
checkXMM(8, mState.xmm, nState.xmm);
checkXMM(9, mState.xmm, nState.xmm);
checkXMM(10, mState.xmm, nState.xmm);
checkXMM(11, mState.xmm, nState.xmm);
checkXMM(12, mState.xmm, nState.xmm);
checkXMM(13, mState.xmm, nState.xmm);
checkXMM(14, mState.xmm, nState.xmm);
checkXMM(15, mState.xmm, nState.xmm);
}
} /* namespace Trace */
////////////////////////////////////////////////////////////////////////
//
// ExeTracer Simulation Object
//
Trace::X86NativeTrace *
X86NativeTraceParams::create()
{
return new Trace::X86NativeTrace(this);
};

90
src/arch/x86/nativetrace.hh Normal file
View file

@ -0,0 +1,90 @@
/*
* Copyright (c) 2007-2009 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#ifndef __ARCH_X86_NATIVETRACE_HH__
#define __ARCH_X86_NATIVETRACE_HH__
#include "base/types.hh"
#include "cpu/nativetrace.hh"
class ThreadContext;
namespace Trace {
class X86NativeTrace : public NativeTrace
{
protected:
bool checkRcx;
bool checkR11;
uint64_t oldRcxVal, oldR11Val;
uint64_t oldRealRcxVal, oldRealR11Val;
struct ThreadState {
uint64_t rax;
uint64_t rcx;
uint64_t rdx;
uint64_t rbx;
uint64_t rsp;
uint64_t rbp;
uint64_t rsi;
uint64_t rdi;
uint64_t r8;
uint64_t r9;
uint64_t r10;
uint64_t r11;
uint64_t r12;
uint64_t r13;
uint64_t r14;
uint64_t r15;
uint64_t rip;
//This should be expanded to 16 if x87 registers are considered
uint64_t mmx[8];
uint64_t xmm[32];
void update(NativeTrace *parent);
void update(ThreadContext *tc);
};
ThreadState nState;
ThreadState mState;
bool checkRcxReg(const char * regName, uint64_t &, uint64_t &);
bool checkR11Reg(const char * regName, uint64_t &, uint64_t &);
bool checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[]);
public:
X86NativeTrace(const Params *p);
void check(NativeTraceRecord *record);
};
} /* namespace Trace */
#endif // __ARCH_X86_NATIVETRACE_HH__

2
src/arch/x86/process.cc
View file

@ -497,6 +497,7 @@ X86LiveProcess::argsInit(int pageSize,
//The system page size
auxv.push_back(auxv_t(M5_AT_PAGESZ, X86ISA::VMPageSize));
//Frequency at which times() increments
//Defined to be 100 in the kernel source.
auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
// For statically linked executables, this is the virtual address of the
// program header tables if they appear in the executable image
@ -505,7 +506,6 @@ X86LiveProcess::argsInit(int pageSize,
auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize()));
// This is the number of program headers from the original elf file.
auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount()));
//Defined to be 100 in the kernel source.
//This is the address of the elf "interpreter", It should be set
//to 0 for regular executables. It should be something else
//(not sure what) for dynamic libraries.

1
src/cpu/NativeTrace.py
View file

@ -31,5 +31,6 @@ from m5.params import *
from InstTracer import InstTracer
class NativeTrace(InstTracer):
abstract = True
type = 'NativeTrace'
cxx_class = 'Trace::NativeTrace'

6
src/cpu/SConscript
View file

@ -112,6 +112,7 @@ SimObject('BaseCPU.py')
SimObject('FuncUnit.py')
SimObject('ExeTracer.py')
SimObject('IntelTrace.py')
SimObject('NativeTrace.py')
Source('activity.cc')
Source('base.cc')
@ -119,6 +120,7 @@ Source('cpuevent.cc')
Source('exetrace.cc')
Source('func_unit.cc')
Source('inteltrace.cc')
Source('nativetrace.cc')
Source('pc_event.cc')
Source('quiesce_event.cc')
Source('static_inst.cc')
@ -136,10 +138,6 @@ if env['FULL_SYSTEM']:
SimObject('LegionTrace.py')
Source('legiontrace.cc')
if env['TARGET_ISA'] == 'x86':
SimObject('NativeTrace.py')
Source('nativetrace.cc')
if env['USE_CHECKER']:
Source('checker/cpu.cc')
TraceFlag('Checker')

169
src/cpu/nativetrace.cc
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2001-2005 The Regents of The University of Michigan
* Copyright (c) 2006-2009 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -25,28 +25,15 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Steve Reinhardt
* Lisa Hsu
* Nathan Binkert
* Steve Raasch
* Authors: Gabe Black
*/
#include <errno.h>
#include "arch/registers.hh"
#include "arch/utility.hh"
#include "base/loader/symtab.hh"
#include "base/socket.hh"
#include "cpu/nativetrace.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "params/NativeTrace.hh"
//XXX This is temporary
#include "arch/isa_specific.hh"
using namespace std;
using namespace TheISA;
namespace Trace {
@ -64,41 +51,6 @@ NativeTrace::NativeTrace(const Params *p)
}
ccprintf(cerr, "Listening for native process on port %d\n", port);
fd = native_listener.accept();
checkRcx = true;
checkR11 = true;
}
bool
NativeTrace::checkRcxReg(const char * name, uint64_t &mVal, uint64_t &nVal)
{
if(!checkRcx)
checkRcx = (mVal != oldRcxVal || nVal != oldRealRcxVal);
if(checkRcx)
return checkReg(name, mVal, nVal);
return true;
}
bool
NativeTrace::checkR11Reg(const char * name, uint64_t &mVal, uint64_t &nVal)
{
if(!checkR11)
checkR11 = (mVal != oldR11Val || nVal != oldRealR11Val);
if(checkR11)
return checkReg(name, mVal, nVal);
return true;
}
bool
NativeTrace::checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[])
{
if (mXmmBuf[num * 2] != nXmmBuf[num * 2] ||
mXmmBuf[num * 2 + 1] != nXmmBuf[num * 2 + 1]) {
DPRINTFN("Register xmm%d should be 0x%016x%016x but is 0x%016x%016x.\n",
num, nXmmBuf[num * 2 + 1], nXmmBuf[num * 2],
mXmmBuf[num * 2 + 1], mXmmBuf[num * 2]);
return false;
}
return true;
}
void
@ -106,119 +58,8 @@ Trace::NativeTraceRecord::dump()
{
//Don't print what happens for each micro-op, just print out
//once at the last op, and for regular instructions.
if(!staticInst->isMicroop() || staticInst->isLastMicroop())
parent->check(thread, staticInst->isSyscall());
if (!staticInst->isMicroop() || staticInst->isLastMicroop())
parent->check(this);
}
void
Trace::NativeTrace::check(ThreadContext * tc, bool isSyscall)
{
// ostream &outs = Trace::output();
nState.update(fd);
mState.update(tc);
if(isSyscall)
{
checkRcx = false;
checkR11 = false;
oldRcxVal = mState.rcx;
oldRealRcxVal = nState.rcx;
oldR11Val = mState.r11;
oldRealR11Val = nState.r11;
}
checkReg("rax", mState.rax, nState.rax);
checkRcxReg("rcx", mState.rcx, nState.rcx);
checkReg("rdx", mState.rdx, nState.rdx);
checkReg("rbx", mState.rbx, nState.rbx);
checkReg("rsp", mState.rsp, nState.rsp);
checkReg("rbp", mState.rbp, nState.rbp);
checkReg("rsi", mState.rsi, nState.rsi);
checkReg("rdi", mState.rdi, nState.rdi);
checkReg("r8", mState.r8, nState.r8);
checkReg("r9", mState.r9, nState.r9);
checkReg("r10", mState.r10, nState.r10);
checkR11Reg("r11", mState.r11, nState.r11);
checkReg("r12", mState.r12, nState.r12);
checkReg("r13", mState.r13, nState.r13);
checkReg("r14", mState.r14, nState.r14);
checkReg("r15", mState.r15, nState.r15);
checkReg("rip", mState.rip, nState.rip);
checkXMM(0, mState.xmm, nState.xmm);
checkXMM(1, mState.xmm, nState.xmm);
checkXMM(2, mState.xmm, nState.xmm);
checkXMM(3, mState.xmm, nState.xmm);
checkXMM(4, mState.xmm, nState.xmm);
checkXMM(5, mState.xmm, nState.xmm);
checkXMM(6, mState.xmm, nState.xmm);
checkXMM(7, mState.xmm, nState.xmm);
checkXMM(8, mState.xmm, nState.xmm);
checkXMM(9, mState.xmm, nState.xmm);
checkXMM(10, mState.xmm, nState.xmm);
checkXMM(11, mState.xmm, nState.xmm);
checkXMM(12, mState.xmm, nState.xmm);
checkXMM(13, mState.xmm, nState.xmm);
checkXMM(14, mState.xmm, nState.xmm);
checkXMM(15, mState.xmm, nState.xmm);
#if THE_ISA == SPARC_ISA
/*for(int f = 0; f <= 62; f+=2)
{
uint64_t regVal;
int res = read(fd, &regVal, sizeof(regVal));
if(res < 0)
panic("First read call failed! %s\n", strerror(errno));
regVal = TheISA::gtoh(regVal);
uint64_t realRegVal = thread->readFloatRegBits(f, 64);
if(regVal != realRegVal)
{
DPRINTF(ExecRegDelta, "Register f%d should be %#x but is %#x.\n", f, regVal, realRegVal);
}
}*/
uint64_t regVal;
int res = read(fd, &regVal, sizeof(regVal));
if(res < 0)
panic("First read call failed! %s\n", strerror(errno));
regVal = TheISA::gtoh(regVal);
uint64_t realRegVal = thread->readNextPC();
if(regVal != realRegVal)
{
DPRINTF(ExecRegDelta,
"Register pc should be %#x but is %#x.\n",
regVal, realRegVal);
}
res = read(fd, &regVal, sizeof(regVal));
if(res < 0)
panic("First read call failed! %s\n", strerror(errno));
regVal = TheISA::gtoh(regVal);
realRegVal = thread->readNextNPC();
if(regVal != realRegVal)
{
DPRINTF(ExecRegDelta,
"Register npc should be %#x but is %#x.\n",
regVal, realRegVal);
}
res = read(fd, &regVal, sizeof(regVal));
if(res < 0)
panic("First read call failed! %s\n", strerror(errno));
regVal = TheISA::gtoh(regVal);
realRegVal = thread->readIntReg(SparcISA::NumIntArchRegs + 2);
if((regVal & 0xF) != (realRegVal & 0xF))
{
DPRINTF(ExecRegDelta,
"Register ccr should be %#x but is %#x.\n",
regVal, realRegVal);
}
#endif
}
/* namespace Trace */ }
////////////////////////////////////////////////////////////////////////
//
// ExeTracer Simulation Object
//
Trace::NativeTrace *
NativeTraceParams::create()
{
return new Trace::NativeTrace(this);
};
} /* namespace Trace */

159
src/cpu/nativetrace.hh
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2001-2005 The Regents of The University of Michigan
* Copyright (c) 2006-2009 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -25,15 +25,16 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Steve Reinhardt
* Nathan Binkert
* Authors: Gabe Black
*/
#ifndef __CPU_NATIVETRACE_HH__
#define __CPU_NATIVETRACE_HH__
#include "arch/x86/floatregs.hh"
#include "arch/x86/intregs.hh"
#include <errno.h>
#include <unistd.h>
#include "base/socket.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
@ -71,103 +72,23 @@ class NativeTrace : public InstTracer
ListenSocket native_listener;
bool checkRcx;
bool checkR11;
uint64_t oldRcxVal, oldR11Val;
uint64_t oldRealRcxVal, oldRealR11Val;
struct ThreadState {
uint64_t rax;
uint64_t rcx;
uint64_t rdx;
uint64_t rbx;
uint64_t rsp;
uint64_t rbp;
uint64_t rsi;
uint64_t rdi;
uint64_t r8;
uint64_t r9;
uint64_t r10;
uint64_t r11;
uint64_t r12;
uint64_t r13;
uint64_t r14;
uint64_t r15;
uint64_t rip;
//This should be expanded to 16 if x87 registers are considered
uint64_t mmx[8];
uint64_t xmm[32];
void update(int fd)
{
int bytesLeft = sizeof(ThreadState);
int bytesRead = 0;
do
{
int res = read(fd, ((char *)this) + bytesRead, bytesLeft);
if(res < 0)
panic("Read call failed! %s\n", strerror(errno));
bytesLeft -= res;
bytesRead += res;
} while(bytesLeft);
rax = TheISA::gtoh(rax);
rcx = TheISA::gtoh(rcx);
rdx = TheISA::gtoh(rdx);
rbx = TheISA::gtoh(rbx);
rsp = TheISA::gtoh(rsp);
rbp = TheISA::gtoh(rbp);
rsi = TheISA::gtoh(rsi);
rdi = TheISA::gtoh(rdi);
r8 = TheISA::gtoh(r8);
r9 = TheISA::gtoh(r9);
r10 = TheISA::gtoh(r10);
r11 = TheISA::gtoh(r11);
r12 = TheISA::gtoh(r12);
r13 = TheISA::gtoh(r13);
r14 = TheISA::gtoh(r14);
r15 = TheISA::gtoh(r15);
rip = TheISA::gtoh(rip);
//This should be expanded if x87 registers are considered
for (int i = 0; i < 8; i++)
mmx[i] = TheISA::gtoh(mmx[i]);
for (int i = 0; i < 32; i++)
xmm[i] = TheISA::gtoh(xmm[i]);
}
void update(ThreadContext * tc)
{
rax = tc->readIntReg(X86ISA::INTREG_RAX);
rcx = tc->readIntReg(X86ISA::INTREG_RCX);
rdx = tc->readIntReg(X86ISA::INTREG_RDX);
rbx = tc->readIntReg(X86ISA::INTREG_RBX);
rsp = tc->readIntReg(X86ISA::INTREG_RSP);
rbp = tc->readIntReg(X86ISA::INTREG_RBP);
rsi = tc->readIntReg(X86ISA::INTREG_RSI);
rdi = tc->readIntReg(X86ISA::INTREG_RDI);
r8 = tc->readIntReg(X86ISA::INTREG_R8);
r9 = tc->readIntReg(X86ISA::INTREG_R9);
r10 = tc->readIntReg(X86ISA::INTREG_R10);
r11 = tc->readIntReg(X86ISA::INTREG_R11);
r12 = tc->readIntReg(X86ISA::INTREG_R12);
r13 = tc->readIntReg(X86ISA::INTREG_R13);
r14 = tc->readIntReg(X86ISA::INTREG_R14);
r15 = tc->readIntReg(X86ISA::INTREG_R15);
rip = tc->readNextPC();
//This should be expanded if x87 registers are considered
for (int i = 0; i < 8; i++)
mmx[i] = tc->readFloatRegBits(X86ISA::FLOATREG_MMX(i));
for (int i = 0; i < 32; i++)
xmm[i] = tc->readFloatRegBits(X86ISA::FLOATREG_XMM_BASE + i);
}
};
ThreadState nState;
ThreadState mState;
public:
NativeTrace(const Params *p);
virtual ~NativeTrace() {}
NativeTraceRecord *
getInstRecord(Tick when, ThreadContext *tc,
const StaticInstPtr staticInst, Addr pc,
const StaticInstPtr macroStaticInst = NULL, MicroPC upc = 0)
{
if (tc->misspeculating())
return NULL;
return new NativeTraceRecord(this, when, tc,
staticInst, pc, tc->misspeculating(), macroStaticInst, upc);
}
template<class T>
bool
checkReg(const char * regName, T &val, T &realVal)
@ -181,35 +102,23 @@ class NativeTrace : public InstTracer
return true;
}
bool
checkRcxReg(const char * regName, uint64_t &, uint64_t &);
bool
checkR11Reg(const char * regName, uint64_t &, uint64_t &);
bool
checkXMM(int num, uint64_t mXmmBuf[], uint64_t nXmmBuf[]);
NativeTrace(const Params *p);
NativeTraceRecord *
getInstRecord(Tick when, ThreadContext *tc,
const StaticInstPtr staticInst, Addr pc,
const StaticInstPtr macroStaticInst = NULL, MicroPC upc = 0)
void
read(void *ptr, size_t size)
{
if (tc->misspeculating())
return NULL;
return new NativeTraceRecord(this, when, tc,
staticInst, pc, tc->misspeculating(), macroStaticInst, upc);
size_t soFar = 0;
while (soFar < size) {
size_t res = ::read(fd, (uint8_t *)ptr + soFar, size - soFar);
if (res < 0)
panic("Read call failed! %s\n", strerror(errno));
else
soFar += res;
}
}
void
check(ThreadContext *, bool syscall);
friend class NativeTraceRecord;
virtual void
check(NativeTraceRecord *record) = 0;
};
/* namespace Trace */ }
} /* namespace Trace */
#endif // __CPU_NATIVETRACE_HH__

22
src/sim/insttracer.hh
View file

@ -129,6 +129,28 @@ class InstRecord
{ cp_seq = seq; cp_seq_valid = true; }
virtual void dump() = 0;
public:
Tick getWhen() { return when; }
ThreadContext *getThread() { return thread; }
StaticInstPtr getStaticInst() { return staticInst; }
Addr getPC() { return PC; }
StaticInstPtr getMacroStaticInst() { return macroStaticInst; }
MicroPC getUPC() { return upc; }
bool getMisspeculating() { return misspeculating; }
Addr getAddr() { return addr; }
bool getAddrValid() { return addr_valid; }
uint64_t getIntData() { return data.as_int; }
double getFloatData() { return data.as_double; }
int getDataStatus() { return data_status; }
InstSeqNum getFetchSeq() { return fetch_seq; }
bool getFetchSeqValid() { return fetch_seq_valid; }
InstSeqNum getCpSeq() { return cp_seq; }
bool getCpSeqValid() { return cp_seq_valid; }
};
class InstTracer : public SimObject