sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Packages Projects Releases Wiki Activity

X86: Implement a locking version of AND.

Browse source
This commit is contained in:
Gabe Black 2009-04-19 04:56:14 -07:00
parent e742cad6f4
commit 789b3191b9
1 changed files with 32 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

32
src/arch/x86/isa/insts/general_purpose/logical.py
View file

@ -239,6 +239,23 @@ def macroop AND_P_I
st t2, seg, riprel, disp
};
def macroop AND_LOCKED_M_I
{
ldstl t2, seg, sib, disp
limm t1, imm
and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
stul t2, seg, sib, disp
};
def macroop AND_LOCKED_P_I
{
rdip t7
ldstl t2, seg, riprel, disp
limm t1, imm
and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
stul t2, seg, riprel, disp
};
def macroop AND_M_R
{
ldst t1, seg, sib, disp
@ -254,6 +271,21 @@ def macroop AND_P_R
st t1, seg, riprel, disp
};
def macroop AND_LOCKED_M_R
{
ldstl t1, seg, sib, disp
and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
stul t1, seg, sib, disp
};
def macroop AND_LOCKED_P_R
{
rdip t7
ldstl t1, seg, riprel, disp
and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
stul t1, seg, riprel, disp
};
def macroop NOT_R
{
limm t1, -1