ARM: Hook the new external data processing instructions to the ARM decoder.
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Gabe Black
parent
bf45d44cbe
commit
8136cb3605
3 changed files with 156 additions and 44 deletions
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@ -93,24 +93,7 @@ format DataOp {
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0xb, 0xd, 0xf: AddrMode3::addrMode3();
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}
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0: decode IS_MISC {
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0: decode OPCODE {
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0x0: and({{ Rd = resTemp = Rn & op2; }});
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0x1: eor({{ Rd = resTemp = Rn ^ op2; }});
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0x2: sub({{ Rd = resTemp = Rn - op2; }}, sub);
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0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, rsb);
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0x4: add({{ Rd = resTemp = Rn + op2; }}, add);
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0x5: adc({{ Rd = resTemp = Rn + op2 + CondCodes<29:>; }}, add);
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0x6: sbc({{ Rd = resTemp = Rn - op2 - !CondCodes<29:>; }}, sub);
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0x7: rsc({{ Rd = resTemp = op2 - Rn - !CondCodes<29:>; }}, rsb);
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0x8: tst({{ resTemp = Rn & op2; }});
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0x9: teq({{ resTemp = Rn ^ op2; }});
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0xa: cmp({{ resTemp = Rn - op2; }}, sub);
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0xb: cmn({{ resTemp = Rn + op2; }}, add);
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0xc: orr({{ Rd = resTemp = Rn | op2; }});
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0xd: mov({{ Rd = resTemp = op2; }});
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0xe: bic({{ Rd = resTemp = Rn & ~op2; }});
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0xf: mvn({{ Rd = resTemp = ~op2; }});
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}
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0: ArmDataProcReg::armDataProcReg();
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1: decode MISC_OPCODE {
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0x0: decode OPCODE {
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0x8: PredOp::mrs_cpsr({{
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@ -195,32 +178,7 @@ format DataOp {
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}
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}
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0x1: decode IS_MISC {
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0: decode OPCODE {
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format DataImmOp {
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0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }});
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0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }});
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0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }}, sub);
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0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }}, rsb);
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0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }}, add);
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0x5: adci({{
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Rd = resTemp = Rn + rotated_imm + CondCodes<29:>;
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}}, add);
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0x6: sbci({{
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Rd = resTemp = Rn -rotated_imm - !CondCodes<29:>;
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}}, sub);
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0x7: rsci({{
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Rd = resTemp = rotated_imm - Rn - !CondCodes<29:>;
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}}, rsb);
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0x8: tsti({{ resTemp = Rn & rotated_imm; }});
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0x9: teqi({{ resTemp = Rn ^ rotated_imm; }});
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0xa: cmpi({{ resTemp = Rn - rotated_imm; }}, sub);
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0xb: cmni({{ resTemp = Rn + rotated_imm; }}, add);
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0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }});
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0xd: movi({{ Rd = resTemp = rotated_imm; }});
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0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }});
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0xf: mvni({{ Rd = resTemp = ~rotated_imm; }});
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}
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}
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0: ArmDataProcImm::armDataProcImm();
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1: decode OPCODE {
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// The following two instructions aren't supposed to be defined
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0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});
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151
src/arch/arm/isa/formats/data.isa
Normal file
151
src/arch/arm/isa/formats/data.isa
Normal file
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@ -0,0 +1,151 @@
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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def format ArmDataProcReg() {{
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instDecode = '''
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case %(opcode)#x:
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if (immShift) {
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if (setCc) {
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return new %(className)sDRegCc(machInst,
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rd, rn, rm, imm5, type);
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} else {
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return new %(className)sDReg(machInst,
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rd, rn, rm, imm5, type);
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}
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} else {
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if (setCc) {
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return new %(className)sDRegRegCc(machInst,
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rd, rn, rm, rs, type);
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} else {
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return new %(className)sDRegReg(machInst,
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rd, rn, rm, rs, type);
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}
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}
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break;
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'''
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def instCode(opcode, mnem):
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global instDecode
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return instDecode % { "className": mnem.capitalize(),
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"opcode": opcode }
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decode_block = '''
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{
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const bool immShift = (bits(machInst, 4) == 0);
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const bool setCc = (bits(machInst, 20) == 1);
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const uint32_t imm5 = bits(machInst, 11, 7);
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const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 6, 5);
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const IntRegIndex rd = (IntRegIndex)(uint32_t)RD;
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const IntRegIndex rn = (IntRegIndex)(uint32_t)RN;
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const IntRegIndex rm = (IntRegIndex)(uint32_t)RM;
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const IntRegIndex rs = (IntRegIndex)(uint32_t)RS;
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switch (OPCODE) {
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'''
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decode_block += instCode(0x0, "and")
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decode_block += instCode(0x1, "eor")
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decode_block += instCode(0x2, "sub")
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decode_block += instCode(0x3, "rsb")
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decode_block += instCode(0x4, "add")
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decode_block += instCode(0x5, "adc")
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decode_block += instCode(0x6, "sbc")
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decode_block += instCode(0x7, "rsc")
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decode_block += instCode(0x8, "tst")
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decode_block += instCode(0x9, "teq")
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decode_block += instCode(0xa, "cmp")
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decode_block += instCode(0xb, "cmn")
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decode_block += instCode(0xc, "orr")
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decode_block += instCode(0xd, "mov")
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decode_block += instCode(0xe, "bic")
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decode_block += instCode(0xf, "mvn")
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decode_block += '''
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default:
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return new Unknown(machInst);
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}
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}
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'''
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}};
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def format ArmDataProcImm() {{
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instDecode = '''
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case %(opcode)#x:
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if (setCc) {
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return new %(className)sDImmCc(machInst, rd, rn, imm, rotC);
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} else {
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return new %(className)sDImm(machInst, rd, rn, imm, rotC);
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}
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break;
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'''
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def instCode(opcode, mnem):
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global instDecode
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return instDecode % { "className": mnem.capitalize(),
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"opcode": opcode }
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decode_block = '''
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{
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const bool setCc = (bits(machInst, 20) == 1);
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const uint32_t unrotated = bits(machInst, 7, 0);
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const uint32_t rotation = (bits(machInst, 11, 8) << 1);
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const bool rotC = (rotation != 0);
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const uint32_t imm = rotate_imm(unrotated, rotation);
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const IntRegIndex rd = (IntRegIndex)(uint32_t)RD;
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const IntRegIndex rn = (IntRegIndex)(uint32_t)RN;
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switch (OPCODE) {
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'''
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decode_block += instCode(0x0, "and")
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decode_block += instCode(0x1, "eor")
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decode_block += instCode(0x2, "sub")
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decode_block += instCode(0x3, "rsb")
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decode_block += instCode(0x4, "add")
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decode_block += instCode(0x5, "adc")
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decode_block += instCode(0x6, "sbc")
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decode_block += instCode(0x7, "rsc")
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decode_block += instCode(0x8, "tst")
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decode_block += instCode(0x9, "teq")
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decode_block += instCode(0xa, "cmp")
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decode_block += instCode(0xb, "cmn")
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decode_block += instCode(0xc, "orr")
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decode_block += instCode(0xd, "mov")
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decode_block += instCode(0xe, "bic")
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decode_block += instCode(0xf, "mvn")
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decode_block += '''
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default:
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return new Unknown(machInst);
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}
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}
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'''
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}};
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@ -67,3 +67,6 @@
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//Include the unknown format
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##include "unknown.isa"
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//Include the formats for data processing instructions
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##include "data.isa"
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