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ARM: Decode the scalar saturating add/subtract instructions.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:05 -05:00
parent 30dd622622
commit 4fb6fcd82d
2 changed files with 23 additions and 6 deletions
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7
src/arch/arm/isa/decoder/arm.isa
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@ -116,12 +116,7 @@ format DataOp {
0x3: decode OPCODE {
0x9: ArmBlxReg::armBlxReg();
}
0x5: decode OPCODE {
0x8: WarnUnimpl::qadd();
0x9: WarnUnimpl::qsub();
0xa: WarnUnimpl::qdadd();
0xb: WarnUnimpl::qdsub();
}
0x5: ArmSatAddSub::armSatAddSub();
}
0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
}

22
src/arch/arm/isa/formats/data.isa
View file

@ -341,6 +341,28 @@ def format ArmDataProcImm() {{
'''
}};
def format ArmSatAddSub() {{
decode_block = '''
{
IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
switch (OPCODE) {
case 0x8:
return new QaddRegCc(machInst, rd, rm, rn, 0, LSL);
case 0x9:
return new QsubRegCc(machInst, rd, rm, rn, 0, LSL);
case 0xa:
return new QdaddRegCc(machInst, rd, rm, rn, 0, LSL);
case 0xb:
return new QdsubRegCc(machInst, rd, rm, rn, 0, LSL);
default:
return new Unknown(machInst);
}
}
'''
}};
def format Thumb16ShiftAddSubMoveCmp() {{
decode_block = '''
{