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X86: Fix some incorrect register widths.

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Gabe Black 2009-02-01 00:18:13 -08:00
parent f3b8371dfc
commit d432bd13b2
1 changed files with 2 additions and 2 deletions
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4
src/arch/x86/isa/operands.isa
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@ -159,7 +159,7 @@ def operands {{
'CSAttr': ('ControlReg', 'udw', 'MISCREG_CS_ATTR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 208),
'MiscRegDest': ('ControlReg', 'uqw', 'dest', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 209),
'MiscRegSrc1': ('ControlReg', 'uqw', 'src1', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 210),
'TscOp': ('ControlReg', 'udw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 211),
'M5Reg': ('ControlReg', 'udw', 'MISCREG_M5_REG', (None, None, None), 212),
'TscOp': ('ControlReg', 'uqw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 211),
'M5Reg': ('ControlReg', 'uqw', 'MISCREG_M5_REG', (None, None, None), 212),
'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 300)
}};