ARM: Begin implementing CP15

This commit is contained in:
Ali Saidi 2009-11-17 18:02:09 -06:00
parent 0916c376a9
commit 422f0d9f10
6 changed files with 69 additions and 4 deletions

View file

@ -27,6 +27,7 @@
* Authors: Stephen Hines
*/
#include "arch/arm/faults.hh"
#include "arch/arm/insts/static_inst.hh"
#include "base/condcodes.hh"
#include "base/cprintf.hh"

View file

@ -49,6 +49,7 @@ def bitfield OPCODE_18 opcode18;
def bitfield OPCODE_15_12 opcode15_12;
def bitfield OPCODE_15 opcode15;
def bitfield MISC_OPCODE miscOpcode;
def bitfield OPC2 opc2;
def bitfield OPCODE_7 opcode7;
def bitfield OPCODE_4 opcode4;

View file

@ -493,10 +493,53 @@ format DataOp {
}
} // MEDIA_OPCODE (MISC_OPCODE 0x1)
} // MISC_OPCODE (CPNUM 0xA)
0xf: decode OPCODE_20 {
0: WarnUnimpl::mcr_cp15();
1: WarnUnimpl::mrc_cp15();
}
0xf: decode RN {
// Barrriers, Cache Maintence, NOPS
7: decode OPCODE_23_21 {
0: decode RM {
0: decode OPC2 {
4: decode OPCODE_20 {
0: PredOp::mcr_cp15_nop1({{ }}); // was wfi
}
}
1: WarnUnimpl::cp15_cache_maint();
4: WarnUnimpl::cp15_par();
5: decode OPC2 {
0,1: WarnUnimpl::cp15_cache_maint2();
4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore);
6,7: WarnUnimpl::cp15_bp_maint();
}
6: WarnUnimpl::cp15_cache_maint3();
8: WarnUnimpl::cp15_va_to_pa();
10: decode OPC2 {
1,2: WarnUnimpl::cp15_cache_maint3();
4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore);
5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore);
}
11: WarnUnimpl::cp15_cache_maint4();
13: decode OPC2 {
1: decode OPCODE_20 {
0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch
}
}
14: WarnUnimpl::cp15_cache_maint5();
} // RM
} // OPCODE_23_21 CR
// Thread ID and context ID registers
// Thread ID register needs cheaper access than miscreg
13: WarnUnimpl::mcr_mrc_cp15_c7();
// All the rest
default: decode OPCODE_20 {
0: PredOp::mcr_cp15({{
fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
}});
1: PredOp::mrc_cp15({{
fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
}});
}
} // RN
} // CPNUM (OP4 == 1)
} //OPCODE_4

View file

@ -58,6 +58,7 @@ namespace ArmISA
Bitfield<15, 12> opcode15_12;
Bitfield<15> opcode15;
Bitfield<7, 4> miscOpcode;
Bitfield<7,5> opc2;
Bitfield<7> opcode7;
Bitfield<4> opcode4;

View file

@ -57,4 +57,20 @@ uint64_t getArgument(ThreadContext *tc, int number, bool fp) {
#endif
}
Fault
setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2)
{
return new UnimpFault(csprintf("MCR CP15: CRn: %d opc1: %d CRm: %d opc1: %d\n",
CRn, opc1, CRm, opc2));
}
Fault
readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2)
{
return new UnimpFault(csprintf("MRC CP15: CRn: %d opc1: %d CRm: %d opc1: %d\n",
CRn, opc1, CRm, opc2));
}
}

View file

@ -135,6 +135,9 @@ namespace ArmISA {
}
uint64_t getArgument(ThreadContext *tc, int number, bool fp);
Fault setCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
Fault readCp15Register(uint32_t &Rd, int CRn, int opc1, int CRm, int opc2);
};