IGbE: Patches I neglected to apply before pushing the previous igbe changeset
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3633a916c2
commit
3d5fe0c372
2 changed files with 59 additions and 23 deletions
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@ -587,6 +587,8 @@ IGbE::postInterrupt(IntTypes t, bool now)
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regs.icr = regs.icr() | t;
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Tick itr_interval = Clock::Int::ns * 256 * regs.itr.interval();
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DPRINTF(EthernetIntr, "EINT: postInterrupt() curTick: %d itr: %d interval: %d\n",
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curTick, regs.itr.interval(), itr_interval);
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if (regs.itr.interval() == 0 || now || lastInterrupt + itr_interval <= curTick) {
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if (interEvent.scheduled()) {
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@ -652,6 +654,7 @@ IGbE::cpuPostInt()
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intrPost();
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lastInterrupt = curTick;
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}
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void
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@ -1404,6 +1407,7 @@ IGbE::txWire()
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txBytes += txFifo.front()->length;
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txPackets++;
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txFifoTick = false;
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txFifo.pop();
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} else {
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@ -133,6 +133,8 @@ class IGbE : public EtherDevice
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EventWrapper<IGbE, &IGbE::tick> tickEvent;
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uint64_t macAddr;
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void rxStateMachine();
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void txStateMachine();
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void txWire();
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@ -250,23 +252,23 @@ class IGbE : public EtherDevice
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void writeback(Addr aMask)
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{
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int curHead = descHead();
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int max_to_wb = usedCache.size();
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// Check if this writeback is less restrictive that the previous
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// and if so setup another one immediately following it
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if (wbOut) {
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if (aMask < wbAlignment) {
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moreToWb = true;
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wbAlignment = aMask;
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}
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DPRINTF(EthernetDesc, "Writing back already in process, returning\n");
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return;
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}
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moreToWb = false;
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wbAlignment = aMask;
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if (!wbDelayEvent.scheduled())
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wbDelayEvent.schedule(igbe->wbDelay + curTick);
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}
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void writeback1()
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{
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int curHead = descHead();
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int max_to_wb = usedCache.size();
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DPRINTF(EthernetDesc, "Writing back descriptors head: %d tail: "
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"%d len: %d cachePnt: %d max_to_wb: %d descleft: %d\n",
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@ -284,21 +286,35 @@ class IGbE : public EtherDevice
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DPRINTF(EthernetDesc, "Writing back %d descriptors\n", max_to_wb);
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if (max_to_wb <= 0 || wbOut)
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if (max_to_wb <= 0) {
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return;
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}
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wbOut = max_to_wb;
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for (int x = 0; x < wbOut; x++) {
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assert(usedCache.size());
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memcpy(&wbBuf[x], usedCache[0], sizeof(T));
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delete usedCache[0];
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usedCache.pop_front();
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assert(!wbDelayEvent.scheduled());
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wbDelayEvent.schedule(igbe->wbDelay + curTick);
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}
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void writeback1()
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{
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// If we're draining delay issuing this DMA
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if (igbe->drainEvent) {
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wbDelayEvent.schedule(igbe->wbDelay + curTick);
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return;
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}
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DPRINTF(EthernetDesc, "Beining DMA of %d descriptors\n", wbOut);
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for (int x = 0; x < wbOut; x++) {
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assert(usedCache.size());
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memcpy(&wbBuf[x], usedCache[x], sizeof(T));
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//delete usedCache[0];
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//usedCache.pop_front();
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}
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assert(wbOut);
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igbe->dmaWrite(igbe->platform->pciToDma(descBase() + curHead * sizeof(T)),
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igbe->dmaWrite(igbe->platform->pciToDma(descBase() + descHead() * sizeof(T)),
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wbOut * sizeof(T), &wbEvent, (uint8_t*)wbBuf,
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igbe->wbCompDelay);
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}
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@ -309,17 +325,13 @@ class IGbE : public EtherDevice
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*/
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void fetchDescriptors()
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{
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if (!fetchDelayEvent.scheduled())
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fetchDelayEvent.schedule(igbe->fetchDelay + curTick);
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}
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void fetchDescriptors1()
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{
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size_t max_to_fetch;
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if (curFetching)
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if (curFetching) {
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DPRINTF(EthernetDesc, "Currently fetching %d descriptors, returning\n", curFetching);
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return;
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}
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if (descTail() >= cachePnt)
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max_to_fetch = descTail() - cachePnt;
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@ -329,6 +341,7 @@ class IGbE : public EtherDevice
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size_t free_cache = size - usedCache.size() - unusedCache.size();
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max_to_fetch = std::min(max_to_fetch, free_cache);
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DPRINTF(EthernetDesc, "Fetching descriptors head: %d tail: "
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"%d len: %d cachePnt: %d max_to_fetch: %d descleft: %d\n",
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@ -338,10 +351,22 @@ class IGbE : public EtherDevice
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// Nothing to do
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if (max_to_fetch == 0)
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return;
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// So we don't have two descriptor fetches going on at once
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curFetching = max_to_fetch;
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assert(!fetchDelayEvent.scheduled());
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fetchDelayEvent.schedule(igbe->fetchDelay + curTick);
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}
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void fetchDescriptors1()
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{
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// If we're draining delay issuing this DMA
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if (igbe->drainEvent) {
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fetchDelayEvent.schedule(igbe->fetchDelay + curTick);
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return;
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}
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DPRINTF(EthernetDesc, "Fetching descriptors at %#x (%#x), size: %#x\n",
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descBase() + cachePnt * sizeof(T),
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igbe->platform->pciToDma(descBase() + cachePnt * sizeof(T)),
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@ -365,6 +390,7 @@ class IGbE : public EtherDevice
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unusedCache.push_back(newDesc);
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}
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#ifndef NDEBUG
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int oldCp = cachePnt;
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#endif
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@ -394,6 +420,12 @@ class IGbE : public EtherDevice
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#ifndef NDEBUG
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long oldHead = curHead;
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#endif
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for (int x = 0; x < wbOut; x++) {
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assert(usedCache.size());
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delete usedCache[0];
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usedCache.pop_front();
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}
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curHead += wbOut;
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wbOut = 0;
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