X86: Make the long mode interrupt/exception microcode handle an error code.
This commit is contained in:
Gabe Black
parent
9b4d1e0f9a
commit
2f8cec849d
2 changed files with 49 additions and 24 deletions
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@ -123,6 +123,7 @@ namespace X86ISA
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}
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tc->setIntReg(INTREG_MICRO(1), vector);
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tc->setIntReg(INTREG_MICRO(7), tc->readPC());
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tc->setIntReg(INTREG_MICRO(15), (uint64_t)(-1));
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tc->setMicroPC(romMicroPC(entry));
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tc->setNextMicroPC(romMicroPC(entry) + 1);
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}
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@ -26,13 +26,13 @@
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#
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# Authors: Gabe Black
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microcode = '''
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intCodeTemplate = '''
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def rom
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{
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# This vectors the CPU into an interrupt handler in long mode.
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# On entry, t1 is set to the vector of the interrupt and t7 is the current
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# ip. We need that because rdip returns the next ip.
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extern longModeInterrupt:
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extern %(startLabel)s:
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#
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# Get the 64 bit interrupt or trap gate descriptor from the IDT
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@ -44,7 +44,7 @@ def rom
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ld t4, idtr, [1, t0, t4], dataSize=8, addressSize=8
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# Make sure the descriptor is a legal gate.
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chks t1, t4, IntGateCheck
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chks t1, t4, %(gateCheckType)s
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#
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# Get the target CS descriptor using the selector in the gate
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@ -53,12 +53,12 @@ def rom
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srli t10, t4, 16, dataSize=8
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andi t5, t10, 0xF8, dataSize=8
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andi t0, t10, 0x4, flags=(EZF,), dataSize=2
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br rom_local_label("globalDescriptor"), flags=(CEZF,)
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br rom_local_label("%(startLabel)s_globalDescriptor"), flags=(CEZF,)
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ld t3, tsl, [1, t0, t5], dataSize=8, addressSize=8
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br rom_local_label("processDescriptor")
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globalDescriptor:
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br rom_local_label("%(startLabel)s_processDescriptor")
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%(startLabel)s_globalDescriptor:
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ld t3, tsg, [1, t0, t5], dataSize=8, addressSize=8
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processDescriptor:
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%(startLabel)s_processDescriptor:
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chks t10, t3, IntCSCheck, dataSize=8
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wrdl hs, t3, t10, dataSize=8
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@ -90,29 +90,29 @@ processDescriptor:
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srli t10, t4, 32, dataSize=8
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andi t10, t10, 0x7, dataSize=8
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subi t0, t10, 1, flags=(ECF,), dataSize=8
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br rom_local_label("istStackSwitch"), flags=(nCECF,)
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br rom_local_label("cplStackSwitch"), flags=(nCEZF,)
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br rom_local_label("%(startLabel)s_istStackSwitch"), flags=(nCECF,)
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br rom_local_label("%(startLabel)s_cplStackSwitch"), flags=(nCEZF,)
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# If we're here, it's because the stack isn't being switched.
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# Set t6 to the new rsp.
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subi t6, rsp, 40, dataSize=8
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# Align the stack
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# Set t6 to the new aligned rsp.
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mov t6, rsp, dataSize=8
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andi t6, t6, 0xF0, dataSize=1
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subi t6, t6, 40 + %(errorCodeSize)d, dataSize=8
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# Check that we can access everything we need to on the stack
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ldst t0, hs, [1, t0, t6], dataSize=8, addressSize=8
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ldst t0, hs, [1, t0, t6], 32, dataSize=8, addressSize=8
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br rom_local_label("stackSwitched")
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ldst t0, hs, [1, t0, t6], \
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32 + %(errorCodeSize)d, dataSize=8, addressSize=8
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br rom_local_label("%(startLabel)s_stackSwitched")
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istStackSwitch:
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%(startLabel)s_istStackSwitch:
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panic "IST based stack switching isn't implemented"
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br rom_local_label("stackSwitched")
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br rom_local_label("%(startLabel)s_stackSwitched")
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cplStackSwitch:
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%(startLabel)s_cplStackSwitch:
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panic "CPL change initiated stack switching isn't implemented"
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stackSwitched:
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%(startLabel)s_stackSwitched:
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##
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@ -130,15 +130,16 @@ stackSwitched:
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# Write out the contents of memory
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st t7, hs, [1, t0, t6], dataSize=8
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%(errorCodeCode)s
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st t7, hs, [1, t0, t6], %(errorCodeSize)d, dataSize=8, addressSize=8
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limm t5, 0, dataSize=8
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rdsel t5, cs, dataSize=2
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st t5, hs, [1, t0, t6], 8, dataSize=8
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st t5, hs, [1, t0, t6], 8 + %(errorCodeSize)d, dataSize=8, addressSize=8
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rflags t10, dataSize=8
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st t10, hs, [1, t0, t6], 16, dataSize=8
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st rsp, hs, [1, t0, t6], 24, dataSize=8
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st t10, hs, [1, t0, t6], 16 + %(errorCodeSize)d, dataSize=8, addressSize=8
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st rsp, hs, [1, t0, t6], 24 + %(errorCodeSize)d, dataSize=8, addressSize=8
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rdsel t5, ss, dataSize=2
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st t5, hs, [1, t0, t6], 32, dataSize=8
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st t5, hs, [1, t0, t6], 32 + %(errorCodeSize)d, dataSize=8, addressSize=8
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# Set the stack segment
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mov rsp, rsp, t6, dataSize=8
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@ -174,7 +175,30 @@ stackSwitched:
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eret
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};
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'''
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microcode = \
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intCodeTemplate % {\
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"startLabel" : "longModeInterrupt",
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"gateCheckType" : "IntGateCheck",
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"errorCodeSize" : 0,
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"errorCodeCode" : ""
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} + \
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intCodeTemplate % {\
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"startLabel" : "longModeSoftInterrupt",
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"gateCheckType" : "SoftIntGateCheck",
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"errorCodeSize" : 0,
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"errorCodeCode" : ""
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} + \
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intCodeTemplate % {\
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"startLabel" : "longModeInterruptWithError",
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"gateCheckType" : "IntGateCheck",
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"errorCodeSize" : 8,
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"errorCodeCode" : '''
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st t15, hs, [1, t0, t6], dataSize=8, addressSize=8
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'''
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} + \
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'''
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def rom
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{
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# This vectors the CPU into an interrupt handler in legacy mode.
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