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X86: Implement the LTR instruction.

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Gabe Black 2009-02-25 10:17:14 -08:00
parent 08f3a126d5
commit aa7bc1be74
2 changed files with 49 additions and 1 deletions
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2
src/arch/x86/isa/decoder/two_byte_opcodes.isa
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@ -94,7 +94,7 @@
0x0: sldt_Mw_or_Rv();
0x1: str_Mw_or_Rv();
0x2: lldt_Mw_or_Rv();
0x3: ltr_Mw_or_Rv();
0x3: Inst::LTR(Ew);
0x4: verr_Mw_or_Rv();
0x5: verw_Mw_or_Rv();
//0x6: jmpe_Ev(); // IA-64

48
src/arch/x86/isa/insts/system/segmentation.py
View file

@ -168,6 +168,54 @@ def macroop LIDT_16_P
wrlimit idtr, t1
};
def macroop LTR_R
{
chks reg, t0, TRCheck
limm t4, 0
srli t4, reg, 3, dataSize=2
ldst t1, tsg, [8, t4, t0], dataSize=8
ld t2, tsg, [8, t4, t0], 8, dataSize=8
chks reg, t1, TSSCheck
wrdh t3, t1, t2
wrdl tr, t1, reg
wrbase tr, t3, dataSize=8
ori t1, t1, (1 << 9)
st t1, tsg, [8, t4, t0], dataSize=8
};
def macroop LTR_M
{
ld t5, seg, sib, disp, dataSize=2
chks t5, t0, TRCheck
limm t4, 0
srli t4, t5, 3, dataSize=2
ldst t1, tsg, [8, t4, t0], dataSize=8
ld t2, tsg, [8, t4, t0], 8, dataSize=8
chks t5, t1, TSSCheck
wrdh t3, t1, t2
wrdl tr, t1, t5
wrbase tr, t3, dataSize=8
ori t1, t1, (1 << 9)
st t1, tsg, [8, t4, t0], dataSize=8
};
def macroop LTR_P
{
rdip t7
ld t5, seg, riprel, disp, dataSize=2
chks t5, t0, TRCheck
limm t4, 0
srli t4, t5, 3, dataSize=2
ldst t1, tsg, [8, t4, t0], dataSize=8
ld t2, tsg, [8, t4, t0], 8, dataSize=8
chks t5, t1, TSSCheck
wrdh t3, t1, t2
wrdl tr, t1, t5
wrbase tr, t3, dataSize=8
ori t1, t1, (1 << 9)
st t1, tsg, [8, t4, t0], dataSize=8
};
def macroop SWAPGS
{
rdval t1, kernel_gs_base, dataSize=8