debug: Move debug_break into src/base

src/arch/alpha/ev5.cc

@@ -35,13 +35,13 @@
 #include "arch/alpha/osfpal.hh"
 #include "arch/alpha/tlb.hh"
 #include "arch/alpha/kgdb.h"
+#include "base/debug.hh"
 #include "base/remote_gdb.hh"
 #include "base/stats/events.hh"
 #include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/thread_context.hh"
-#include "sim/debug.hh"
 #include "sim/sim_exit.hh"
 
 namespace AlphaISA {

src/base/SConscript

@@ -36,6 +36,7 @@ Source('bigint.cc')
 Source('circlebuf.cc')
 Source('cprintf.cc')
 Source('crc.cc')
+Source('debug.cc')
 Source('fast_alloc.cc')
 if env['USE_FENV']:
     Source('fenv.c')

src/base/debug.cc

@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+#include <sys/types.h>
+#include <signal.h>
+#include <unistd.h>
+
+#include "base/cprintf.hh"
+
+void
+debug_break()
+{
+#ifndef NDEBUG
+    kill(getpid(), SIGTRAP);
+#else
+    cprintf("debug_break suppressed, compiled with NDEBUG\n");
+#endif
+}

src/base/debug.hh

@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+#ifndef __BASE_DEBUG_HH__
+#define __BASE_DEBUG_HH__
+
+void debug_break();
+
+#endif // __BASE_DEBUG_HH__

src/cpu/pc_event.cc

@@ -34,12 +34,12 @@
 #include <string>
 #include <utility>
 
+#include "base/debug.hh"
 #include "base/trace.hh"
 #include "config/full_system.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/pc_event.hh"
-#include "sim/debug.hh"
 #include "sim/core.hh"
 #include "sim/system.hh"
 

src/dev/ns_gige.cc

@@ -36,6 +36,7 @@
 #include <deque>
 #include <string>
 
+#include "base/debug.hh"
 #include "base/inet.hh"
 #include "cpu/thread_context.hh"
 #include "dev/etherlink.hh"
@@ -44,7 +45,6 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "params/NSGigE.hh"
-#include "sim/debug.hh"
 #include "sim/host.hh"
 #include "sim/system.hh"
 

src/dev/sinic.cc

@@ -33,6 +33,7 @@
 #include <string>
 
 #include "arch/vtophys.hh"
+#include "base/debug.hh"
 #include "base/inet.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/intr_control.hh"
@@ -40,7 +41,6 @@
 #include "dev/sinic.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/debug.hh"
 #include "sim/eventq.hh"
 #include "sim/host.hh"
 #include "sim/stats.hh"

src/sim/debug.cc

@@ -30,29 +30,17 @@
  */
 
 #include <Python.h>
-#include <sys/types.h>
-#include <signal.h>
-#include <unistd.h>
 
 #include <string>
 #include <vector>
 
+#include "base/debug.hh"
 #include "sim/debug.hh"
 #include "sim/eventq.hh"
 #include "sim/sim_events.hh"
 
 using namespace std;
 
-void
-debug_break()
-{
-#ifndef NDEBUG
-    kill(getpid(), SIGTRAP);
-#else
-    cprintf("debug_break suppressed, compiled with NDEBUG\n");
-#endif
-}
-
 //
 // Debug event: place a breakpoint on the process function and
 // schedule the event to break at a particular cycle

src/sim/debug.hh

@@ -28,16 +28,15 @@
  * Authors: Nathan Binkert
  */
 
-#ifndef __DEBUG_HH__
-#define __DEBUG_HH__
+#ifndef __SIM_DEBUG_HH__
+#define __SIM_DEBUG_HH__
 
 #include "sim/host.hh"
 
 void schedBreakCycle(Tick when);
-void debug_break();
 
 int getRemoteGDBPort();
 // Remote gdb base port.  0 disables remote gdb.
 void setRemoteGDBPort(int port);
 
-#endif // __DEBUG_HH__
+#endif // __SIM_DEBUG_HH__

src/sim/pseudo_inst.cc

@@ -38,6 +38,7 @@
 #include "arch/kernel_stats.hh"
 #include "arch/vtophys.hh"
 #include "base/annotate.hh"
+#include "base/debug.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/quiesce_event.hh"
@@ -49,7 +50,6 @@
 #include "sim/stat_control.hh"
 #include "sim/stats.hh"
 #include "sim/system.hh"
-#include "sim/debug.hh"
 #if FULL_SYSTEM
 #include "sim/vptr.hh"
 #endif